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FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings

1
Padova Neuroscience Center, University of Padua, 35131 Padua, Italy
2
Department of Biomedical Sciences, University of Padua, 35131 Padua, Italy
*
Author to whom correspondence should be addressed.
Digital 2021, 1(1), 34-53; https://doi.org/10.3390/digital1010003
Received: 20 December 2020 / Revised: 25 January 2021 / Accepted: 25 January 2021 / Published: 30 January 2021
Numerous experiments require low latencies in the detection and processing of the neural brain activity to be feasible, in the order of a few milliseconds from action to reaction. In this paper, a design for sub-millisecond detection and communication of the spiking activity detected by an array of 32 intracortical microelectrodes is presented, exploiting the real-time processing provided by Field Programmable Gate Array (FPGA). The design is embedded in the commercially available RHS stimulation/recording controller from Intan Technologies, that allows recording intracortical signals and performing IntraCortical MicroStimulation (ICMS). The Spike Detector (SD) is based on the Smoothed Nonlinear Energy Operator (SNEO) and includes a novel approach to estimate an RMS-based firing-rate-independent threshold, that can be tuned to fine detect both the single Action Potential (AP) and Multi Unit Activity (MUA). A low-latency SD together with the ICMS capability, creates a powerful tool for Brain-Computer-Interface (BCI) closed-loop experiments relying on the neuronal activity-dependent stimulation. The design also includes: A third order Butterworth high-pass IIR filter and a Savitzky-Golay polynomial fitting; a privileged fast USB connection to stream the detected spikes to a host computer and a sub-milliseconds latency Universal Asynchronous Receiver-Transmitter (UART) protocol communication to send detections and receive ICMS triggers. The source code and the instruction of the project can be found on GitHub. View Full-Text
Keywords: digital signal processing; field programmable gate array; spike detection; action potential; multi-unit activity; multi electrode array; brain computer interface; neuroscience digital signal processing; field programmable gate array; spike detection; action potential; multi-unit activity; multi electrode array; brain computer interface; neuroscience
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MDPI and ACS Style

Tambaro, M.; Bisio, M.; Maschietto, M.; Leparulo, A.; Vassanelli, S. FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings. Digital 2021, 1, 34-53. https://doi.org/10.3390/digital1010003

AMA Style

Tambaro M, Bisio M, Maschietto M, Leparulo A, Vassanelli S. FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings. Digital. 2021; 1(1):34-53. https://doi.org/10.3390/digital1010003

Chicago/Turabian Style

Tambaro, Mattia, Marta Bisio, Marta Maschietto, Alessandro Leparulo, and Stefano Vassanelli. 2021. "FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings" Digital 1, no. 1: 34-53. https://doi.org/10.3390/digital1010003

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