FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings
Abstract
:1. Introduction
- A third order Butterworth high-pass Infinite Input Response (IIR) filter with a cutoff frequency of 300 Hz and a Savitzky-Golay smoothing filter [18], fitting the high-pass filtered signal with a second degree polynomial.
- A point-by-point signal energy estimation using the SNEO [19], that aggregates both the frequency and the amplitude of the voltage fluctuations in a series of samples that can be compared with a threshold.
- A novel dynamic threshold per-channel estimation based on the Root Mean Square (RMS) of the SNEO output that accommodates any drift of the probe or changes in the signal quality, that rapidly converges to a firing-independent value close to an ideal threshold based only on the noise energy. The threshold can be adjusted by the user, to open the detection of both the single AP and MUA.
- A post-ICMS blind window of a user-defined duration, to prevent the detection of false positives following the high increase in the signal power due to the artifact induced by the injection of a current.
- The capability to stream the amplitude, the channel, and the timing of each detected spikes via the USB to the host computer, and, simultaneously, via the UART protocol to any other connected device with sub-milliseconds latency. By the UART command, it is also possible to trigger the ICMS set from the host application.
2. Materials and Methods
2.1. Design Algorithms
2.1.1. High-Pass and Savitzky-Golay Filtering
2.1.2. Smoothed Nonlinear Energy Operator and Threshold
2.1.3. Spike Detection and Local Minimum Finder
2.2. Design Implementation
2.2.1. Filter
2.2.2. Savitzky-Golay Fitting
2.2.3. Smoothed Nonlinear Energy Operator
2.2.4. Energy RMS and Threshold
2.2.5. Local Minimum Finder and Spike Output
2.2.6. Software Integration
2.3. Animals and Surgical Procedure
3. Results
4. Discussion
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Appendix A
References
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Mask | 0 | 1 | 2 | 3 | 4 | 5 | 6 |
---|---|---|---|---|---|---|---|
a | 0.9274 | −2.7821 | 2.7821 | −0.9274 | \ | \ | \ |
b | 1 | −2.8492 | 2.7096 | −0.8600 | \ | \ | \ |
SG | −0.0952 | 0.1429 | 0.2857 | 0.3333 | 0.2857 | 0.1429 | −0.0952 |
Coefficients | Rounding Error (%) | ||||||||
---|---|---|---|---|---|---|---|---|---|
0 | 1 | 2 | 3 | 0 | 1 | 2 | 3 | ||
a | 30.388 | −91.163 | 91.163 | −30.388 | 0.0021 | 0.0010 | 0.0010 | 0.0021 | |
b | 32.768 | −93.364 | 88.789 | −28.180 | 0 | 0.0009 | 0.0001 | 0.0008 |
Component | Clock Cycles to Output | Notes |
---|---|---|
Samples preprocessing | 7 | cross-clock and samples format |
High-pass filter | 11 | complete the filter state after 17 |
Savitzky-Golay fitting | 15 | 8 + mask length |
SNEO | 34 | 18 + 4 * k (k = 4) |
Thresholding | 5 | |
Local minimum | 20 | 4 k + 4 (k = 4) |
Samples postprocessing | 4 | writing to output FIFOs |
Threshold estimation 1 | 11 | the square root and eight more cycles are required every samples |
Total | 96 | One hundred and twenty-five cycles are available between the two samples |
Logic | Default | Custom | Increment | Available |
---|---|---|---|---|
Slice register | 8883 | 13,770 | 4887 | 54,576 |
Slice LUT | 17,775 | 23,065 | 5290 | 27,288 |
BRAM16 | 69 | 76 | 7 | 116 |
BRAM8 | 0 | 15 | 15 | 232 |
DSP48A1 | 8 | 19 | 11 | 58 |
This Work | Default | [29] | [24] | [30] | |
---|---|---|---|---|---|
AP detection accuracy (%) | 92 | N/A | 90.7 | 80–96 1 | N/A |
Latency (ms) | ~0.5 | 0.2 | 0.3–0.8 | 1.96 | 0.1 |
Supported channels | 32 | 8 | 8 | 1 | 32 |
Automatic threshold | ✓ | ✗ | ✗ | ✓ | ✓ |
Stimulation artifact dealing | ✓ | ✗ | ✓ | ✗ | ✗ |
MUA detection | ✓ | ~ | ✓ | ✗ | ✗ |
Sorting | ✗ | ✗ | ✗ | ✓ 2 | ✓ 2 |
UDP spike communication | ✓ | ✗ | ✗ | ✗ | ✗ |
Use Intan RHS | ✓ | ✓ | ✓ | ✓ 3 | ✓ 3 |
Code availability | ✓ | ✓ | ✓ | ✗ | ✓ |
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Tambaro, M.; Bisio, M.; Maschietto, M.; Leparulo, A.; Vassanelli, S. FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings. Digital 2021, 1, 34-53. https://doi.org/10.3390/digital1010003
Tambaro M, Bisio M, Maschietto M, Leparulo A, Vassanelli S. FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings. Digital. 2021; 1(1):34-53. https://doi.org/10.3390/digital1010003
Chicago/Turabian StyleTambaro, Mattia, Marta Bisio, Marta Maschietto, Alessandro Leparulo, and Stefano Vassanelli. 2021. "FPGA Design Integration of a 32-Microelectrodes Low-Latency Spike Detector in a Commercial System for Intracortical Recordings" Digital 1, no. 1: 34-53. https://doi.org/10.3390/digital1010003