Design and Experimental Verification of Electric Vehicle Battery Charger Using Kelvin-Connected Discrete MOSFETs and IGBTs for Energy Efficiency Improvement

Abstract

This research investigates the advantages of Kelvin-connected 4-pin discrete transistors, both MOSFETs and IGBTs, in onboard battery chargers for electric vehicles. The study compares the standard 3-pin and the extended 4-pin packages based on averaged data collected from leading manufacturers. The investigation shows significant potential power loss reduction, thermal operation mitigation, and reduced gate-drive oscillation for the 4-pin package. The benefits have been quantified by analysing the operation of actual switches in an automotive battery charger based on Boost-PFC and DC-DC LLC converters. The converters’ practical design demonstrates a procedure for integrating the Kelvin-connected package into the design methodology. The results have been verified experimentally.

1. Introduction

Battery chargers for automotive applications are one of the main onboard sub-systems of electric vehicles. Like all other pieces of electronics, high efficiency, power density, reliability, and ease of thermal management are vital. To fulfil these needs, this study investigates 4-pin Kelvin-connected discrete MOSFETs and IGBTs, which offer advanced characteristics potentially leading to power loss and temperature reductions.

The advantages of Kelvin-connected MOSFETs have been well evaluated with analytical models based on equivalent circuits, supported by experimental verification [1,2,3,4,5]. In [1], the research focuses on the influence of gate-drive resistance on the drain current spike and oscillations during turn-on and turn-off. The importance of minimising parasitic inductance in the gate-drive circuit, which takes advantage of the Kelvin-connected 4-pin package’s full potential, is analysed in [2]. This paper also analyses the effects of external factors, such as PCB layouts and gate-drive elements. The model in [3] includes device and circuit layout parasitics, exploring the effective transconductance during transients. The targeted maximum parasitic common source inductance criterion is $3 \mathrm{n}\mathrm{H}$, as given in [4]. Assuming the above requirements for the package have been implemented, the Kelvin connection can also improve the reverse-recovery phenomenon associated with the body diode, as shown in [5].

Many studies have demonstrated the advantages of the Kelvin-connected 4-pin package by directly comparing it to the standard 3-pin through-hole package [6,7,8,9]. A reliability comparison between the two packages was conducted in [6] with High Electric Field (HEF) and Active Channel Gate Bias (ACGB) tests. The experimental results show that, generally, 3-pin packages are more tolerant to short circuits due to their higher source inductance and resistance. The research demonstrates a disadvantage of Kelvin-connected packages, which must be mitigated by providing over-current protection to ensure the same level of reliability. In a similar case, in [7,8], both packages’ dynamic parameters were compared, and the blanking time of the desaturation protection scheme for the power modules was studied. The parasitic inductances for the standard 3-pin package are in the range of $5–10 \mathrm{n}\mathrm{H}$, while those for the Kelvin package are estimated to be $0.2–1 \mathrm{n}\mathrm{H}$ [8]. The comparison in [9] shows the Kelvin-connected 4-pin advantage over the exact 3-pin counterpart applied in a Boost-PFC converter. The same research also specified the optimal gate-drive resistors for the Kelvin-connected package as 18 Ω, being a trade-off between the oscillations at the gate-drive circuit, EMI, and the transistors’ dynamic performance in that particular case.

The ability to use transistors in parallel is used to increase the current-handling capability. Research in this direction shows that by meeting specific requirements, Kelvin-connected devices could offer some advantages when connected in parallel [10,11,12,13,14]. A passive balancing method applied to Kelvin-connected SiC MOSFETs using a differential mode choke without additional active control was proposed in [10]. The undesirable effect of crosstalk was investigated further in [11], applying techniques for Gate Impedance Regulation (GIR) and Gate Voltage Regulation (GVR). The impact of an asymmetric layout on current balancing was analysed in [12]. It has been shown that current balancing strongly depends on the quality of the gate-drive circuit, particularly the prevention of gate-drive oscillations [13]. For this reason, in [14], additional resistors in the Kelvin circuit were utilised between the emitter and the gate driver, which was demonstrated with 4-pin IGBTs. The study recommends resistors in the range of $0.5–1 \mathrm{\Omega }$ connected in series to the driver.

Additional benefits of the Kelvin connection in both MOSFETs and IGBTs have been objects of research in several studies [15,16,17,18,19,20,21]. In [15], online bond wire fault monitoring was proposed, and with a similar topology [16], it offers short-circuit, overload, and gate-drive protection for high-voltage MOSFET modules. Because such overloads apply significant stress, a comprehensive study on consequent thermal–electrical degradation was undertaken in [17]. Finally, the main benefit of the Kelvin connection—improved dynamic characteristics leading to loss reduction—was shown in [18,19]. These advantages make the Kelvin-connected transistors the right choice for critical automotive applications, as proven in [20,21].

Similar studies have been dedicated to discrete Kelvin-connected IGBTs and SiC MOSFETs. According to the comparison conducted in [22,23,24] and the 4-pin package analysis [25], the switching loss for Kelvin-connected SiC MOSFET is $60\mathrm{\%}$ [23] to $80\mathrm{\%}$ [22] reduced compared to Si IGBTs, reducing the junction temperature by $38\mathrm{\%}$ [23]. Also, a comparison between the 3-pin and 4-pin IGBTs demonstrated an improved power density with the TO-247PLUS package due to the reduced number of paralleled transistors [24]. The expected switching power loss reduction by using IGBTs in a 4-pin package is up to $10\mathrm{\%}$ compared to the identical transistors in a 3-pin TO-247 package [25]. Further power density and efficiency improvements were reported due to IGBTs with TRENCHSTOP technology [26], giving up to $15\mathrm{\%}$ more output current, and these IGBTs are also offered in the TO-247PLUS package. The measurement techniques and protection abilities of Kelvin-connected IGBTs were reported in [27,28,29,30] for discrete packages and modules.

Power density and efficiency are the central requirements for automotive applications, including onboard battery chargers. One of the topologies offering high efficiency is the LLC DC-DC converter, widely used in battery chargers [31,32,33,34,35,36,37,38,39,40,41]. The reported efficiency in [31] is $94.6\mathrm{\%}$ at $2.7 \mathrm{k}\mathrm{W}$, operating with a combination of Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) for light-load operation. The topology is applicable for low-voltage (LV) [31,34,35,36,39,41] and high-voltage (HV) [32,37,38] battery chargers. A similar efficiency of $94.3\mathrm{\%}$ was reported in [32] for a train application charger rated at $25 \mathrm{k}\mathrm{W}$. The switching frequency using SiC MOSFETs can reach $1 \mathrm{M}\mathrm{H}\mathrm{z}$, achieving $95.8\mathrm{\%}$ efficiency over the battery voltage range, as experimentally shown for an $11 \mathrm{k}\mathrm{W}$ charger in [33]. In [35], a frequency range between $91 \mathrm{k}\mathrm{H}\mathrm{z}$ and $110 \mathrm{k}\mathrm{H}\mathrm{z}$ was applied, giving $96.9\mathrm{\%}$ efficiency with a five-level LLC converter. Similar multi-level techniques have been demonstrated with a series–parallel connection of two transformers [37], reducing the size and the core power loss and improving heat dissipation. The same benefits are achievable with an interleaved LLC topology, as shown in [38], giving 95.65% peak efficiency for a converter with 1.5 kW maximum power. A three-phase topology was described in [39]. Optimal transformer design techniques were presented in [40], and the low-voltage output ($28 \mathrm{V}$) with a relatively high output current ($50 \mathrm{A}$) solution was suggested in [41].

The Power Factor Correction (PFC) converter is mandatory for offline chargers [42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57]. The DC-DC topologies used are Boost, semi-bridgeless, and bridgeless. The review in [42] presents their advantages and disadvantages. Many studies report the superior efficiency of bridgeless converters [43,44,45,46,47] based on the Totem-pole topology with GaN HEMTs. However, the circuit is distinguished by increased complexity and price due to the expensive GAN transistors. Therefore, the DC-DC Boost-PFC converter is still preferred for many applications, offering a good quality/price ratio [48,49,50,51,52,53,54,55,56,57].

Although PFC-Boost is a well-known topology, its development and improvement are still in progress. A modification of the PFC-Boost feedback circuit to reduce the compensation capacitor, potentially leading to improved reliability and reduced cost, was suggested in [48]. Further, an overall power factor increase can be achieved by applying variable inductances, for example, ranging from 0.193 mH to 0.951 mH [49]. The potential of the Boost-PFC converter to operate with low Electromagnetic Interference (EMI) was shown in [50], and the reduction in the Total Harmonic Distortion (THD) in the supply current to within industrial standards was shown in [51].

The interleaved Buck–Boost and PFC-Boost topologies [52,53,54,55,56,57,58,59] offer additional benefits, like reduced current and, thermal stress on the power switches, more uniform power loss distribution, and improved reliability. To deploy the full potential of the interleaved circuit, some essential issues must be resolved: equalising current sharing [52]; applying soft commutation [53]; increasing the output voltage range with Buck–Boost operation [54,55]; and improving the light-load operation with a coupled inductor [56]. Nevertheless, an interleaved Boost-PFC converter remains a good choice for an onboard battery charger, as demonstrated in [57]. The general utilisation of Buck–Boost converters is a part of the charging system of the electric drivetrain, as shown in [58,59]

The literature review leads to the following conclusions:

• The advantages of the 4-pin discrete Kelvin-connected MOSFETs [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20] and IGBT [21,22,23,24,25,26,27,28,29,30] are well demonstrated with models and simulations and supported with experiments. The switches were studied individually and are not associated with a specific converter topology. Therefore, their potential contribution to power loss and temperature reduction in a particular topology requires additional study.
• Most battery charger converters are based on a PFC-Boost circuit [42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57], offering a good quality/price ratio and a subsequent LLC [31,32,33,34,35,36,37,38,39,40,41] stage, which is highly efficient due to the ZVS operation. Published results suggest that further improvement could be achieved with Kelvin-connected transistors, but this requires further analytical and experimental investigation. However, no complete study has demonstrated the application of Kelvin-connected discrete IGBTs and MOSFETs in automotive battery chargers.

Based on these conclusions, this research aims to fill the knowledge gap by showing approaches for integrating Kelvin-connected transistors into the Boost-PFC and LLC DC-DC stages in an automotive battery charger, supported by a comparison between the standard 3-pin and Kelvin-connected 4-pin packages. The results quantify the potential benefits by numerically estimating the power loss reduction, temperature decrease, and efficiency improvement. In this sense, the novelty is finding alternative approaches to improving converters based on 4-pin Kelvin-connected TO 247 package transistors, enhancing the battery charger.

The rest of this paper is structured as follows: Section 2 introduces the proposed battery charger architecture and develops the primary mathematical approach to describe the main difference between the two packages; in Section 3 and Section 4, the design of the LLC and PFC-Boost converters are presented, respectively; Section 5 introduces the experimental verification, and the final conclusions are given in Section 6.

2. The Architecture of the Proposed Battery Charger

This part presents the topology of the proposed charger based on discrete Kelvin-connected IGBTs and MOSFETs. Based on 4-lead TO-247PLUS transistors, the potential for power loss reduction, leading to efficiency improvement, is studied analytically, supported by datasheet examples for several off-the-shelf devices.

2.1. The Central Topology of the Proposed Charger

Figure 1 shows the primary circuit of the explored battery charger. This research focuses on two sub-systems: the Boost-PFC DC-DC converter and the LLC DC-DC converter, which operates as a battery charger. As the suggested Kelvin connection benefits apply to the converters’ power parts, control systems and feedback networks are not considered.

The proposed charger comprises the following elements:

• Single-phase input rectifier (not part of this research).
• Boost-PFC converter with three channels. Channel 1: Kelvin-connected IGBT Q1, inductor L1, ultra-fast diode D1, and current sense resistor Rcs1. Channel 2: Q2, L2, D2, Rcs2. Channel 3: Q3, L3, D3, and Rcs3. The Boost capacitor C1 is common for all three parallel channels.
• LLC DC-DC half-bridge converter with Kelvin-connected MOSFETs Q4 and Q5, resonant circuit capacitor C2, transformer with integrated resonant inductor T1, output rectifier ultra-fast diodes D4 and D5, and output filter capacitor C3. The transformer integrates the resonant inductance $L_r$ and magnetised inductance $L_m$.

2.2. Investigation of the Application of Kelvin-Connected Discrete MOSFETs and IGBTs in the Suggested Battery Charger

The primary circuits of the standard 3-pin and Kelvin 4-pin TO-247 packages are shown in Figure 2A and Figure 2B, respectively. The main elements are the driver, the gate-drive resistor (Rg), the gate-drive capacitor (Cd), and the parasitic source inductance (Lsource). The same circuit topology and analysis applies to the IGBTs; therefore, they are not presented separately.

As previously explained, the first package includes the parasitic source inductance, $L_{source}$, as a part of the gate-drive loop, the driver $V_{out}$, $R_g$, $Q1$ gate-source junction, $L_{source}$, and ground GND. The Kelvin source package isolates $L_{source}$ from the gate-drive loop by doubling the source pins. The configuration has the potential to reduce the switching losses by lowering the ON and OFF times and, respectively, the accumulated energies $E_{ON}$ and $E_{OFF}$. This package advantage is first studied analytically based on the main circuit equations and supported numerically with statistical data and specific examples [60,61,62].

In a steady state, the $Q1$ gate-source voltage ($V_{GS}$) can be related to the voltage difference between the gate driver output voltage ($V_{Dr}$) and the voltage drop ($V_{Ls}$) over the $L_{source}$ as follows:

$$V_{GS}=V_{Dr}-V_{Ls},$$

(1)

expressing $V_{Ls}$ with

$$V_{Ls}=L_{source}{\displaystyle \frac{di}{dt}},$$

(2)

which gives the following equation:

$$V_{GS}=V_{Dr}-L_{source}{\displaystyle \frac{di}{dt}}$$

(3)

From the last equation, the $L_{source}$ influence on the ON ($V_{GS.ON}$) and OFF ($V_{GS.OFF}$) gate-source voltages can be expressed as

$$V_{GS.ON}=V_{Dr.ON}-R_G\times I_{G.ON}-L_{source}{\displaystyle \frac{di}{dt}}$$

(4)

$$V_{GS.OFF}=V_{Dr.OFF}-R_G\times I_{G.OFF}+L_{source}{\displaystyle \frac{di}{dt}}$$

(5)

where $I_{G.ON}$ and $I_{G.OFF}$ are, respectively, ON and OFF gate currents through the gate-drive resistance $R_G$, and $V_{Dr.ON}$ and $V_{GS.OFF}$ are ON and OFF gate-drive voltages.

Based on the obtained data [4,8] and the datasheets provided by the manufacturers (Appendix A

Table A1. IGBTs with the 4-pin Kelvin-source TO-247 package, used for the statistical analysis.

Infineon [60]	ON Semiconductor [61]	ST Microelectronics [62]
IPZA65R029CFD7; IPZA60R024P7	FCH023N65S3L4	stw48n60m2-4; stw56n60m2-4
IPZA60R016CM8; IPZ65R019C7	FCH041N65EFL4	stw56n65m2-4; stw57n65m5-4
IPZ60R017C7; IMZA65R030M1H	NTH4L027N65S3F	stw65n023m9-4; stw68n60m6-4
IMZA65R027M1H; IMZA65R027M1H	NTH4L040N65S3F	stw70n60dm6-4; stw70n60m2-4
IMZA65R020M2H; IMZA65R015M2H	NVH4L040N65S3F	stw75n60m6-4; stw75n65dm6-4

and

Table A2. MOSFETs with Kelvin source TO-247 4pin, used for the statistical analysis.

Infineon [60]	ON Semiconductor [61]	ST Microelectronics [62]
IGZ50N65H5; IGZ75N65H5; IGZ100N65H5 IKZ50N65EH5; IKZ75N65EH5; IKZ75N65ES5 IKZA50N65EH7; IKZA75N65EH7; IKZA100N65EH7	FGH4L50T65MQDC50 FGH4L75T65MQDC50 FGH75T65SHDTL4 FGH75T65SQDNL4 FGHL50T65MQDTL4 FGHL75T65MQDTL4	STGW50H65DFB2-4 STGW60H65DFB-4 STGW75H65DFB2-4 STGW100H65FB2-4

), a maximum parasitic inductance of $3\mathrm{n}\mathrm{H}$ is accepted in this design. Following the manufacturers’ recommendations, a PCB parasitic inductance of $30\mathrm{n}\mathrm{H}$ is included in the design procedure in Section 3.

The switching-ON ($t_{on}$) and -OFF ($t_{off}$) times can be distinct for both packages, depending on $L_{source}$ and the transistor transconductance $g_{fs}$, taken to be constant. Therefore, for the 3-pin package, these times are calculated from

$$\begin{array}{ll}{t}_{on}=(R_g\times C_{iss}& + L_{source}\times g_{fs})\times ln({\displaystyle \frac{V_{g.on}-V_{gs.th}}{V_{g.on}-V_{gs.Miller}}})\\ & + C_{rss}\times R_g\times \left({\displaystyle \frac{V_{ds}-V_{gs.Miller}}{V_{g.on}-V_{gs.Miller}}}\right)\end{array}$$

(6)

$$\begin{array}{ll}{t}_{off}=(R_g\times C_{iss}& + L_{source}\times g_{fs})\times ln({\displaystyle \frac{V_{gs.Miller}-V_{g.off}}{V_{gs.th}-V_{g.off}}})\\ & +C_{rss}\times R_g\times \left({\displaystyle \frac{V_{ds}-V_{gs.Miller}}{V_{gs.Miller}}}\right)\end{array}$$

(7)

where $C_{iss}$ is the input capacitance; $C_{rss}$ is the reverse capacitance; $V_{g.on}$ is the gate ON voltage; $V_{gs.th}$ is gate-source threshold voltage; $V_{gs.Miller}$ is the Miller plateau voltage; $V_{ds}$ is the drain-source voltage; and $V_{g.off}$ is gate OFF voltage.

The transconductance $g_{fs}$ is calculated from the ratio $I_D$ between the drain current and the $V_{GS}$:

$$g_{fs}={\displaystyle \frac{I_D}{V_{GS}}}$$

(8)

Equations (6) and (7) expressed for the Kelvin source 4-pin package are written as

$$t_{on}=\left(R_g\times C_{iss}\right)\times ln\left({\displaystyle \frac{V_{g.on}-V_{gs.th}}{V_{g.on}-V_{gs.Miller}}}\right)+C_{rss}\times R_g\times \left({\displaystyle \frac{V_{ds}-V_{gs.Miller}}{V_{g.on}-V_{gs.Miller}}}\right)$$

(9)

$$t_{off}=\left(R_g\times C_{iss}\right)\times ln\left({\displaystyle \frac{V_{gs.Miller}-V_{g.off}}{V_{gs.th}-V_{g.off}}}\right)+C_{rss}\times R_g\times \left({\displaystyle \frac{V_{ds}-V_{gs.Miller}}{V_{gs.Miller}}}\right)$$

(10)

Based on the above Equations (6)–(10), the $P_{ON}$ and $P_{OFF}$ switching power losses are calculated, respectively, from the equations

$$P_{ON}={\displaystyle \frac{I_{avg}\times V_{ds}}{2}}\times t_{on}\times F_{sw}$$

(11)

$$P_{OFF}={\displaystyle \frac{I_{avg}\times V_{ds}}{2}}\times t_{off}\times F_{sw}$$

(12)

where $I_{avg}$ is the average drain current; $F_{sw}$ is the switching frequency. The total switching power loss $P_{sw.loss}$ is the sum of $P_{ON}$ and $P_{OFF}$.

The turn-on energy $E_{ON}$ is determined by the gate-to-source charge $Q_{gs}$, gate-to-drain charge $Q_{gd}$, and gate charge $Q_g$, which are specified in the transistors’ datasheets for a given gate-to-source voltage $V_{GS}$, drain-to-source voltage $V_{DS}$, and drain current $I_D$ as follows:

$$E_{ON}={\displaystyle \frac{Q_{gs}{V}_{gs.Miller}+\left(Q_g+Q_{gs}+Q_{gd}\right)\times \left(V_{GS}-V_{gs.Miller}\right)}{2}}$$

(13)

$E_{OFF}$ determines the loss in the gate discharge of the gate energy $E_G=Q_G\times V_{GS}$ from $V_{GS}$ to zero according to

$$E_{OFF}=E_G-E_{ON}$$

(14)

In zero-voltage switching (ZVS) operation, required for the LLC converter, the gate charge $Q_{Gzvs}$ is expressed as (assumes charges are linearly related to voltage, i.e., constant capacitances)

$$Q_{Gzvs}={\displaystyle \frac{V_{GS}}{V_{GS}-V_{gs.Miller}}}\left(Q_G-\left(Q_{GS}+Q_{GD}\right)\right)$$

(15)

The ZVS On $E_{ONzvs}$ and ZVS Off $E_{OFFzvs}$ energies are

$$E_{ONzvs}={\displaystyle \frac{Q_{Gzvs}\times V_{GS}}{2}}={\displaystyle \frac{\frac{V_{GS}^2}{V_{GS}-V_{gs.Miller}}\left(Q_G-\left(Q_{GS}+Q_{GD}\right)\right)}{2}}$$

(16)

$$E_{OFFzvs}={\displaystyle \frac{\left(V_{GS}^2+V_{gs.Miller}^2\right)\left(Q_G-Q_{GD}\right)-(V_{GS}\times Q_{GS})\left(V_{GS}+V_{gs.Miller}\right)}{2\left(V_{GS}-V_{gs.Miller}\right)}}$$

(17)

And, finally, the total ZVS energy is expressed as

$$E_{zvs}={\displaystyle \frac{\left({2\times V}_{GS}^2+V_{gs.Miller}^2\right)\left(Q_G-Q_{GD}\right)-(V_{GS}\times Q_{GS})\left({2\times V}_{GS}+V_{gs.Miller}\right)}{2\left(V_{GS}-V_{gs.Miller}\right)}}$$

(18)

The above equations are the basis for the 3-pin and 4-pin energy estimations. While leading manufacturers offer such comparisons based only on their products, this research aims at a broader range of data. Figure 3, Figure 4, Figure 5 and Figure 6 show the graphical representation of statistical data collected for multiple 4-pin MOSFETs (Figure 3 and Figure 4) and 4-pin IGBTs (Figure 5 and Figure 6) for the Kelvin-connected transistors, respectively, given in Appendix A Table A1 and Table A2. The above-presented equations are applied to the energies $E_{ON}$ and $E_{OFF}$ (Equations (13) and (14)) and the total power loss calculation (Equations (9)–(12)).

Generally, for Kelvin-connected MOSFETs, the average reduction in $E_{ON}$ is $47.9\%$, and that for $E_{OFF}$ is $65.2\%$, calculated for the current range of $20–30\mathrm{A}$. For the same range, the power loss reduction varies between $8.6\mathrm{W}$ and $17.9\mathrm{W}$ (Figure 4, diagram 3), which gives a $12.5\mathrm{W}$ reduction. The results were calculated for both packages at a switching frequency of $100\mathrm{k}\mathrm{H}\mathrm{z}$.

It must be clarified that the numerical comparison was conducted with hard-switching to demonstrate the benefits of 4-pin packages. In the ZVS operation, the expected loss for the LLC converter will be lower than that depicted in

Table 1. Comparison between the main parameters of 3-pin and 4-pin MOSFETs and IGBTs.

	MOSFET		IGBTs
	IMW65R015M2H TO-247 3-pin	IMZA65R015M2H TO-247 4-pin	STGW80H65DFB TO-247 3-pin	STGW80H65DFB-4 TO-247 4-pin
Times (ns)
${\mathit{t}}_{\mathit{d}\left(\mathit{o}\mathit{n}\right)}$	34	11.6	84	75
${\mathit{t}}_{\mathit{r}}$	21	14.7	52	35
${\mathit{t}}_{\mathit{d}\left(\mathit{o}\mathit{f}\mathit{f}\right)}$	22	22	280	336
${\mathit{t}}_{\mathit{f}}$	8	6.4	31	23
${\mathit{t}}_{\mathit{r}\mathit{r}}$	40.5	21.5	85	112
Energies (µJ)
${\mathit{E}}_{\mathit{o}\mathit{n}}$	825	84	2100	1000
${\mathit{E}}_{\mathit{o}\mathit{f}\mathit{f}}$	191	138	1500	1700
${\mathit{E}}_{\mathit{t}\mathit{o}\mathit{t}}$	1016	222	3600	2700
${\mathit{E}}_{\mathit{r}\mathit{r}}$	88.4	61.6	257	170

. In this case, the Kelvin-connected 4-pin package could benefit the LLC topology, as analysed in [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30], through reduced gate-drive oscillations, improved efficiency due to the reduced timing, and consequently, a stable ZVS operation with reduced $E_{rr}$, leading to lower body diode loss. These assumptions have been verified experimentally, as described in Section 5.

Similarly, the results for Kelvin-connected IGBTs’ $E_{ON}$ show an average reduction of $22.8\%,$ and the $E_{OFF}$ reduction is $14.8\%$, calculated for the range of $20–40\mathrm{A}$. The power loss reduction ranges between $4.6\mathrm{W}$ and $15.7\mathrm{W}$, giving a $10\mathrm{W}$ average result. These results are calculated with a $40 \mathrm{k}\mathrm{H}\mathrm{z}$ switching frequency, typical for an interleaved PFC-Boost converter.

The statistical results can be supported by concrete data for specific transistors; the main datasheet parameters of the two packages are compared in Table 1. The data presented for $t_{d\left(on\right)}$ delay on, $t_r$ rise, $t_{d\left(off\right)}$ delay off, $t_f$ fall, and $t_{rr}$ reverse-recovery times determine the energy values $E_{on}$, $E_{off}$, total energy $E_{tot}$, and reverse-recovery energy $E_{rr}$. The comparison is visualised graphically in Figure 7 for MOSFETs and in Figure 8 for IGBTs. For the transistors considered, the total energy is reduced for the 4-pin Kelvin-connected package MOSFET by $78.2\%$ and, for an IGBT in the same package, by $25\%$.

The results indicate that the lower energy loss for the Kelvin-connected package also reduces the junction temperature. Table 2 shows the thermal parameters for a model based on an equivalent circuit for junction temperature estimation under steady-state conditions (Equations (20)–(23)). Table 3 shows the power loss and junction temperature comparison calculated for certain conditions. The applied thermal model shows a 4-pin MOSFET $T_j$ reduction of $22.1\%$ and 4-pin KE IGBT $T_j$ reduction of $17.8\%$. The total power loss $P_{tot}$ is calculated as a sum of the switching $P_{ON}$ (Equation (11)) and $P_{OFF}$ (Equation (12)) loss, and the conduction loss is

$$P_{cond}=I_D^2\times R_{on}$$

(19)

where $I_D$ is the average drain current, and $R_{on}$ is the drain-to-source on-state resistance.

Table 2. Thermal model equivalent circuit and base equations.

Package	Equivalent Circuit		Equation
		$P_{tot}$—total power at the junction	$T_j=(P_{tot}\times R_{th1})+T_c$	(20)
		$T_j$—junction temperature
		$R_{th1}$—junction-to-case thermal resistance
		$T_c$—case temperature	$T_c=(P_{tot}\times R_{th2})+T_{hs}$	(21)
		$R_{th2}$—case-to-heat-sink th. resistance
		$T_{hs}$—heat sink temperature
		$R_{th3}$—heat-sink-to-ambient th. resistance	$T_{hs}=\left(P_{tot}\times R_{th3}\right)+T_{amb}$	(22)
		$T_{amb}$—ambient temperature
		Total thermal balance	$T_j=(P_{tot}\times \left(R_{th1}+R_{th2}+R_{th3}\right))+T_{amb}$	(23)

Table 2. Thermal model equivalent circuit and base equations.

Package	Equivalent Circuit		Equation
		$P_{tot}$—total power at the junction	$T_j=(P_{tot}\times R_{th1})+T_c$	(20)
		$T_j$—junction temperature
		$R_{th1}$—junction-to-case thermal resistance
		$T_c$—case temperature	$T_c=(P_{tot}\times R_{th2})+T_{hs}$	(21)
		$R_{th2}$—case-to-heat-sink th. resistance
		$T_{hs}$—heat sink temperature
		$R_{th3}$—heat-sink-to-ambient th. resistance	$T_{hs}=\left(P_{tot}\times R_{th3}\right)+T_{amb}$	(22)
		$T_{amb}$—ambient temperature
		Total thermal balance	$T_j=(P_{tot}\times \left(R_{th1}+R_{th2}+R_{th3}\right))+T_{amb}$	(23)

Table 3. Comparison of the power losses and temperatures of 3-pin and 4-pin MOSFETs and IGBTs.

	MOSFET		IGBTs
	IMW65R015M2H TO-247 3-pin	IMZA65R015M2H TO-247 4-pin	STGW80H65DFB TO-247 3-pin	STGW80H65DFB-4 TO-247 4-pin
Datasheet data
${\mathit{R}}_{\mathit{t}\mathit{h}1}$ (°C/W) (datasheet)	0.44		0.32
${\mathit{R}}_{\mathit{t}\mathit{h}2}$ (°C/W) (estimated)	1		1
${\mathit{R}}_{\mathit{t}\mathit{h}3}$ (°C/W) (heat sink selected)	1.5		1.5
Calculated results according to Table 2
${\mathit{P}}_{\mathit{t}\mathit{o}\mathit{t}}$ (W)	27.5	18.4	36.4	27.4
${\mathit{T}}_{\mathit{j}}$ (°C)	120.9	94.2	142.8	117.4
${\mathit{T}}_{\mathit{h}\mathit{s}}$ (°C)	81.2	67.6	94.7	81.2

Table 3. Comparison of the power losses and temperatures of 3-pin and 4-pin MOSFETs and IGBTs.

	MOSFET		IGBTs
	IMW65R015M2H TO-247 3-pin	IMZA65R015M2H TO-247 4-pin	STGW80H65DFB TO-247 3-pin	STGW80H65DFB-4 TO-247 4-pin
Datasheet data
${\mathit{R}}_{\mathit{t}\mathit{h}1}$ (°C/W) (datasheet)	0.44		0.32
${\mathit{R}}_{\mathit{t}\mathit{h}2}$ (°C/W) (estimated)	1		1
${\mathit{R}}_{\mathit{t}\mathit{h}3}$ (°C/W) (heat sink selected)	1.5		1.5
Calculated results according to Table 2
${\mathit{P}}_{\mathit{t}\mathit{o}\mathit{t}}$ (W)	27.5	18.4	36.4	27.4
${\mathit{T}}_{\mathit{j}}$ (°C)	120.9	94.2	142.8	117.4
${\mathit{T}}_{\mathit{h}\mathit{s}}$ (°C)	81.2	67.6	94.7	81.2

3. Design of LLC Converter

The half-bridge LLC converter (Figure 1) design procedure is based on First Harmonic Analysis (FHA), conducted according to the equivalent circuit in Figure 9 [31,32,33,34,35,36,37,38,39,40,41]. The components of the circuit are as follows: $C_r$ is the resonant capacitor; $L_r$ is the resonant inductor; $L_m$ is the magnetising inductance; $C_p$ is the parasitic capacitance referred from the transformer’s primary side and the PCB layout; and $R_{ac}$ is the reflected load resistance.

3.1. Methodology for LLC Converter Design Based on FHA

The methodology for LLC converter design consists of using the main equations to calculate values for the resonant tank and transformer and determine the parameters of the primary-side MOSFETs and secondary-side rectifiers.

In Figure 9, $C_P$ represents the sum of the parasitic drain–source capacitance $C_{DS}$ and parasitic capacitance of the transformer’s primary side, which are usually neglected in conventional design procedures. However, to describe the minimum dead time, $C_P$ should not be neglected, especially when high-voltage, high-power MOSFET transistors are used.

The LLC design methodology is given in Table 4, presenting the main equations applied to the converter design in Section 3.2. The gain G calculated (Equation (32)) versus the normalised frequency $Fx$ (Equation (26)) is depicted graphically in Figure 10. $G_{min}$ and $G_{max}$ are depicted in Figure 11. The gain range determines the switching frequency range. As a product of this, the ZVS region on the primary side is specified, as shown in the exact figure.

Table 4. A design procedure of the LLC DC-DC converter.

Description	Equation	Number
Gain ($\mathit{G}$)	$G\left(Q,m,F_x\right)=\left|{\displaystyle \frac{V_o}{V_{in}}}\right|={\displaystyle \frac{F_x^2(m-1)}{\sqrt{{(m.F_x^2-1)}^2+F_x^2.{(F_x^2-1)}^2.{(m-1)}^2.Q^2}}}$	(24)
Quality factor (Q)	$Q={\displaystyle \frac{\sqrt{L_r/C_r}}{R_{ac}}}$	(25)
Normalised frequency ( ${\mathit{F}}_{\mathit{x}}$)	$F_x={\displaystyle \frac{F_{sw}}{F_r}}$	(26)
Resonant factor ($\mathit{m}$)	$m={\displaystyle \frac{L_p}{L_r}}={\displaystyle \frac{L_r+L_m}{L_r}}$ where $L_p$ is the primary inductance, and $L_r$ is the resonant inductance	(27)
Reflected load resistance ${(\mathit{R}}_0)$	$R_{ac}={\displaystyle \frac{8}{{\pi }^2}}.{\displaystyle \frac{N_{pri}^2}{N_{sec}^2}}.R_0$	(28)
Resonant capacitor ${\mathit{C}}_{\mathit{r}}$	$C_r={\displaystyle \frac{1}{2\pi Q\times F_r\times R_{ac}}}$	(29)
Resonant inductance ${\mathit{L}}_{\mathit{r}}$	$L_r={\displaystyle \frac{1}{{\left(2\pi F_r\right)}^2\times C_r}}$	(30)
Transient function $\mathit{G}\left(\mathrm{j}\mathsf{\omega }\right)$	$G\left(\mathrm{j}\mathsf{\omega }\right)={\displaystyle \frac{V_{out}\left(\mathrm{j}\mathsf{\omega }\right)}{V_{in}\left(\mathrm{j}\mathsf{\omega }\right)}}$	(31)
Gain $\left(\mathit{G}\right)$ including ${\mathit{C}}_{\mathit{p}}$	$\mathrm{G}\left(\mathrm{j}\mathsf{\omega }\right)={\displaystyle \frac{{\mathrm{j}\mathsf{\omega }}^2}{{\mathrm{j}\mathsf{\omega }}^4\frac{{\mathrm{L}}_{\mathrm{m}}{\mathrm{C}}_{\mathrm{p}}}{\mathrm{m}}+{\mathrm{j}\mathsf{\omega }}^3\frac{L_m}{\mathrm{m}.{\mathrm{R}}_{\mathrm{ac}}}+{\mathrm{j}\mathsf{\omega }}^2\left(\frac{{\mathrm{C}}_{\mathrm{p}}{\mathrm{L}}_{\mathrm{m}}{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}}+\frac{1}{\mathrm{m}}+1\right)+\mathrm{j}\mathsf{\omega }\frac{{\mathrm{L}}_{\mathrm{m}}{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}{\mathrm{R}}_{\mathrm{ac}}}+\frac{{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}}}}$ where $\omega =2\mathsf{\pi }\mathrm{f}$; $k_r=1/\sqrt{L_r{.C}_r}$	(32)
ZVS condition	${\displaystyle \frac{\left(L_m+L_r\right).I_{mpk}^2}{2}}\ge {\displaystyle \frac{\left(2.C_p\right).V_{in}^2}{2}}$	(33)
Required minimum gain ${(\mathit{G}}_{\mathit{m}\mathit{i}\mathit{n}})$	$G_{min}={\displaystyle \frac{N_{tr}.{(V}_{outmin}+V_f)}{V_{inmax}/2}}$	(34)
Required maximum gain ${(\mathit{G}}_{\mathit{m}\mathit{a}\mathit{x}})$	$G_{max}={\displaystyle \frac{N_{tr}.{(V}_{outmax}+V_f)}{V_{inmin}/2}}$ where $V_f$ is the voltage drop over the diodes $Dr1$ and $Dr2$	(35)
Input LLC power (${\mathit{P}}_{\mathit{i}\mathit{n}\_\mathit{l}\mathit{l}\mathit{c}}$)	$P_{in\_llc}={\displaystyle \frac{P_{out}}{{\eta }_{llc}}}$	(36)
Minimum input voltage $\left({\mathit{V}}_{\mathit{i}\mathit{n}\_\mathit{m}\mathit{i}\mathit{n}}\right)$	$V_{in\_min}=\sqrt{V_{out\_pfc}^2-{\displaystyle \frac{{2P}_{in\_llc}\times t_{hold\_up}}{C_{out}}}}$	(37)
Primary-side turns ${(\mathit{N}}_{\mathit{p}\mathit{r}\mathit{i}\_\mathit{m}\mathit{i}\mathit{n}})$	$N_{pri\_min}={\displaystyle \frac{N_{tr}(V_{out}+V_f)}{2f_{SWmin}\times G\times ∆B\times A_e}}$	(38)
Transformer turns ratio (${\mathit{N}}_{\mathit{t}\mathit{r}}$)	$N_{tr}={\displaystyle \frac{N_{pri}}{N_{sec}}}$	(39)
RMS primary side $\left({\mathit{I}}_{\mathit{C}\mathit{r}\left(\mathit{R}\mathit{M}\mathit{S}\right)}\right)$	$I_{Cr\left(RMS\right)}={\displaystyle \frac{1}{\eta }}\sqrt{{\left({\displaystyle \frac{\pi I_{out}}{2\sqrt{2}{N}_{tr}}}\right)}^2+{\left({\displaystyle \frac{N_{tr}\left(V_{out}+V_f\right)}{4\sqrt{2}{f}_{r}G\left(L_p-L_r\right)}}\right)}^2}$	(40)
RMS current through each MOSFET ${(\mathit{I}}_{\mathit{d}\_\mathit{r}\mathit{m}\mathit{s}})$	$I_{d\_rms}={\displaystyle \frac{\pi }{4}}\times I_{out}$	(41)

Table 4. A design procedure of the LLC DC-DC converter.

Description	Equation	Number
Gain ($\mathit{G}$)	$G\left(Q,m,F_x\right)=\left|{\displaystyle \frac{V_o}{V_{in}}}\right|={\displaystyle \frac{F_x^2(m-1)}{\sqrt{{(m.F_x^2-1)}^2+F_x^2.{(F_x^2-1)}^2.{(m-1)}^2.Q^2}}}$	(24)
Quality factor (Q)	$Q={\displaystyle \frac{\sqrt{L_r/C_r}}{R_{ac}}}$	(25)
Normalised frequency ( ${\mathit{F}}_{\mathit{x}}$)	$F_x={\displaystyle \frac{F_{sw}}{F_r}}$	(26)
Resonant factor ($\mathit{m}$)	$m={\displaystyle \frac{L_p}{L_r}}={\displaystyle \frac{L_r+L_m}{L_r}}$ where $L_p$ is the primary inductance, and $L_r$ is the resonant inductance	(27)
Reflected load resistance ${(\mathit{R}}_0)$	$R_{ac}={\displaystyle \frac{8}{{\pi }^2}}.{\displaystyle \frac{N_{pri}^2}{N_{sec}^2}}.R_0$	(28)
Resonant capacitor ${\mathit{C}}_{\mathit{r}}$	$C_r={\displaystyle \frac{1}{2\pi Q\times F_r\times R_{ac}}}$	(29)
Resonant inductance ${\mathit{L}}_{\mathit{r}}$	$L_r={\displaystyle \frac{1}{{\left(2\pi F_r\right)}^2\times C_r}}$	(30)
Transient function $\mathit{G}\left(\mathrm{j}\mathsf{\omega }\right)$	$G\left(\mathrm{j}\mathsf{\omega }\right)={\displaystyle \frac{V_{out}\left(\mathrm{j}\mathsf{\omega }\right)}{V_{in}\left(\mathrm{j}\mathsf{\omega }\right)}}$	(31)
Gain $\left(\mathit{G}\right)$ including ${\mathit{C}}_{\mathit{p}}$	$\mathrm{G}\left(\mathrm{j}\mathsf{\omega }\right)={\displaystyle \frac{{\mathrm{j}\mathsf{\omega }}^2}{{\mathrm{j}\mathsf{\omega }}^4\frac{{\mathrm{L}}_{\mathrm{m}}{\mathrm{C}}_{\mathrm{p}}}{\mathrm{m}}+{\mathrm{j}\mathsf{\omega }}^3\frac{L_m}{\mathrm{m}.{\mathrm{R}}_{\mathrm{ac}}}+{\mathrm{j}\mathsf{\omega }}^2\left(\frac{{\mathrm{C}}_{\mathrm{p}}{\mathrm{L}}_{\mathrm{m}}{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}}+\frac{1}{\mathrm{m}}+1\right)+\mathrm{j}\mathsf{\omega }\frac{{\mathrm{L}}_{\mathrm{m}}{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}{\mathrm{R}}_{\mathrm{ac}}}+\frac{{{\mathrm{k}}_{\mathrm{r}}}^2}{\mathrm{m}}}}$ where $\omega =2\mathsf{\pi }\mathrm{f}$; $k_r=1/\sqrt{L_r{.C}_r}$	(32)
ZVS condition	${\displaystyle \frac{\left(L_m+L_r\right).I_{mpk}^2}{2}}\ge {\displaystyle \frac{\left(2.C_p\right).V_{in}^2}{2}}$	(33)
Required minimum gain ${(\mathit{G}}_{\mathit{m}\mathit{i}\mathit{n}})$	$G_{min}={\displaystyle \frac{N_{tr}.{(V}_{outmin}+V_f)}{V_{inmax}/2}}$	(34)
Required maximum gain ${(\mathit{G}}_{\mathit{m}\mathit{a}\mathit{x}})$	$G_{max}={\displaystyle \frac{N_{tr}.{(V}_{outmax}+V_f)}{V_{inmin}/2}}$ where $V_f$ is the voltage drop over the diodes $Dr1$ and $Dr2$	(35)
Input LLC power (${\mathit{P}}_{\mathit{i}\mathit{n}\_\mathit{l}\mathit{l}\mathit{c}}$)	$P_{in\_llc}={\displaystyle \frac{P_{out}}{{\eta }_{llc}}}$	(36)
Minimum input voltage $\left({\mathit{V}}_{\mathit{i}\mathit{n}\_\mathit{m}\mathit{i}\mathit{n}}\right)$	$V_{in\_min}=\sqrt{V_{out\_pfc}^2-{\displaystyle \frac{{2P}_{in\_llc}\times t_{hold\_up}}{C_{out}}}}$	(37)
Primary-side turns ${(\mathit{N}}_{\mathit{p}\mathit{r}\mathit{i}\_\mathit{m}\mathit{i}\mathit{n}})$	$N_{pri\_min}={\displaystyle \frac{N_{tr}(V_{out}+V_f)}{2f_{SWmin}\times G\times ∆B\times A_e}}$	(38)
Transformer turns ratio (${\mathit{N}}_{\mathit{t}\mathit{r}}$)	$N_{tr}={\displaystyle \frac{N_{pri}}{N_{sec}}}$	(39)
RMS primary side $\left({\mathit{I}}_{\mathit{C}\mathit{r}\left(\mathit{R}\mathit{M}\mathit{S}\right)}\right)$	$I_{Cr\left(RMS\right)}={\displaystyle \frac{1}{\eta }}\sqrt{{\left({\displaystyle \frac{\pi I_{out}}{2\sqrt{2}{N}_{tr}}}\right)}^2+{\left({\displaystyle \frac{N_{tr}\left(V_{out}+V_f\right)}{4\sqrt{2}{f}_{r}G\left(L_p-L_r\right)}}\right)}^2}$	(40)
RMS current through each MOSFET ${(\mathit{I}}_{\mathit{d}\_\mathit{r}\mathit{m}\mathit{s}})$	$I_{d\_rms}={\displaystyle \frac{\pi }{4}}\times I_{out}$	(41)

3.2. LLC DC-DC Converter Design Case Study

The foregoing LLC design methodology (Equations (24)–(41)) is for the converter design as a part of the overall battery charger (Figure 1). The transistor’s power loss is considered with ZVS conditions (Equations (15)–(18)) calculated for a Kelvin-connected 4-pin MOSFET. The LLC DC-DC converter design specification and results are presented in

Table 5. LLC input data and design results.

Design Specification
Input Parameters		Output Parameters
Minimum voltage	$350 \mathrm{V}$	Minimum voltage	$200 \mathrm{V}$
Nominal voltage	$400 \mathrm{V}$	Nominal voltage	$300 \mathrm{V}$
Maximum voltage	$420 \mathrm{V}$	Maximum voltage	$400 \mathrm{V}$
Estimated efficiency	0.96	Output power	$3600 \mathrm{W}$
Minimum switching frequency	$75 \mathrm{k}\mathrm{H}\mathrm{z}$	Nominal output current	$12 \mathrm{A}$
Resonant frequency	$100 \mathrm{k}\mathrm{H}\mathrm{z}$
Maximum switching frequency	$150 \mathrm{k}\mathrm{H}\mathrm{z}$
Design parameters
Input power	$3750 \mathrm{W}$	Magnetising inductance	$25.2 \mathrm{\mu }\mathrm{H}$
Transformer turns ratio	0.5	Resonant inductance	$6.4 \mathrm{\mu }\mathrm{H}$
Minimum gain	0.64	Resonant capacitance	$400 \mathrm{n}\mathrm{F}$
Maximum gain	1.93	Nominal resistance	$5.1 \mathrm{\Omega }$
Quality factor	0.88	Peak primary-side current	$26.6 \mathrm{A}$
Resonant current	$31.4 \mathrm{A}$	Maximum output current	$12.5 \mathrm{A}$
Magnetising current at minimum switching frequency	$11.4 \mathrm{A}$	Secondary half-wave current	$8.8 \mathrm{A}$
Magnetising current at nominal switching frequency	$8.5 \mathrm{A}$	Energy accumulated in parasitic capacitors $Cds$ in both transistors	$88 \mathrm{\mu }\mathrm{J}$
Magnetising current at maximum switching frequency	$5.6 \mathrm{A}$	Dead time	$33.3 \mathrm{n}\mathrm{s}$
Selected semiconductors
Primary-side transistors: IMZA65R015M2H (CoolSiC™ 4-pin Kelvin-connected MOSFET)
Secondary-side rectifiers: VS-E5PH7506LHN3

. Figure 12 shows the gain vs. the switching frequency for different resonant factors m (Equation (27)).

The transistor’s power loss under ZVS conditions (Equations (15)–(18)) at 3.6 kW output was evaluated for the selected Kelvin-connected 4-pin MOSFET. The results are as follows: $Q_{Gzvs}=110\mathrm{n}\mathrm{C}$, $E_{ONzvs}=825\mathrm{n}\mathrm{J}$, $E_{OFFzvs}=1032\mathrm{n}\mathrm{J}$, and $E_{zvs}=1.857\mathrm{\mu }\mathrm{J}$. The switching loss at a maximum operating frequency of $150\mathrm{k}\mathrm{H}\mathrm{z}$ will be $0.279\mathrm{W}$. The conducting loss is calculated at $12.74\mathrm{W}$ (Equation (19)), rounding the total loss to $13\mathrm{W}$. Applying the equivalent model (Equations (20)–(23)), the expected temperature allocation will be $T_j=78.2 \mathrm{W}$ and $T_{hs}=59.5 \mathrm{W}$ with the suggested $1.5 \mathrm{C}/\mathrm{W}$ heat sink thermal resistance.

4. The Design of the PFC-Boost Converter

The interleaved PFC-Boost topology chosen (Figure 1) aims to distribute the losses amongst the three channels, reducing the stress on individual devices. The converter is based on 4-pin Kelvin-connected IGBTs.

4.1. Methodology for PFC-Boost Design

The input PFC power $P_{in\_pfc}$ is determined from the required output PFC power $P_{out\_pfc}$, considering the input LLC power calculated in (Equation (36)) $P_{out\_pfc}=P_{in\_LLC}$:

$$P_{in\_pfc}={\displaystyle \frac{P_{out\_pfc}}{{\eta }_{pfc}}}$$

(42)

where ${\eta }_{pfc}$ is the estimated PFC-Boost converter efficiency.

The total output current $I_{out\_pfc}$ is

$$I_{out\_pfc}={\displaystyle \frac{P_{out\_pfc}}{V_{out\_pfc}}}$$

(43)

where $V_{out\_pfc}$ is the output PFC-Boost voltage.

The current through each PFC-Boost channel, considering the number of channels, $N_{ch}$, is given by

$$I_{pfc\_ch}={\displaystyle \frac{P_{out\_pfc}}{V_{out\_pfc}\times N_{ch}}}$$

(44)

The duty cycle $D_{pfc}$ at the maximum output voltage $V_{out\_pfc}$ is calculated from the maximum input voltage $V_{in\_max}$:

$$D_{pfc}={\displaystyle \frac{V_{out\_pfc}-\sqrt{2}{V}_{in\_max}}{V_{out\_pfc}}}$$

(45)

The current ripple ${\mathsf{\Delta }I}_{boost}$ in the Boost inductor at the minimum input voltage, i.e., the worst-case conditions, depends on the duty cycle and the switching frequency as follows:

$${\mathsf{\Delta }I}_{boost}=D_{pfc}\times {\displaystyle \frac{V_{out\_pfc}-\sqrt{2}{V}_{in\_min}}{V_{out\_pfc}}}\times {\displaystyle \frac{1}{F_{sw}}}$$

(46)

The average inductor current $I_{avg\_pfc}$ is calculated at the minimum input voltage $V_{in\_min}$ as follows:

$$I_{avg\_pfc}={\displaystyle \frac{\sqrt{2}{V}_{out\_pfc}}{V_{in\_min}\times {\eta }_{pfc}}}$$

(47)

The inductance of each PFC inductor $L_{pfc}$ must be calculated at a specified ripple factor $K_{rf}$ and switching frequency $F_{sw}$:

$$L_{pfc}={\displaystyle \frac{\sqrt{2}{V}_{in\_min}}{K_{rf}\times I_{avg\_pfc}}}\times {\displaystyle \frac{V_{out\_pfc}-\sqrt{2}{V}_{in\_min}}{V_{out\_pfc}}}\times {\displaystyle \frac{1}{F_{sw}}}$$

(48)

The peak inductor current $I_{Lpk}$ applies to an inductor selection with no core saturation, calculated from

$$I_{Lpk}=I_{avg\_pfc}\times \left(1+{\displaystyle \frac{K_{rf}}{2}}\right)$$

(49)

For a maximum output voltage ripple $V_{pfc\_ripp}$, the minimum capacitance of the output capacitor $C_{out}$ is given by

$$C_{out}>{\displaystyle \frac{I_{out\_pfc}}{2\pi F_{in}{V}_{pfc\_ripp}}}$$

(50)

where $F_{in}$ is the input line frequency.

4.2. PFC-Boost Converter Design Case Study

The interleaved PFC-Boost converter is designed to match the LLC converter (Section 3.2), supplying the necessary input power of $3750\mathrm{W}$, $400\mathrm{V}$. The design results (Equations (42)–(50)) are given in

Table 6. Interleaved PFC design results.

Design Specification
Input Parameters		Output Parameters
Minimum AC voltage	$180 \mathrm{V}$	Nominal output DC voltage	$400 \mathrm{V}$
Maximum AC voltage	$264 \mathrm{V}$	Minimum output DC voltage	$350 \mathrm{V}$
Line frequency	$50 \mathrm{H}\mathrm{z}$	Output power	$3750 \mathrm{W}$
Number of channels	3	Output voltage ripples	$0.05\mathrm{\%}$
Switching frequency	$40 \mathrm{k}\mathrm{H}\mathrm{z}$
Efficiency (estimated)	$92\mathrm{\%}$
Design parameters
Input power	$4076.1 \mathrm{W}$	Duty cycle	0.399
Nominal output DC current	$9.4 \mathrm{A}$	Inductor	$130 \mathrm{\mu }\mathrm{H}$
Current per channel	$3.1 \mathrm{A}$	Inductor peak current at line brownout 160 V	$21.3 \mathrm{A}$
Power per channel	$1250 \mathrm{W}$	Output capacitor	$1500 \mathrm{\mu }\mathrm{F}$
Maximum switch current	$5.2 \mathrm{A}$
Selected semiconductors
IGBT: STGW80H65DFB-4
Fast-recovery diode: VS-E5PH7506LHN3

.

Applying the analytical power loss model (Equations (1)–(14) and (19)) and the thermal model (Equations (20)–(23)), the results for the selected 4-pin Kelvin-connected IGBT are a conduction loss of $0.24\mathrm{W}$, a switching loss of $22\mathrm{W}$, a total loss of $22.24\mathrm{W}$, a junction temperature of $102.73 °\mathrm{C}$, and a heat sink temperature of $95.61 °\mathrm{C}$. As a comparison, the same IGBT with a standard 3-pin connection, based on the data in Table 1, shows a total loss of $31.24\mathrm{W}$ in the same application, leading to a junction temperature of $128.1 °\mathrm{C}$ and a heat sink temperature of $118.1 °\mathrm{C}$. The total power loss dissipated from the three interleaved IGBTs is $93.7\mathrm{W}$ for the 3-pin package and $66.7\mathrm{W}$ for the Kelvin-connected package. Although both packages show satisfactory results, the power loss reduction of $27\mathrm{W}$, or $28.8\%$, shows that 4-pin discrete IGBTs could be preferred for this application.

Further significant power loss reduction could be achieved by applying CoolSiC 4-pin Kelvin-connected MOSFETs. Using the data in Table 1, the standard 3-pin package shows a power loss of $11.1\mathrm{W}$ and a junction temperature of $72.6$ °C, while the 4-pin package dissipates $7.46\mathrm{W}$ and has a temperature of $61.9$ °C. The results show that this approach would allow the interleaved Boost-PFC converter to be completed with only two transistors and a reduced heat sink size for power density improvement. In this case, the Boost PFC was reconstructed with two interleaved MOSFETS (Figure 13A). The comparison of 3-pin (diagram 1) and 4-pin (diagram 2) power losses (Figure 13B) and temperatures (Figure 13C) was conducted with a switching frequency of $66\mathrm{k}\mathrm{H}\mathrm{z}$, according to the ASIC utilised, and a heat sink of $5.5\mathrm{C}/\mathrm{W},$ leading to power density improvement.

5. Experimental Setup

The experimental verification started with testing both packages, 3-pin and 4-pin TO-247, as individual switches, as shown in Figure 2, under the same conditions. The experiments were conducted with standard laboratory equipment, such as a Keysight DSOX1204G oscilloscope, an HMC8015 Rohde & Schwarz power analyser, a power supply, and digital multimeters. The experiments were conducted with both Boost-PFC and LLC converters and the entire battery charger (Figure 1). The measurements were taken for input/output power, efficiency, power loss, transistor junctions, gate driver control signals, and transistor temperature. The converters were tested under nominal and worst-case conditions, applying maximum power at minimum input voltage.

Oscillograms for the 3-pin results are depicted for switch-on (Figure 14A) and switch-off (Figure 14B) as follows: Trace 1 shows the PWM; 2 is the collector–emitter voltage; 3 is the collector current; and 4 is the result of using the mathematical function for power calculation, multiplying the current and voltage, embedded in the oscilloscope. The experiments were conducted with IGBT STGW80H65DFB-4 at a switching frequency of 40 kHz, according to the Boost PFC specified in Table 6.

A comparison of the oscillations in the gate-drive circuit is shown in Figure 15. The voltage over $V_{Ls}$ (Figure 2A) during the 3-pin package switched-on process is shown in Figure 15A, and the voltage over $V_{Lgs}$ (Figure 2B) for the 4-pin package is given in Figure 15B. It must be clarified that the result strongly depends on the board layout.

As a continuation of the previous experiment, the voltage applied to the gate is depicted in Figure 16 with diagram 4. The measurement shows the minimal impact of the Miller plateau for the 4-pin package.

The automotive battery charger has been prototyped and experimentally tested to support the analytical data and the design procedures. Both converter stages were initially tested in general, depicting their operation over the entire charger power range. Eventually, the integrated 4-pin Kelvin-connected operation was tested.

The PFC-Boost converter was tested according to the design described in Section 4.2. The results are presented as follows:

• Figure 17 shows a single channel of the interleaved PFC-Boost converter implemented with three IGBTs, as suggested in the initial design (Table 6). The gate PWM (1) controls the switch with the collector-to-emitter voltage (2) and the collector current (3). The diode conducts the current in the OFF switch state (4).
• Figure 18 shows the input PFC-Boost rectified DC voltage (1) without filtering. The PFC operates by varying the PWM (3) signal according to the input voltage variation and the collector-to-emitter voltage (2), leading to a stable output DC current (4).
• Figure 19 shows the converter operating with the PFC at a nominal load (Figure 19A) and during the charger’s stand-by without the PFC (Figure 19B). The result demonstrates the ability of the converter to correct the power factor in the entire power range.

The LLC converter was tested first to show the ZVS operation with 4-pin Kelvin-connected transistors, according to Figure 1 and the design in the case study in Section 3.2, Table 5. The oscillograms present the following results:

• Figure 20A shows the ZVS operation in which the voltage at the middle point of the half-bridge (3) switches in the dead time between the two transistors’ PWM (1, 2). The current through the resonant capacitor and transformer (4) is depicted under the resonant frequency under output power control. Figure 20B shows the magnetising current (3) on the primary side. Both oscillograms depict the accurate operation of the LLC converter completed with 4-pin Kelvin-connected MOSFETs.
• Figure 21A shows the ZVS in greater resolution, depicting the voltage switching at the zero point (3) between the drain-to-source voltages over the two MOSFETs (1, 2) in the half-bridge. The output DC current is shown in diagram 4. Figure 21B shows the output voltage (1) and current (2) in better resolution as part of the switching process. The output ripples are according to those accepted in the design procedure.

The energy efficiency of the Boost-PFC converter has been experimentally verified. Figure 22A compares the total transistors’ power loss, calculated from the measurement results over the entire power range. Diagram 1 shows the total loss of the three interleaved 4-pin Kelvin-connected IGBTs, and diagram 2 depicts the power loss of their 3-pin counterparts. The difference is shown in Figure 22B. As measured experimentally, the power loss reduction at the nominal rated power of 3750 W is 26.63 W or 8.9 W per transistor in this design. This contributes to a total efficiency improvement of 98% to 98.71% (Figure 23A) or 0.71% (Figure 23B) estimated for the interleaved transistors (Q1, Q2, and Q3, Figure 1).

Temperature rises were investigated using thermal imaging to confirm the power loss reductions. Images from both packages are compared in Figure 24: (A) 4-pin, showing 85.6 °C on the transistor cage, and (B) 3-pin, reaching 101.2 °C. The Kelvin-connected package connected to a heat sink for the presented experiments is shown in Figure 24C.

Figure 25 depicts a thermal image of the entire Boost-PFC power stage with three 4-pin TO-247 IGBTs. The final prototype is completed with heat sinks with a reduced surface, as suggested in the design above. The maximum temperature of the heat sink reaches 114.4 °C.

The LLC converter’s 4-pin MOSFET transistors’ thermal operation, according to the design in Section 3, is shown in Figure 26. The measured heat sink temperature is 53.5 °C versus the calculated temperature of 59.5 °C (Table 5).

The data obtained from the design and experimental measurements are summarised in

Table 7. An experimental comparison between 3-pin and 4-pin IGBTs, with the TO-247 package, used for Boost-PFC design and prototyping.

	3-pin IGBTs			4-pin IGBTs
	Total Loss for Three Interleaved PFC IGBTs (W)	Total Loss per IGBT (W)	Heat Sink/Junction Temperatures (°C)	Total Loss for Three Interleaved PFC IGBTs (W)	Loss per IGBT (W)	Heat Sink/Junction Temperatures (°C)
Calculated	93.7	31.24	118.1/ 128.1	66.6	22.2	95.61/ 102.73
	The total 4-pin package power loss reduction for 3 interleaved PFC IGBTs is 27.1 W. The single-IGBT power loss reduction is 9.04 W.
Measured	75	25	101.2/ 95.6	48.4	16.1	85.6/ 78.5
	The total 4-pin package power loss reduction for 3 interleaved PFC IGBTs is 26.63 W. The single-IGBT power loss reduction is 8.9 W. The junction temperatures are estimated according to package and heat sink temperatures.

. The results mismatch between the two studies is due to the 30% design safety margins applied to the datasheet parameters.

Finally, the Electromagnetic Interference (EMI), measured for the entire charger, is depicted in Figure 27. EMI improvement measures included the PCB design, specifically focused on the gate drivers, the parasitic element reduction enabled by the suggested switches, and proper grounding and shielding.

6. Results and Discussion

The results obtained in the conducted research can be summarised as follows:

• The statistical data collected from multiple 4-pin Kelvin-connected and their 3-pin analogue TO-247 IGBTs and MOSFETs show a power loss reduction for the 4-pin package. The calculations were conducted using Equations (1)–(19) describing both packages’ power losses, and these are depicted graphically (Figure 3, Figure 4, Figure 5 and Figure 6) in the range 20–30 A, consistent with conditions in automotive onboard battery chargers. The results show that the expected power loss reduction obtained by applying Kelvin-connected transistors is between 8.6 W and 17.9 W.
• The same calculations were applied to two specific IGBTs and MOSFETs (Table 1), including thermal models (Table 2) based on the equivalent circuits. The preliminary study shows that it can be expected that a 4-pin Kelvin-connected package offers a power loss reduction, leading to lower junction temperatures (Table 3). The results are obtained due to reduced ON and OFF switching times and, respectively, $E_{on}$ and $E_{off}$ energies, for the Kelvin-connected transistors, as depicted in Figure 7 and Figure 8.
• The 4-pin Kelvin-connected packages were successfully utilised in the design methodology of the Boost PFC (using IGBTs) and the resonant LLC converter (using MOSFETs). The case studies for both converters show that applying Kelvin-connected IGBTs to the interleaved Boost PFC reduces the switching loss. For the LLC converter, CoolSiC 4-pin MOSFETs can be recommended. The experimental study shows the stable operation of the Boost-PFC (Figure 17 and Figure 18) and LLC converters (Figure 20 and Figure 21).
• The experimental study confirms the analytical results, showing a total power loss reduction of 26.63 W, or 8.9 W per transistor, for the three interleaved IGBTs in the Boost-PFC converter. The power loss reduction and efficiency improvement, experimentally depicted in Figure 23 and Figure 24, match the preliminary results presented in Section 2 and shown in Figure 3, Figure 4, Figure 5 and Figure 6.
• Due to the power loss reduction, the heat sink temperature decreases proportionally from 101.2 °C to 85.6 °C, as the infrared images in Figure 22 show. Further temperature reductions, potentially leading to heat sink minimisation and power density improvement, could be achieved by applying SiC 4-pin MOSFET to the Boost-PFC converter (Figure 23 and Figure 24).
• The experimental study also shows fewer gate circuit oscillations in both converters (Figure 15) and stable operation on the gate-drive circuits (Figure 14 and Figure 16). This result leads to acceptable EMI, as depicted in Figure 25.

Based on the presented results, it can be concluded that the 4-pin Kelvin-connected TO-247 transistors are a good candidate for further power loss reduction and efficiency improvement in power converters. In the presented research, such a result was demonstrated in the context of Boost-PFC and DC-DC LLC converters as a part of the automotive battery charger.

7. Conclusions

This research has conducted and presented analytical and experimental studies focused on the Kelvin-connected transistor package and its utilisation in the primary converters of a battery charger topology. The thorough literature review supported and defined the necessity of the presented results. The primary data obtained were used in the following design processes. The central battery charger converters, Boost PFC and DC-DC LLC, were designed with 4-pin Kelvin-connected TO-247 IGBT and MOSFET packages. Finally, the experimental results confirmed the expected power loss reduction and efficiency improvement. Furthermore, both converters showed stable operation with minimised oscillations, improved thermal operation, and power density improvement.