Design and Performance Analysis of Double-Gate TFETs Using High-k Dielectrics and Silicon Thickness Scaling for Low-Power Applications ^†

Abstract

Tunnel Field-Effect Transistors (TFETs) are being explored for ultra-low-power very-large-scale integrated circuits (VLSI) because their band-to-band tunnelling (BTBT) transport permits subthreshold swings (SS) below the 60 mV/dec thermionic limit at room temperature, along with significantly lower leakage than MOSFETs. This paper presents a systematic TCAD study of DG-TFETs that maps how four primary knobs–gate dielectric materials, silicon channel thickness, temperature variation, and different channel material shape key figures of merit: the ON current (I_ON), OFF current (I_OFF), threshold voltage (V_TH), SS, and the I_ON/I_OFF switching ratio. High-k gate enhances gate-to-channel coupling and boost tunnelling efficiency; rigorous body scaling enhances electrostatic control; and targeted source-proximal doping profiles elevate I_ON while minimizing leakage. We also measure the trade-offs between I_ON, SS, and I_OFF that occur when scaling is performed at the same time. This shows that careful coordination is needed instead of just tuning one parameter. This is a simulated work, and the physical models are calibrated to experimental TFET data and all parameters are checked against previously reported results. The device reaches SS = 31.4 mV/dec, V_TH = 0.46 V, I_ON = 5.91 × 10⁻⁵ A and an I_ON/I_OFF of about 4.5 × 10¹¹. This shows that it can switch quickly with little leakage. The design insights that come from this work provide useful advice regarding how to choose gate dielectric material, structures, and doping strategies to add DG-TFETs to the next generation of low-power semiconductor technologies.

1. Introduction

The fabrication industry follows the technology of scaling down the MOS structure towards the nanoscale realms [1]. As MOSFET continues to be small in size and faces fundamental performance limitations, there has been an extended emphasis in introducing modified devices that use band-to-band tunnelling for ON currents [2,3,4,5,6,7,8]. Specifically, attention is given to devices functioning as field-effect transistors (FETs) that utilize tunnelling mechanisms not only in the ON state but also during the transition from OFF to ON. In such devices, the current is controlled by varying the gate voltage. They offer the potential for extremely low OFF-state current and the capability to achieve subthreshold swings below the conventional 60 mV/decade limit of traditional MOSFETs. Among all these, we can consider TFET as one of the most favourable structures to overcome those limits as shown below.

• SS << 60 mV/dec, as TFET is run by tunnelling mechanism through band-to-band tunneling [9];
• I_ON/I_OFF is in order of 10⁹ or more for TFET and it can be obtained at lower V_DD;
• Low leakage current.

Most of the existing literature reports ON currents that are too low to feasibly replace conventional MOSFET technology. Although OFF currents typically fall within the femtoampere or picoampere range, ON currents under drain and gate voltages of 2 V remain restricted to the nanoampere level [10]. For compatibility with CMOS technology, operating voltages should ideally be reduced further, to around 1.2 V. While one study reports ON currents reaching 0.5 mA/µm [11], the devices in question appear to be hybrid rather than purely tunnel-based FETs, as indicated by their constant subthreshold slope, which lacks the expected dependence on gate voltage. Looking at the 2015 ITRS, the Tunnel-FET technology fits best into the low standby power (LSTP). The design presented here, a Double-Gate (DG) device with a high-k gate dielectric, indicates highly promising performance, aligning well with or exceeding the standards set by ITRS 2015 roadmap [12]. The ON current (I_ON) is approximately 59.1 µA, which falls within the ideal range of applications of low power consumption. Meanwhile, the OFF current (I_OFF) is exceptionally low, at 2.68 × 10⁻¹⁶ A (~0.27 femtoamperes). This results in a remarkable I_ON/I_OFF ratio of 2.2 × 10¹¹, far surpassing the typical requirements of 10⁵ to 10⁶ for high-performance devices. The device exhibits a subthreshold swing (SS) of 31.75 mV/dec, which is well below the thermionic limit of 60 mV/dec, highlighting excellent switching characteristics and energy efficiency compared to conventional MOSFET. Additionally, the threshold voltage V_T is 0.469 V, which is within the optimal range for low voltage logic circuits. These results collectively indicate that the TFET structure is highly suitable for ultra-low-power applications such as biosensors; it adheres closely to the performance expectations outlined in the final ITRS roadmap. High-k dielectric materials increase gate capacitance but decrease leakage current, which in turn increases the I_ON/I_OFF ratio. This work investigates the structure of a Tunnel-FET and how it functions in terms of specific output, and discusses different parameters for both MOSFETS and Tunnel-FETs [13]. Subsequently it shows how the design with an optimized silicon body thickness and a high-k gate dielectric with varying temperature results in improved device characteristics in terms of current and subthreshold swing.

2. Device Structure and Simulation Methodology

The physical and material parameters used in the design and simulation of a Double-Gate Tunnel Field-Effect Transistor (DGTFET) structure, as shown in Figure 1a,b, are crucial in defining the electrical characteristics, switching behaviour, and overall performance, particularly in low-power and high-sensitivity applications. The channel length (L_g) is specified as 50 nm with intrinsic region where band-to-band tunnelling occurs in the DGTFET (Figure 1a). This length plays a critical role in balancing tunnelling efficiency and the short channel effect. The silicon film thickness (T_si) is 10 nm, indicating the thickness of the undoped or lightly doped silicon layer that forms the body of the device; this thin channel ensures strong gate control and better electrostatic integrity. At 300 K, the electron mobility of Si is approximately 1350 cm²/V·s and the hole mobility for the same is approximately 480 cm²/V·s. The gate oxide thickness (T_ox) is given as 3 nm, which defines the thickness of the insulating layer between the gate electrode and the channel. The source and drain lengths (L_s and L_d) are each 30 nm. The source region is heavily p-type doped to a concentration of 1 × 10²⁰ cm⁻³, facilitating a high tunnelling rate by creating a strong electric field at the source–channel junction. The drain is n-type, doped at 5 × 10¹⁸ cm⁻³, which is intentionally kept lower than the source doping to suppress ambipolar current and ensure unidirectional tunnelling. The channel doping is relatively light, at 1 × 10¹⁶ cm⁻³, maintaining the intrinsic nature of the channel and allowing for efficient band bending when gate voltage is applied. In terms of dielectric materials, the device uses a high-k gate dielectric, specifically hafnium dioxide (HfO₂), with a dielectric constant (k) of 21. These structural and material parameters form a highly optimized DGTFET design that aims to achieve steep subthreshold swing, low OFF current, and reasonably high ON current, making it a strong candidate for future ultra-low-power electronics and sensitive biosensing applications. All simulations were created in Silvaco Atlas, version 1.8.20 [14]; this version of Atlas shows better physical consistency than older versions, which used a local band-to-band tunnelling (BTBT) model. The simulations use a very detailed meshing across the region where the tunnelling through band-to-band takes place. The positions for the start and end of tunnelling are found for each energy and are used to calculate the current in that energy range. To calculate the tunnelling current, non-local band-to-band tunnelling (BTBT) has been used and also the operation incorporated the band gap narrowing (BGN) model to utilize the highly doped regions in the device. In the simulation, the Shockley–Read–Hall (SRH) and Auger models have been considered to evaluate generation/recombination. Adding to this, the Fermi–Dirac distribution function model and the drift–diffusion carrier transport model are also employed in the simulation. The concentration-dependent mobility mode and also concentration-dependent lifetime is incorporated by conmob and consrh respectively. The Double-Gate TFET devices are found to have properly calibrated transfer characteristics, as is presented in Figure 2, in conformity with experimental values of literature, ensuring the device models are also physically accurate [15].

3. Results and Discussion

3.1. Performance Analysis of DGTFET and DGMOSFET

Table 1. Performance comparison of DGTFET and DGMOSFET.

Device	SS (mV/dec)	Vt (V)	IOFF (A)	ION (A/µm)	ION/IOFF
DGMOSFET	61.1	0.85	1.97 × 10−8	0.011	5.5 × 105
DGTFET	31.4	0.46	2.68 × 10−16	5.91 × 10−5	2.2 × 1011

presents a comparative analysis of the different parameters of a Double-Gate MOSFET (DGMOSFET) and a Double-Gate Tunnel Field-Effect Transistor (DGTFET), emphasizing the fundamental differences in their switching behaviour and current performance. The table shows a relatively gradual transition from OFF to ON states, with a subthreshold swing (SS) of approximately 61.1 mV/dec and a threshold voltage (V_t) around 0.85 V, which aligns with conventional MOSFET performance. In contrast, the DGTFET exhibits a much steeper turn on characteristic, with a significantly lower subthreshold swing of 31.4 mV/dec, indicating its superior capability to switch at lower voltages. The threshold voltage of the TFET is also much lower, at around 0.46 V, demonstrating its suitability for low power applications. Importantly, the DGTFET achieves an impressively high ON/OFF current ratio of approximately 2.2 × 10¹¹, driven by an extremely low OFF current of about 2.68 × 10⁻¹⁶ A and a respectable ON current of 5.91 × 10⁻⁵ A. The energy band diagram of two devices has been presented in Figure 3 to understand the difference between carrier transport mechanism. The transconductance is higher for the DG-MOSFET due to the mechanism of thermionic current, whereas the transconductance is lower but steadily increasing for the DG-TFET due to the mechanism of band-to-band tunnelling. In contrast, as shown in Figure 4, the DGMOSFET exhibits an ON current of 0.011 A and an OFF current of 1.97 × 10⁻⁸ A, leading to an ON/OFF ratio of about 5.5 × 10⁵, which, although acceptable, falls short of the TFET’s performance in ultra-low-power scenarios. These results highlight the DGTFET’s advantages in achieving steeper subthreshold behaviour and dramatically lower OFF currents, which are crucial for energy-efficient electronic circuits, especially in emerging applications such as biosensing. The comparative table thus underscores the potential of DGTFETs as promising candidates to replace or complement conventional MOSFETs in future low-power and high-sensitivity device architectures. Even though the transconductance is lower for the DG-TFET, the device is still beneficial for ultra-low-power devices since the low gate voltage benefits the device.

3.2. Thin Film Structure

Figure 5 illustrates the impact of varying silicon body thickness (T_Si) on the transfer characteristics of a Double-Gate Tunnel Field-Effect Transistor (DGTFET), specifically showing how the drain current (I_D) changes with gate voltage (V_GS). The y-axis is plotted on a logarithmic scale and represents the drain current (I_ds) in amperes, ranging from 10⁻⁴ A down to 10⁻¹⁶ A, which allows for the detailed observation of both ON- and OFF-state current levels across several orders of magnitude. The x-axis represents the gate voltage (V_gs), varying from 0 V to 1.8 V, covering the subthreshold and active operating regions of the device. The plot includes multiple curves corresponding to different silicon body thicknesses, such as t = 5 nm and t = 7 nm. These curves demonstrate how reducing the silicon body thickness significantly affects the tunnelling behaviour and overall performance of the device. From the graph, it is evident that thinner silicon layers, such as T_Si = 5 nm, yield a steeper subthreshold slope and lower OFF current, as the drain current remains extremely low for small gate voltages and increases sharply near threshold. This is due to enhanced gate control over the channel potential in thinner bodies, which helps reduce leakage and enables the stronger modulation of the tunnelling barrier. Conversely, thicker silicon layers result in higher OFF currents and a more gradual increase in current with gate voltage, indicating weaker electrostatic control and reduced energy efficiency.

3.3. Performance Analysis of Different High k Dielectrics

Figure 6 illustrates a comparative analysis of the transfer characteristics (drain current I_D versus gate voltage V_GS) of a Double-Gate Tunnel Field-Effect Transistor (DGTFET) when different high-K dielectric materials are used as the gate insulator. The primary focus is on how these materials influence the device’s electrical performance, especially in terms of the ON-state current (I_ON), subthreshold swing (SS), and threshold voltage (V_TH). Each curve in the plot corresponds to a specific dielectric material such as SiO₂, Si₃N_4, HfO₂ and ZrO₂, each with different dielectric constants (K). As we move from SiO₂ (K ≈ 3.9) to high-K materials like Si₃N₄ (K ≈ 7.5), HfO₂ (K ≈ 21) and ZrO₂ (K ≈ 25), a consistent trend is observed: the drain current increases significantly for a given gate voltage, particularly in the subthreshold and ON regions of the curve. This improvement occurs because higher-K dielectrics enable stronger capacitive coupling between the gate and the channel, which enhances the vertical electric field across the tunnelling junction.

This stronger field promotes more efficient band-to-band tunnelling—the primary carrier injection mechanism in TFETs—thereby increasing the I_ON without a corresponding increase in leakage current. Additionally, the curves for high-K dielectrics show steeper slopes in the subthreshold region, indicating a lower subthreshold swing. A lower SS is highly desirable in low-power electronics as it enables faster switching at lower voltages. Moreover, the threshold voltage (V_TH) appears to shift slightly toward lower values with an increasing dielectric constant, meaning the device can turn on at a reduced gate voltage, further contributing to power efficiency [16]. In contrast, the device with SiO₂ shows the weakest performance, with the lowest drain current, highest SS, and delayed switching characteristics, which are unfavourable for both logic and sensing applications. Devices with high-K dielectrics are more responsive to these subtle changes due to their improved gate control and higher current drive, resulting in better charge sensitivity and enhanced detection capability.

3.4. Effect of Temperature

Figure 7 illustrates the transfer characteristics (I_D–V_GS) of a Tunnel Field-Effect Transistor (TFET) at various temperatures, indicating how the drain current varies with the changes in gate voltage across different thermal conditions. Multiple curves, each corresponding to a distinct temperature, which ranges typically from 200 K to 400 K, reveal that as the temperature increases, the overall drain current rises for any given gate voltage. This behaviour is attributed to the increased thermal energy available at higher temperatures, which enhances band-to-band tunnelling probabilities and results in more thermally excited carriers, thereby elevating both the ON- and OFF-state currents. Notably, in the subthreshold region (low gate voltages), the curves demonstrate a degradation in the subthreshold swing (SS) with increasing temperature, as indicated by the progressively flatter slopes; this means the device becomes less effective at switching between the OFF and ON states, which is undesirable for low-power logic or biosensing applications requiring high sensitivity. This temperature-dependent behaviour is critical in TFET operation, particularly in biosensors, where environmental temperature fluctuations can impact device reliability and sensitivity.

3.5. Effect of Different Channel Materials

Figure 8a,b illustrate the comparative study among the drain current (I_d) and transconductance (g_m) profiles for the Si, Ge, and GaAs-based DG-TFETs under the drain voltage V_ds = 1 V. Based on the graph plotted between the drain current (I_d) and the gate-source voltage (V_gs), the GaAs TFET displays the largest current during the ON-state operation, followed by Ge and Si. This increased current is due to the smaller energy bandgap along with the lower effective mass of the carriers within the Ge [17] and GaAs materials. As a result, the possibility of band-to-band tunnelling within the source–channel junction is higher compared to the Si material. Consequently, the overall turn-on delay as well as the current increase for the GaAs TFET will be sharper than that for the Si material. The graph plotted between the transconductance g_m and the gate-source voltage V_gs clearly verifies the above observation on the performance superiority of the GaAs TFET over the other two materials. At the same time, the Si material displays the least transconductance. At higher gate voltages, transconductance appears to reach saturation or to slightly reduce due to the saturated current during the tunnelling process.

4. Conclusions

This study has shown that the Simulated Tunnel Field-Effect Transistor (TFET) performs better than traditional DG-MOSFETs in context of low-power and high-sensitivity applications, especially biosensing. The DGTFET outperforms the DG-MOSFET by achieving a significantly lower subthreshold swing of 31.4 mV/dec and an exceptionally high I_ON/I_OFF ratio of 2.2 × 10¹¹ through the optimization of structural parameters such as silicon body thickness, gate dielectric materials, and doping concentrations. High-κ dielectrics, such as HfO₂, have been used to further improve gate control and lower leakage currents. The device is a promising candidate for upcoming nano-electronic and biosensing technologies because simulation results using Silvaco Atlas have confirmed its ability to maintain performance consistency under varying physical parameters and temperatures. The DGTFET exhibits itself as a highly efficient, scalable, and thermally stable alternative to traditional MOSFETs, with substantial advantages in switching behaviour and sensitivity crucial for next-generation semiconductor devices.