LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging
Abstract
:1. Introduction
2. LinoSPAD: A Versatile SPAD Line Sensor
2.1. Sensor Architecture
2.2. FPGA Interface Card
2.3. FPGA Architecture
2.3.1. Global Architecture
2.3.2. Clock Architecture
2.3.3. Event Counter Array
2.3.4. TDC Core
2.3.5. Histogram Accumulation
2.3.6. Histogram Processing
2.4. FPGA Implementation
3. LinoSPAD Characterization
3.1. Breakdown Voltage
3.2. Photon Detection Probability (PDP) and Photo Response
3.3. Dark Count Rate (DCR)
3.4. Power Consumption
3.5. TDC Response
3.6. Temperature Effects in SPAD Sensors
3.7. Post-Processing
3.8. Histograms
3.9. Performance Summary and Comparison to other FPGA TDCs
4. Extended Non-Linearity Characterization and Fabrication Variations
4.1. Dead Time and Afterpulsing
4.2. TDC-to-TDC Variation
4.3. Sensor-to-Sensor Variation
4.4. FPGA-to-FPGA
5. Conclusions
Acknowledgments
Author Contributions
Conflicts of Interest
References
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Condition/Supply | VOP (2 Vex) | VDD (3.3 V) | VREG (5 V) |
---|---|---|---|
Darkness | 7 µA | 2.0 mA | 928 mA |
Intense ambient light | ~425 µA | ~600 mA | 1063 mA |
Saturation | ~750 µA | ~0.3 mA | 944 mA |
Parameter | Value |
---|---|
Chip size | 6.8 × 1.68 mm2 |
Technology | 0.35 µm 4 M high-voltage |
Number of pixels | 256 (+8 perpendicular) |
Pixel pitch | 24 µm |
Fill factor | 40% |
Dead time (Vex = 3 V, VQ = 1 V) | 100 ns |
Median DCR (Vex = 3 V, 20 °C) | 5–10 kHz |
Spectral range (Vex = 3 V, PDP > 5%) | 400–775 nm |
Light incidence | ±45° from normal |
Number of TDCs | 64 |
Maximum TDC event rate | 133 MHz/TDC |
Average TDC resolution (LSB) | <25 ps |
TDC range | 28 bit (4.5 ms) |
TDC DNL range, uncorrected | 4 LSB |
TDC DNL range, corrected | 0.2 LSB |
TDC INL range, uncorrected | 7 LSB |
TDC INL range, corrected | 0.5 LSB |
Data transfer rate | 200 MB/s |
LinoSPAD | [19] | [20] | [21] | [32] | [33] | [34] | ||
---|---|---|---|---|---|---|---|---|
Technology | S6 | V5 | V6 | S6 | C | C | A | |
Process | (nm) | 45 | 65 | 40 | 45 | 350 | 130 | - |
# of TDCs | 64 | 1 | 160 | 1 | 1 | 1 | 8 | |
# of channels | 256 | 1 | 160 | 1 | 1 | 1 | 8 | |
LSB Resolution | (ps) | 25 | 17 | 10 | 26 | 0.61 | 1 | 1 |
Event rate | (MHz) | 133 | 300 | 300 | 125 | 0.8 | 10 | 12.5 |
Carry blocks | (TDC−1) | 35 | 50 | 40 | 124 | n/a | n/a | n/a |
Clock frequency | (MHz) | 400 | 300 | 600 | 125 | 200 | 80 | n/a |
DNLpk-pk | (LSB) | 4 | 4.6 | 3 | n/a | 0.5 | 0.8 | 0.04 |
INLpk-pk | (LSB) | 7 | 5.6 | 6 | n/a | 9 | 1.6 | n/a |
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Burri, S.; Bruschini, C.; Charbon, E. LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging. Instruments 2017, 1, 6. https://doi.org/10.3390/instruments1010006
Burri S, Bruschini C, Charbon E. LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging. Instruments. 2017; 1(1):6. https://doi.org/10.3390/instruments1010006
Chicago/Turabian StyleBurri, Samuel, Claudio Bruschini, and Edoardo Charbon. 2017. "LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging" Instruments 1, no. 1: 6. https://doi.org/10.3390/instruments1010006
APA StyleBurri, S., Bruschini, C., & Charbon, E. (2017). LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging. Instruments, 1(1), 6. https://doi.org/10.3390/instruments1010006