Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs
Abstract
:1. Introduction
- We analyze bitstream architecture and formats, to determine the most effective data preprocessing techniques for RNN analysis.
- We utilize dynamic partial reconfiguration with various optimization subroutines, to create a comprehensive data set containing different circuit profiles of benchmark circuits.
- We develop a special preprocessing algorithm that transforms configuration bitstreams into a format suitable for processing by an RNN.
- We demonstrate the effectiveness of using RNN-based supervised learning methods on preprocessed configuration bitstreams, to identify malicious patterns indicative of HTs.
2. Preliminaries
2.1. Hardware Trojan
2.2. Bitstream Architecture
- bus width auto-detection;
- sync word;
- FPGA configuration.
2.3. Recurrent Neural Networks (RNN)
3. Related Work
3.1. Machine Learning Techniques in Hardware Trojan Detection
3.2. HT Detection in FPGA Bitstreams Using Machine Learning
4. Methodology
4.1. Data Set Generation
4.2. Preprocessing FPGA Bitstream for RNN and LSTM Models
5. Results
5.1. Combinational Trojan Detection
- Two bidirectional SimpleRNN layers with 64 and 32 units, respectively, where the first layer processed input sequences bidirectionally, while the second layer processed output sequences bidirectionally.
- Dropout layers with a dropout rate of 0.5 after each SimpleRNN layer, to prevent overfitting.
- A dense output layer with a sigmoid activation function that facilitated binary classification.
- A bidirectional LSTM layer with 64 units/nodes along with a dropout layer with a rate = 0.5;
- A bidirectional LSTM layer with 32 units/nodes along with a dropout layer with a rate = 0.5;
- A dense layer with 1 unit/node and a ’sigmoid’ activation function.
5.2. Case Study: Multi-Tenant FPGA Ring Oscillator-Based Trojan
5.3. Comparison with Relevant Work
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
References
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Steps | Description |
---|---|
1. Input Verilog and XDC file. | Provide the Verilog hardware description language (HDL) file describing the FPGA design and the XDC file containing timing constraints. |
2. Synthesize design. | Convert the Verilog code into a netlist, a low-level representation of the circuit. |
3. Enable dynamic function exchange. | Configure the FPGA to allow for partial reconfiguration. |
4. Perform partial reconfiguration in selected floorplan. | Define the area of the FPGA where the reconfiguration will occur and implement the desired changes. |
5. Generate full bitstream in .bit format. | Create a complete configuration file containing instructions for the entire FPGA, including both static and reconfigured areas. |
Benchmarks | Accuracy | Precision | Recall | F1Score | ||||
---|---|---|---|---|---|---|---|---|
RNN | LSTM | RNN | LSTM | RNN | LSTM | RNN | LSTM | |
c432 | 0.52 | 0.95 | 0.48 | 0.97 | 0.66 | 0.92 | 0.56 | 0.95 |
c499 | 0.49 | 0.88 | 1.00 | 0.81 | 0.74 | 0.98 | 0.85 | 0.88 |
c1355 | 0.64 | 0.98 | 0.71 | 0.96 | 0.49 | 1.0 | 0.58 | 0.98 |
c6288 | 0.44 | 0.93 | 0.00 | 0.96 | 0.00 | 0.92 | 0.00 | 0.94 |
Benchmark | Accuracy | Precision | Recall | F1Score | ||||
---|---|---|---|---|---|---|---|---|
RNN | LSTM | RNN | LSTM | RNN | LSTM | RNN | LSTM | |
c432 | 0.46 | 0.92 | 0.45 | 0.97 | 0.84 | 0.84 | 0.59 | 0.90 |
c499 | 0.49 | 0.93 | 0.49 | 0.97 | 1.0 | 0.88 | 0.66 | 0.93 |
c1355 | 0.60 | 0.93 | 0.61 | 0.93 | 0.60 | 0.93 | 0.61 | 0.93 |
c6288 | 0.41 | 0.96 | 0.39 | 0.94 | 0.20 | 0.91 | 0.26 | 0.92 |
Benchmark | Accuracy | Precision | Recall | F1Score | ||||
---|---|---|---|---|---|---|---|---|
RNN | LSTM | RNN | LSTM | RNN | LSTM | RNN | LSTM | |
c432 | 0.55 | 0.55 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
c499 | 0.56 | 0.93 | 0.54 | 0.97 | 0.60 | 0.88 | 0.57 | 0.93 |
c1355 | 0.49 | 0.91 | 0.00 | 0.93 | 0.00 | 0.89 | 0.00 | 0.91 |
c6288 | 0.44 | 0.82 | 0.00 | 0.94 | 0.00 | 0.80 | 0.00 | 0.70 |
Benchmark | Accuracy | Precision | Recall | F1Score | ||||
---|---|---|---|---|---|---|---|---|
RNN | LSTM | RNN | LSTM | RNN | LSTM | RNN | LSTM | |
c432 | 0.55 | 0.55 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
c499 | 0.51 | 0.51 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
c1355 | 0.49 | 0.49 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
c6288 | 0.47 | 0.47 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 | 0.00 |
Reference Article | Type of IC Used | Feature Selection Needed | Feature Selection | HT Type | Learning Model | Evaluation Metric |
---|---|---|---|---|---|---|
[48] | ASIC | ✓ | Circuit path information | Combinational | LSTM | TPR: 84.00% |
Proposed Method | FPGA | X | Not needed | Combinational | LSTM | Accuracy: 93.50% |
[48] | ASIC | ✓ | Circuit path information | Sequential | LSTM | TPR-99.00% |
Proposed Method | FPGA | X | Not needed | Sequential | LSTM | Accuracy: 91.00% |
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Dofe, J.; Danesh, W.; More, V.; Chaudhari, A. Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs. Cryptography 2024, 8, 36. https://doi.org/10.3390/cryptography8030036
Dofe J, Danesh W, More V, Chaudhari A. Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs. Cryptography. 2024; 8(3):36. https://doi.org/10.3390/cryptography8030036
Chicago/Turabian StyleDofe, Jaya, Wafi Danesh, Vaishnavi More, and Aaditya Chaudhari. 2024. "Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs" Cryptography 8, no. 3: 36. https://doi.org/10.3390/cryptography8030036
APA StyleDofe, J., Danesh, W., More, V., & Chaudhari, A. (2024). Natural Language Processing for Hardware Security: Case of Hardware Trojan Detection in FPGAs. Cryptography, 8(3), 36. https://doi.org/10.3390/cryptography8030036