A Novel PWM Signal-Generation Strategy for Pockels Cell Drivers

Abstract

A Pockels cell driver (PCD) can be viewed as a high-voltage pulse width generator for controlling the bi-refringence effect of electro-optical crystals. The main features of a PCD include a high repetition rate, fast on and off switching, variable pulse duration, and a true square pulse shape. The most commonly used PCD has a narrow pulse width tuning range, typically within a few microseconds. In this paper, we propose a PCD based on a novel pulse width modulation (PWM) signal-generation strategy that can continuously adjust its pulse width with a minimum step size of 10 ns and no restriction on the maximum width. Therefore, it is easily compatible with both “On-type” and “Off-type” applications of the electro-optic crystal quarter-wave voltage. The experimental results show that the rising and falling times of the proposed PCD are approximately 7.3 ns and 7.8 ns, respectively, with a maximum repetition rate of 1 MHz and a maximum voltage of approximately 2.0 kV. Finally, the functionality of the PCD is demonstrated in a home-built slab laser.

1. Introduction

1.1. Description of a PCD

A PCD is a high-voltage pulsed power modulator used to control the bi-refringence of an electro-optical crystal (such as KTP, KD*P, or BBO) in order to drive the polarization direction of the light propagating through the crystal. They are widely used for Q-switching [1,2,3], pulse picking [4,5], cavity damping [6,7] and regenerative amplifier control [8,9,10,11]. Taking Q-switching as an example, Figure 1 shows the optical arrangement of a solid-state laser in two different operating modes [12]. As the arrangement in Figure 1a shows, the PCD uses quarter-wave “Off-type” voltage to keep the resonator closed, and then the voltage switches down to zero and the resonator is opened. On the contrary, the arrangement shown in Figure 1b uses a zero level of control voltage to provide the closed condition of a laser cavity. The resonator is opened by applying a quarter-wave voltage to the electro-optic crystal (called “On-type” voltage). The duty cycle of the high-voltage pulses generated by the PCD varies from application to application. It is difficult for a single product to meet different application requirements, especially to achieve high-precision wide-range pulse width adjustment and to meet a variety of compatibility applications for “On-type” and “Off-type” operations. In this study, we apply a novel PWM signal-generation strategy to the PCD design to address the aforementioned issues.

1.2. Major Factors Affecting PCD Performance

In the past, the majority of the research conducted on PCDs has focused on switching components and topologies, but the control methods, which are extremely significant, have rarely been discussed. We discuss these major factors affecting PCD performance in the following sections.

1.2.1. Switching Components

The characteristics of the switching components are the main factors that determine the performance of a PCD. High-voltage vacuum tubes, such as krytron and thyratron [13,14], were used in the early days; these components can generate pulses with nanosecond rising/falling times, but the repetition frequency is not optimal, and the device is bulky and complex.

The second method uses a bipolar transistor in series [15,16], in order to improve the operating voltage; however, the circuit is complex and the reliability is poor when extreme voltage is required. A nanosecond rising/falling time can also be obtained in this approach. When Marx-configured avalanche transistor circuits [17,18,19] are used, sub-nanosecond edge time can be obtained, but the repetition frequency is low.

A third method is to use metal-oxide semiconductor-field-effect transistors (MOSFET) [20,21,22] or silicon carbide (SiC) MOSFETs [23,24], due to their high breakdown voltage (upper kilovolt), several nanosecond edge time, high repetition rate, and low cost. The performance among the various switching components is presented in

Table 1. Performance of different switch components.

Switching Components	Breakdown Voltage	Switching Speed	Rising/Falling Time	Complexity
Vacuum tubes	high	low	medium	medium
Avalanche transistors	low	medium	fast	high
SiC MOSFETs	medium	fast	medium	low

.

Vacuum tubes are scarcely used today, avalanche transistors can be used to generate sub-nanosecond rising/falling times, and SiC MOSFETs are widely used to generate nanosecond rising/falling times and high repetition rates.

1.2.2. Selection of Topology

Common PCD topologies include the single switch type, the push-pull type, and the full-bridge type. The single switch type is the simplest structure, but Pockels cell voltage recovery relies on RC discharges, which take a long time and are not suitable for Q-switching with high repetition rates [25]. The structure is shown in Figure 2, where VS is the quarter-wave voltage of the Pockels cell (PC).

In the push-pull type shown in Figure 3, one side of the PC is connected to a push-pull circuit, and the remaining side is pulled to GND. In this way, the PC can be rapidly recharged and discharged by the push-pull circuit, enabling extremely high switching frequencies [26,27,28,29].

Figure 4 shows the full-bridge structure with two different power supply modes. The circuits in Figure 4a,b use unipolar and bipolar power supply and can generate unipolar and bipolar voltages, respectively. Clearly, a bipolar supply with half the voltage of a unipolar supply can lessen the stress on insulation and reduce the chances of arcing over to ground.

1.2.3. Control Method

Currently, a push-pull circuit using MOSFETs as the high-voltage switching elements and isolated from the low-voltage control signals $S_1$ and $S_2$ by a transformer is commonly used, as shown in Figure 5.

In order to generate positive pulses of width $T_{pulse}$, it is common practice to drive the upper and lower bridge arms alternately with a time interval of $T_{pulse}$. The resulting sequential waveform is shown in Figure 6a. This control method has two drawbacks:

(1)

The on-time lengths of $Q_1$ and $Q_2$ following the drive signals $S_1$ and $S_2$ are limited to prevent core saturation, which is due to the volt-second product of the gate drive transformers, and this time length is normally on the order of microseconds. When $P_1$ generates a high voltage with $Q_1$ switched on, it gradually decreases due to the leakage current, which limits the maximum width $T_{pulse}$ that can be achieved. In this paper, we propose a recharging method to extend the pulse width. Although this method produces a certain amount of ripple, it can be reduced to a negligible degree by increasing the repetition rate, as shown in Figure 6b.

(2)

In addition, a dead time $T_{dead}$ must be introduced to prevent the upper and lower bridge arms from conducting simultaneously, as shown in Figure 7. For fast MOSFET switching, it is safe to set a dead time interval of at least a few tens of nanoseconds, in which case the minimum width that $T_{pulse}$ can achieve is represented by Equation (1).

$$T_{pulse}=T_{push}+T_{dead}$$

(1)

The effect of dead time can be eliminated by using the full-bridge circuit shown in Figure 8 and the timing control method shown in Figure 9. At time $t_0$, $S_1$ and $S_3$ generate positive pulses, $Q_1$ and $Q_3$ are switched on, and the $P_1$ and $P_2$ are VS with zero $V_{PC}$. Assuming that $T_{dead}=t_2-t_1$, the safety time reserved at $t_3$ is greater than the dead time; $S_2$ generates a positive pulse, $Q_2$ is switched on, and $V_{PC}$ is VS. Then, at time $t_4$, $S_4$ generates a positive pulse, $Q_4$ is switched on, and $V_{PC}$ is zero. Since the time interval between $t_3$ and $t_4$ can be extremely short without dead time constraints, a narrow pulse of width $T_{pulse}=t_4-t_3$ can be generated.

1.3. Introduction of the Proposed PCD with a PWM Signal-Generation Strategy

We propose a novel high-voltage PWM signal-generation strategy and design a PCD with continuously tunable pulse width using the previously mentioned modified push-pull circuit timing control method. This PCD can be applied to Q-switched lasers, pulse pickers, regenerative amplifiers, and other applications by tuning the high-voltage pulse width.

1.3.1. Generation of High-Voltage PWM Signals with Full-Bridge Topology

A PWM signal is a square wave with an adjustable duty cycle whose main parameters include amplitude, frequency, and duty cycle, as shown in Figure 10. A push-pull structure with the aforementioned control methods is commonly used to regulate the frequency and the duty cycle.

We used a bipolar full-bridge circuit consisting of SiC MOSFETs to generate a high-voltage PWM signal with a PC (Pockels cell) as its load, as shown in Figure 11. The advantage of using a bipolar supply is that it reduces the supply voltage by half, thereby lessening the stress on the insulation and reducing the chances of arcing over to ground. In the following section, we present a novel timing control method for continuous modulation of high-voltage pulse widths suitable for Pockels-cell-driven applications.

$$\begin{array}{cc}duty& cycle\end{array}=D=\frac{T_{on}}{T_s}$$

(2)

1.3.2. Applying PWM Timing Control Strategy to the PCD

In this section, we discuss two PWM timing control strategies to implement a PCD: one for generating symmetric positive and negative high-voltage pulses and one for generating unipolar positive high-voltage pulses. Both of these methods can be used to drive a PC.

(1)

Generating symmetric positive and negative PWM signals.

Figure 12 depicts the timing control method for each bridge arm in the case of producing a narrow duty cycle. Each MOSFET is controlled in the same way. In the case of $Q_1$, $S_1$ generates a positive pulse through a 1:1 transformer to turn on $Q_1$, resulting in a voltage of $\frac{VS}{2}$ for $V_{P1}$. To reduce the voltage drop in $V_{P1}$ due to the leakage current, $S_1$ repeatedly generates a positive pulse with period $T_R$ such that $Q_1$ is periodically switched on to maintain the voltage $V_{P1}$. However, in order to eliminate the effect of dead time, the interval between the last pulse of $S_1$ and the first pulse of $S_2$ must be larger than $T_{dead}$. The control patterns of $S_2$ to $S_4$ are the same as those of $S_1$. $V_{P1}$ and $V_{P2}$ behave as square waves with duty cycles of 50 percent, and the delay between them results in $V_{PC}$ generating symmetric positive and negative pulses with width $T_{pulse}$ and period $T_s$.

We can tune the pulse period by changing the on-time length of each bridge arm and the pulse width by adjusting the relative positions of $V_{P1}$ and $V_{P2}$. Figure 13 shows the waveform of $V_{PC}$ after increasing the duty cycle.

(2)

Generating unipolar positive PWM signals.

In order to generate a unipolar positive PWM signal, we can use the timing control method shown in Figure 14. The procedure is as follows: control the left bridge arm so that the length of $V_{P1}$ is $T_H$ for high levels and $T_L$ for low levels, respectively. The process is calculated using the following Equations (3) and (4):

$$T_H=T_s+T_{pulse}$$

(3)

$$T_L=T_s-T_{pulse}$$

(4)

The high- and low-level durations of $V_{P2}$ are opposite of those of $V_{P1}$, and they lag by period $T_s$. In this way, $V_{PC}$ is a positive pulse train, and the pulse width is calculated by Equation (5).

$$T_{pulse}=\frac{T_H-T_L}{2}$$

(5)

According to Equation (5), we can lengthen $T_{pulse}$ by increasing $T_H$ and decreasing $T_L$ while keeping $T_S$ constant. The timing control method is illustrated in Figure 15. It should be noted that during the control of $S_1$ and $S_2$, as well as $S_3$ and $S_4$, a safety distance larger than the dead time should be preserved, which can be implemented easily by using counters.

1.3.3. Features of the Proposed PCD

Compared with conventional PCDs, the circuit and PWM signal-generation strategies described in this paper have the following main advantages:

(1)

High reliability: the proposed circuit uses a bipolar voltage source instead of a unipolar one, which reduces the maximum voltage by half. This can effectively lessen the stress on the insulation and reduce the chances of arcing over to ground, which could otherwise negatively affect the reliability of the system. Moreover, the circuit employs a reasonable timing control method to ensure that the on-off intervals of the upper and lower MOSFETs are longer than the dead time. The dead time is the time interval between turning off one MOSFET and turning on another MOSFET in the same arm of the bridge. If the dead time is too short or even negative, it may cause a short circuit across the DC bus and damage the devices. Therefore, by avoiding this risk, the proposed circuit enhances the reliability of the system.

(2)

Short pulse width: the proposed circuit adopts a novel timing control method that eliminates the effect of dead time on the pulse width. In conventional PCDs, the dead time limits the minimum pulse width that can be generated by the full-bridge circuit. However, in the proposed circuit, the dead time is compensated by adjusting the phase shift between the upper and lower MOSFETs in each arm of the bridge. As a result, the proposed circuit can generate extremely short pulses with a minimum pulse width of only 10 ns.

(3)

Adjustable pulse width: the proposed PWM signal generation strategy is based on the precise phase shift of the two square waves with the same frequency generated by the two pairs of bridge arms of the full-bridge circuit to control. By adjusting the phase difference between these two waves, the proposed strategy can generate PWM signals with continuously adjustable duty cycles. The duty cycle is defined as the ratio of pulse width to pulse period. Theoretically, the duty cycle can be adjusted from 0% to 100%. This means that the proposed strategy can generate pulses with various widths to meet different application requirements.

(4)

High switching speed: the proposed circuit uses transformer-coupled circuits to drive the gate terminals of the MOSFETs. This can reduce the delay time and improve the synchronization between different MOSFETs. In addition, the proposed circuit uses silicon carbide (SiC) MOSFETs as switching components instead of conventional silicon (Si) MOSFETs. SiC MOSFETs have several advantages over Si MOSFETs, such as higher breakdown voltage, lower on-state resistance, faster rising/falling times, and higher switching repetition rates. These advantages enable SiC MOSFETs to achieve higher switching speed and efficiency than Si MOSFETs.

In summary, the proposed circuit and PWM signal-generation strategies have four main advantages over conventional PCDs. First, we use a bipolar voltage source and a reasonable timing control method to reduce the chances of arcing over to ground and avoid short circuit risk, which can improve the system’s reliability. Second, a novel timing control method is employed that compensates the dead time and enables the generation of extremely short pulses with a minimum pulse width of 10 ns, which can enhance the accuracy and flexibility of laser system control. Third, we design a PWM signal-generation strategy that can adjust the duty cycle from 0% to 100%, which can provide various pulse widths for different application scenarios. Fourth, the transformer-coupled circuits and SiC MOSFETs are considered to achieve high switching speed and efficiency, which can reduce the power loss and heat dissipation of the system. Therefore, the proposed circuit and PWM signal-generation strategies are superior to conventional PCDs and can be applied to various fields that require precise control of laser systems.

2. Design and Implementation

In this section, we present our design of a PCD with the PWM signal-generation strategy mentioned above. The design specifications are shown in

Table 2. Design specifications of the PCD.

Parameters	Values
Maximum pulse voltage	2.0 kV
Rising/falling time	<10 ns
Maximum frequency	1 MHz
Minimum pulse width	10 ns
Maximum pulse width	no limitation
Adjustable pulse step	10 ns

.

2.1. System Block Diagram and Topology

As shown in Figure 16, the PCD mentioned above is divided into two main parts. The timing control circuit on the left uses the PWM signal-generation strategy to generate the timing control signals that drive the four bridge arms. The MOSFET drive circuit on the right is used to convert the low-voltage control signal into high-voltage high pulses with adjustable frequency and pulse width.

2.1.1. MOSFET Driving Circuit

A classical transformer-coupling scheme is used to implement the MOSFET driver circuit, as it has negligible latency and can operate across higher potential differences. The primary winding of the transformer is driven by a fast MOSFET driver with low propagation delay and fast rising/falling times. Each bridge arm consists of two MOSFETs in series for increased voltage stress, driven by a 1:1:1 transformer.

2.1.2. Timing Control Circuit

As shown in Figure 17, The timing control of the PCD is conducted using a complex programmable logic device (CPLD, Intel 5M240ZT100C5N), fed by a 100 MHz oscillator (EPSON SG-8018CB-100MHz). Parameters are set to registers via SERIAL_BUS. Configuration logic, pulse generator, frequency and width registers are modules inside the CPLD. The configuration logic loads the input data into the frequency and width registers after serial-to-parallel conversion. The register has a bit depth of 24 bits and can be reconfigured as needed during design. The pulse generator then generates timing control signals $S_1-S_4$ based on these two parameters, the working principle of which is described in detail in the next paragraph.

2.2. PWM Timing Control Method

The principle of the PWM signal-generation strategy was described in the previous section. As an example, in this section, we describe the implementation of the timing control method for generating symmetric positive and negative pulses.

In order for $V_{PC}$ to generate a pulse with period $T_S$ and width $T_{pulse}$, all that is required is for $V_{P1}$ and $V_{P2}$ to generate a square wave with period $2T_s$ and duty cycle 50%, and for $V_{P2}$ to delay $T_{pulse}$ relative to $V_{P1}$, as shown in Figure 12.

We adopt an approach where the timing of $S_1-S_2$ and $S_3-S_4$ is controlled by two state machines, ST-P1 and ST-P2, respectively, as shown in Figure 18. There are five states—STS_DY, STS_HIGH, TD1, TD2, and STS_LOW— each of which is controlled by a counter. When the current state counter is completed, it jumps to the next state. Given the period $T_s$, the pulse width $T_{pulse}$, and the dead time $T_{dead}$, the counting values of the five states can be calculated as follows.

• Duration of STS_DY: CNT_DY = $T_{pulse}$;
• Duration of STS_HIGH: CNT_HIGH = $T_s-T_{dead}$;
• Duration of STS_LOW: CNT_LOW = $T_s-T_{dead}$;
• Dead time is $T_{dead}$: CNT_DEAD = $T_{dead}$ = 50 ns;
• High-level duration of $V_{P1}$ and $V_{P2}$:$T_{VPH}$ = $T_s$;
• Low-level duration of $V_{P1}$ and $V_{P2}$:$T_{VPL}$ = $T_s$.

First, in the ST-P1 state machine, STS_HIGH and STS_LOW control $S_1$ and $S_2$, respectively, to generate pulses with period $T_R$. Second, in the ST-P2 state machine, STS_DY and STS_HIGH control $S_3$ to generate pulses with period $T_R$, and STS_LOW controls $S_4$ to generate pulses with period $T_R$. Finally, all control-signal-generated pulses are forbidden in the TD1 and TD2 regimes. The effect of dead time is avoided by the timing control method described above for $S_1-S_4$, and the resulting waveforms for $V_{PC}$ with adjustable frequency and pulse width are shown in Figure 19.

2.3. Selection of Switches and Discrete Components

As mentioned above, switching devices are the main factors affecting the PCD performance, and SiC MOSFETs are preferred because of their high-voltage stress, fast rising/falling times, and low cost, and they can be used to design PCDs with simple circuit structures. As shown in Figure 16, four CREE SiC MOSFETs C3M0350120D were used in this design, and the main parameters are shown in

Table 3. Main parameters of C3M0350120D.

Parameters	Values
Vds (br)	1200 V
Vgs (th)	2.5 V
Qg	19 nC

. The resistors $R_1-R_8$ (100 $\Omega$) provide low impedance channels to release the gate charge.

Gate drive transformers are widely used to drive high-voltage circuits. High-voltage gate drive ICs are smaller and more convenient, but they have significant turn-on and turn-off delays and lower insulation voltages than transformers. Therefore, we used gate drive transformers made with manganese-zinc ferrite magnetic rings. The turn ratio is 1:1:1, and the inductance is approximately 10 μH.

2.4. Transformer-Coupled Gate Drive Circuits

In order to increase the switching speed of the SiC MOSFETs, the transformers are driven by ultrafast low-voltage MOSFET drivers (IXDN614 $U_1-U_4$), which can source and sink 14 A of the peak current. The coupling capacitors $C_1-C_4$ must be placed in series with the primary winding of the transformers to provide the reset voltage for the magnetizing inductance.

The capacitances of $C_1-C_4$ are calculated by the following Equation (6) [30].

$$C_C=\frac{Q_G}{\Delta V_C}+\frac{V_{DRV}\times \left(1-D\right)\times D}{\Delta V_C\times R_{GS}\times f_{DRV}}$$

(6)

$C_C$: Coupling capacitance;

$Q_G$: Total gate charge, 19 nC;

$V_{DRV}$: Output voltage of IXDN614, 18 V;

$f_{DRV}$: Switching frequency, $<{10}^6$ Hz;

D: Duty cycle at $f={10}^6$ Hz, $0.2$;

$\Delta V_C$:Voltage ripple across $C_C$, $V_{DRV}\times 1\%$;

$R_{GS}$: Gate to source resistor, 100 $\Omega$.

$C_C=\frac{19\times {10}^{-9}}{0.01\times 18}+\frac{18\times \left(1-0.2\right)\times 0.2}{0.01\times 18\times 100\times {10}^6}\approx 105.6\times {10}^{-9}+160\times {10}^{-9}\approx 265.6$ nF

Therefore, $C_1-C_4$ were determined to be 470 nF by taking into account the sufficient margin.

As the primary winding of the isolation transformer can be equivalently viewed as an inductor L and can form an L-C resonator with the coupling capacitor, the resistors $R_9-R_{12}$ should be inserted in series with $C_1-C_4$, respectively, to damp this L-C resonance. The values of $R_9-R_{12}$ are shown in Equation (7).

$$R_C\ge 2\times \sqrt{\frac{L_M}{C_C}}\approx 10\Omega$$

(7)

3. Experiment Results

3.1. Experiment Setups

We use the experimental setup shown in Figure 20 to test the performance of the PCD, which directly drives a PC (BBO Pockels cell, 6.7 pf, 2.03 kV). Five additional instruments are included in the block diagram, including a power supply PCD-HV-250 (250 W, 1.0–3.0 kV) to provide high voltage, a cooling system (MPS-1500A-22) to cool the MOSFETs, an oscilloscope HDO4035 (350 MHz, 2.5 GS/s), and two single-ended probes PPE6KV-A (500 MHz, 2.8 pF, 1 kV RMS) to record the pulse waveforms. A Q-switched slab laser is also used to demonstrate the function of the PCD.

3.2. Small Duty Cycle Test

Figure 21 shows a positive short pulse with a width of 50 ns and a duty cycle of 0.005%. The rising and falling times were approximately 7.3 ns and 7.8 ns, respectively, with a repetition rate of 1 kHz and an amplitude of approximately 2.0 kV. Channels $C_1$ and $C_2$ show the waveforms of $V_{P1}$ and $V_{P2}$, channels $C_3$ and $C_4$ show the waveforms of $S_1$ and $S_3$, and channel $F_1$ shows the waveform of $V_{P1}-V_{P2}$. Since $V_{P1}$ and $V_{P2}$ are controlled by $S_1$ and $S_3$, respectively, the width of $F_1$ is determined by the delay between $S_1$ and $S_3$. It also can be adjusted by shifting their relative positions. The delay between $S_1$ to $V_{P1}$ and $S_3$ to $V_{P2}$ is caused by the MOSFET driver circuit.

As shown in Figure 22, channels $C_3$ and $C_4$ are changed to $S_2$ and $S_4$, respectively. After one cycle, $S_2$ and $S_4$ generate pulses successively, and $V_{P1}$ and $V_{P2}$ then switch from positive to negative voltages and generate pulses with widths which is equal to the phase delay of $V_{P1}$ and $V_{P2}$ represented by $V_{P2}$ − $V_{P1}$.

The recharging method is shown in Figure 23, where the display window is adjusted to 500 us/div, channels $C_3$ and $C_4$ are changed to $S_1$ and $S_2$, respectively, and channel $F_2$ displays the waveform |$V_{P1}-V_{P2}$|. $S_1$ and $S_2$ are periodic pulses with a frequency of 50 kHz and a width of 200 ns, which proved to be a suitable set of parameters to control the high and low levels of $V_{P1}$. We can also see ripples on $V_{P1}$ and $V_{P2}$ caused by repeated charging. $V_{P2}$ is controlled by $S_3$ and $S_4$ in the same way and is not shown in the figure.

Figure 24 is a zoomed-in version of Figure 23. Although $S_1$ and $S_2$ are signals that control the opening of the upper and lower arms of the full bridge circuit, respectively, the time interval between them can not damage the SiC MOSFETs as long as it is larger than the dead time. We do this by adding a protected region equal to the dead time at the end of each period. In this protected region, the pulses generated by $S_1$ and $S_2$ are canceled.

Finally, to precisely demonstrate the pulse width adjustment function, we capture five data sets using an oscilloscope and plot them on a single figure for comparison. Figure 25 shows high-level pulses with widths extending from 10 ns to 50 ns in 10 ns steps.

3.3. Fifty Percent Duty Cycle Test

In Figure 26, channels $C_3$ and $C_4$ are changed to $S_1$ and $S_3$, respectively, which control $V_{P1}$ and $V_{P2}$ to switch from low level to high level and produce a phase shift of 90 degrees. The channel $F_2$ displays the waveform of |$V_{P1}-V_{P2}$|, which shows a square waveform with a width of 500 us and a duty cycle of 50% at a frequency of 1 kHz and an amplitude of approximately 2.0 kV. $S_2$ and $S_4$ control $V_{P1}$ and $V_{P2}$ to switch from high level to low level, respectively, which are shown in Figure 27.

3.4. Large Duty Cycle Test

Figure 28 shows the waveform of a negative pulse with a width of 50 ns and a large duty cycle of 99.995%. The rising and falling edges are approximately 7.6 ns and 7.5 ns, respectively, with 1 kHz frequency and approximate 2.0 kV amplitude. $S_1$ controls $V_{P1}$ to switch from low level to high level and $S_4$ controls $V_{P2}$ to switch in the opposite direction, and the delay between the two causes |$V_{P1}-V_{P2}$| to generate a low pulse. The pulse width can be changed by adjusting the delay time between $S_1$ and $S_4$. In addition, Figure 29 shows that $S_2$ and $S_3$ can be used in a similar way to generate a low pulse in the next cycle.

We captured five data sets via an oscilloscope in the same way and plotted them on a figure for comparison. Figure 30 shows low pulses with widths extending from 10 ns to 50 ns in 10 ns steps.

3.5. High-Repetition-Rate Test

Figure 31 shows the waveform with a repetition rate of 1 MHz and an operating voltage of approximately 2.0 kV. Due to the high switching loss of MOSFETs, a cooling system is required for heat dissipation. $S_1$ and $S_3$ control the switching of $V_{P1}$ and $V_{P2}$ from low to high levels, and the delay between the two causes |$V_{P1}-V_{P2}$| to generate high pulses. As shown in Figure 32, $S_2$ and $S_4$ control $V_{P1}$ and $V_{P2}$ to switch in opposite directions and cause |$V_{P1}-V_{P2}$| to generate pulses in the next cycle. When the PCD is operated at a high repetition rate, the duty cycle is controlled in the same way as for the 1 kHz repetition rate. Figure 33 and Figure 34 show waveforms with duty cycles of 1% and 99%, respectively. Moreover, when the repetition rate is larger than 50 kHz, $S_1$–$S_4$ does not need to generate periodic repeated charging pulses. The 0% and 100% duty cycles can be obtained by generating uninterrupted 50 kHz pulses from $S_1$, $S_3$ and $S_1$, $S_4$, respectively. Thus, this is true for all output frequencies of the PCD.

3.6. Power Loss Test

The PCD power loss is dominated by the power consumed in the PC $P_{PC}$, the switching loss of SiC MOSFETs $P_{SW}$ and the power loss of the control circuits $P_{CTRL}$. The PC can be regarded as an equivalent capacitor $C_{PC}$, so $P_{PC}$ is given by the following equation (8).

$$P_{PC}=\frac{1}{2}\times C_{PC}\times V{S}^2\times f_{sw}$$

(8)

Where VS is the quarter-wave voltage and $f_{sw}$ is the switching frequency. The PC used in this work has an equivalent capacitance of about 6.7 pF and a quarter-wave voltage VS of about 2030 V. As an example, at $f_{sw}$ of 1 MHz, $P_{PC}$ = 13.4 W. The remaining two power losses are difficult to estimate accurately.

In fact, we can obtain the power consumption of these three parts by measuring the power consumption of the low-voltage supply and the power consumption of the high-voltage supply with and without PC load. The results of the test are shown in Figure 35. For a high-voltage pulse of 2.0 kV, the power consumption of the three parts varies almost linearly with frequency. The maximum power consumption of $P_{SW}$, $P_{PC}$, and $P_{CTRL}$ is about 202.4 W, 14.2 W, and 5.7 W, respectively, when operating at 1 MHz. $P_{CTRL}$ has a static power consumption of about 0.6 W. As a result, the calculated power efficiency is rather small, about 6.4% at an operating voltage of 2.0 kV and a repetition frequency of 1 MHz, which are also shown in Figure 36.

3.7. PCD Test in a Slab Laser

Figure 37 shows a photograph of the developed PCD, including a high-voltage bipolar power supply. We verify the function of this PCD in a home-built slab laser operating in the “Off-type” mode. The quarter-wave voltage of the PC is approximately 2.03 kV.

In Figure 38, the PCD and HV supply modules are measured approximately 4.5” × 3.0” and 4.5” × 2.0”, respectively, for easy installation in the electronic compartment. The Q-switched high-voltage signal is wired through the substrate to the PC mounted in the optical compartment. The HV supply module (PCD-HV-08) is a low-power version of about 8 W. Since the slab laser uses water cooling, the MOSFETs are mounted against the substrate, indicating that the PCD can share a large chiller in the laser system.

The PCD generates waveforms with a duty cycle of 99%, a low-level width of 1 μs, and a repetition rate of 10 kHz. A 1064 nm laser pulse with a width of approximately 11.0 ns and a power of 100 W was obtained, and the waveform is shown in Figure 39.

4. Conclusions

In this paper, we presented a novel PWM signal-generation strategy applied to a transformer-coupled, bipolar-power-supplied SiC MOSFET-switched full-bridge circuit. By using this strategy to control the timing of the primary winding of the transformer, the effect of dead time is removed, and the limitation of the volt-second product of the transformer on the width of the drive signal is resolved. Compared with existing products, this PCD has the advantage of producing continuously tunable pulses with a step of 10 ns, and there is no restriction on the maximum width, which allows it to be widely used in Q-switched lasers, pulse pickers, and regenerative amplifiers. The experimental results show that the circuit has a rising time of approximately 7.3 ns and a falling time of approximately 7.8 ns, with a maximum voltage of approximately 2.0 kV, and a maximum repetition rate of 1 MHz.