Integrated Zeta–Ćuk-Based Single-Phase DC/AC Inverter for Standalone Applications

Abstract

Power electronics has significantly contributed to advances in developing single-stage integrated converter topologies, enabling DC/AC conversion with voltage step-up capability in a compact and efficient structure. This work proposes a novel Integrated Zeta–Ćuk Inverter (IZCI), derived from combining the Zeta and Ćuk DC/DC converter structures. In addition, the proposed topology achieves high efficiency and full utilization of the input voltage. A potential application for the IZCI topology involves DC microgrids, in which the proposed topology can supply AC local loads, achieving high power quality, such as a low total harmonic distortion (THD). The IZCI operates in discontinuous conduction mode (DCM), exhibiting three distinct operating stages for each switching period. The DCM operation guarantees a linear relationship between output and duty cycle, simplifying the control strategy and requiring fewer sensors, thereby reducing the cost and processing requirements. The feasibility and performance of the IZCI topology are evaluated and validated through experimental results in a standalone application. The results demonstrate high energy conversion efficiency and reliability, providing an AC output voltage with low harmonic distortion.

1. Introduction

Experts consider renewable energy sources inexhaustible because they continuously regenerate during use. The most prominent sources are hydro, solar, wind, biomass, geothermal, and ocean energy [1]. In addition to being naturally replenished resources, renewable sources are also recognized for their low greenhouse gas (GHG) emissions, which characterize them as clean energy alternatives [2].

In light of the growing global effort to mitigate environmental impacts and promote a more sustainable energy matrix, renewable energy sources (RES) have gained increasing prominence, especially in conjunction with distributed generation (DG). Brazil stands out for its predominant use of RES, with particular emphasis on photovoltaic (PV) solar energy, which has been growing significantly in this scenario in recent years, resulting in lower GHG emissions and aligning with global efforts to reduce the environmental impact of fossil fuel-based power generation [3,4,5].

Current forms of energy generation require appropriate processing of the generated electrical power to enable its integration into various applications, such as battery energy storage systems (BESS) and distribution networks [4,5,6,7,8,9]. Power converters primarily perform this processing and act as the interface between direct current (DC) sources and alternating current (AC) loads [10,11].

In this context, recent advances in technologies applied to power electronics have significantly contributed to developing new static converter topologies, characterized by higher efficiency, flexibility, and performance, thereby expanding their potential for application in various technological scenarios [4,5,6,7,8,9,10,11,12].

In the current energy transition context, it is also essential to highlight microgrids, systems composed of distributed generation (DG) sources, local loads, and BESS [13,14,15]. These systems can operate autonomously or be connected to the primary AC power grid, enhancing the flexibility and reliability of the electrical system. Over the years, numerous proposals have emerged to advance microgrid development, leading to changes in their topological structures, control strategies, and functionalities to meet the requirements of diverse applications, such as aeronautical, maritime, rural, residential, commercial, and industrial environments [16,17].

DC-based microgrids have garnered increased attention due to their technical and operational advantages as part of this evolution. Their main benefits are elevated energy efficiency, simplified interfacing with RES and BESS, and high compatibility with modern electronic loads. The growing integration of RES and DG has contributed to the increasing complexity of modern electrical systems, demanding more dynamic, intelligent, and resilient solutions.

Accordingly, power converter structures have been extensively investigated and developed for various applications, driven by the growing use of RES, the increasing electricity demand, and the expansion of DC microgrids [18,19]. These studies aim to enhance the efficiency and stability of such systems in the face of the inherent challenges associated with integrating multiple energy sources and diverse loads.

Double-stage conversion systems are commonly employed to interface DC sources with AC systems. This configuration typically consists of a cascaded association of a boost converter followed by a voltage source inverter (VSI), enabling appropriate energy conditioning for delivery to the grid or end-use load [20,21].

Although this is a well-established and relatively simple solution, such architecture presents significant limitations, including the requirement of an intermediate DC bus with high capacitance, used to decouple both conversion stages. These factors increase physical volume and costs. They also hinder achieving high overall efficiency once the DC/DC and DC/AC conversion processes inherently involve conduction and switching losses, which become more pronounced due to the larger number of components and conversion stages [22,23].

As an alternative to the previously discussed limitations, several recent studies have investigated the development of integrated inverters capable of simultaneously performing input voltage boosting and DC/AC conversion [24,25,26,27,28,29,30,31,32,33,34,35,36]. These topologies are designed to meet increasingly stringent requirements in modern applications, such as operating with reduced volume and weight to facilitate integration into compact systems; achieving high DC/AC conversion efficiency to enhance energy utilization; and, whenever possible, minimizing the number of electronic components, thereby reducing cost, control complexity, and improving system reliability.

Among the integrated inverter topologies, the Single-Stage Common Ground Boost Inverter (S²CGBI) eliminates leakage current by employing a common ground between input and output [24]. Other structures, such as those proposed in [25], introduce direct coupling between the boost converter and a full-bridge inverter, thereby eliminating the need for large decoupling capacitances. Similar topologies, like the Buck–Boost Inverter (BBI) presented in [26], integrate DC/DC and DC/AC conversion functions using fewer components, contributing to a more straightforward and compact implementation.

Other approaches integrate classical DC/DC converters into single-phase inverter architectures. Ref. [27] proposes a structure based on SEPIC and Ćuk converters that enables alternating operating modes according to the output voltage half-cycle. Similarly, Ref. [28] presents an architecture derived from the Buck–Boost converter, which uses a single inductor for both half-cycles and operates in discontinuous conduction mode (DCM), resulting in simplified control and a reduced number of passive components. These approaches demonstrate the potential of creating novel topologies of integrated inverters based on traditional DC/DC topologies within integrated inverter configurations.

Among recent advances, notable contributions include the works of [11,29], which propose integrated inverters based on Zeta and Ćuk topologies, such as the Single-Phase Integrated Zeta Inverter (SP-IZI) and the Hybrid Zeta–Ćuk Inverter (HZCI). These topologies operate DCM and provide a regulated output voltage with low harmonic distortion. The coupling capacitors, combined with the alternating operation between Zeta and Ćuk modes, reduce current stress on the components and enhance conversion efficiency.

Hence, a similar topology composed of two modified Ćuk converters connected in parallel, enabling voltage step-up and unidirectional operation, was proposed in [30]. The modulation strategy adopted relies on sinusoidal pulse-width modulation (SPWM). In [31], the Integrated Ćuk Inverter (ICI) is presented as a DC/AC topology using hysteresis control and maximum power point tracking (MPPT) employing the perturb and observe (P&O) method. The converter operates in two half-cycles with three distinct switching stages, where the sequential control of the switches ensures efficient magnetization and demagnetization of the inductors.

Other studies, such as [32,33], strengthen the trend toward structural simplification and minimizing the number of passive components. In [32], an approach was proposed to eliminate electrolytic capacitors and introduce a common ground, thereby minimizing parasitic capacitance. Meanwhile, an integrated inverter based on the Ćuk converter connected to a T-type inverter and an LC filter was proposed in [33]. These contributions highlight the current advancements in single-stage inverter research for photovoltaic systems, focusing on improved efficiency, compactness, and harmonic performance.

In [32], a Modified Zeta Inverter (MZI) was proposed, based on the conventional Zeta topology and operating in DCM. The modification includes diodes in series with the inductors, which alter the static gain compared to the traditional Zeta converter operating in DCM, and prevent energy exchange between the magnetic elements. During the third operating stage, the inductor currents in the MZI reach zero, differing from the behavior observed in the conventional Zeta converter. In [35], an integrated inverter based on the Ćuk converter topology that operates autonomously in DCM was studied and implemented. The proposed solution stands out for reducing the number of components, delivering a sinusoidal voltage with low harmonic distortion, and achieving high efficiency compared to double-stage topologies.

The previously discussed structures have nominal power ratings ranging from 147 W to 2000 W, emphasizing the topologies presented in [32,33], which operate at higher power levels. None of the investigated topologies employ high-frequency transformers, which helps to avoid the increased voltage stress on power switches due to the transformation ratios.

Therefore, this paper presents the development of a novel integrated inverter topology named Integrated Zeta–Ćuk Inverter (IZCI). The IZCI originates from the combination of Zeta and Ćuk DC/DC converter topologies, resulting in an inverter composed of six power switches that operate alternately during the positive and negative half-cycles. The IZCI operates in DCM, making it easier to control once the output and the duty cycle have a linear relationship.

The DCM operation inherently provides zero current switching (ZCS), which helps reduce switching losses. However, it typically results in higher overall power losses due to the increased peak current through the components and the low inductance values generally employed. Another important aspect of it is its dependence on the switching frequency. The converter may unintentionally transition to CCM at higher frequencies and lower power levels. Specific parameters, particularly the inductance, must be carefully adjusted to maintain DCM operation for a wider power range. For instance, reducing the inductances can help preserve the DCM operation. However, as previously discussed, this strategy has drawbacks, including elevated peak and RMS currents, which increase power losses and stress on the circuit components.

Regarding topological origin, the IZCI is derived from both the Ćuk and Zeta converter structures. Similarly, the topologies presented in [30,31,33,35] are based on the Ćuk inverter, while [11,29,32,34] follow the Zeta inverter architecture. Other structures combine Buck–Boost, Boost, or SEPIC converters with the Ćuk topology. Although the IZCI uses six switches, it contains fewer components than eight of the eleven analyzed topologies, showcasing a well-balanced trade-off between construction complexity and performance.

The Hybrid Zeta–Ćuk Inverter (HZCI) is highly similar to the IZCI in switching frequency and nominal power. Both structures operate without splitting the input voltage, functioning complementarily during the positive and negative output waveforms. This approach enables the integration of the functional characteristics of the Zeta and Ćuk converters into a single structure. However, the IZCI provides constructive advantages by utilizing only two inductors, in contrast to the three used in the HZCI topology. In addition, it eliminates the diodes in series with the switches, thereby reducing power losses. Using a single input or magnetizing inductor also reduces cost and improves power density since fewer bulky components are required. On the other hand, this simplification can lead to higher peak and RMS currents through the inductor compared to the HZCI, which employs two input inductors. The increased RMS current contributes to greater conduction losses in the inductor and magnetic losses in the core.

In this context, this paper proposes the application of the IZCI topology in an autonomous DC microgrid, where the alternating output voltage is adequately regulated using a proportional-integral multiresonant (PI-MR) controller. Experimental validations verify the proposal’s effectiveness, demonstrating that the inverter can provide an output voltage waveform with low harmonic distortion and high energy conversion efficiency.

The IZCI topology shows potential for application in a wide range of systems, including DG from RES, interfacing DC microgrids and AC power grid, uninterruptible power supply (UPS) systems, and standalone systems, among other applications.

This paper is structured to present the IZCI topology and validate its performance in standalone DC microgrids. It begins with an introduction that contextualizes the need for integrated inverters. Section 2 describes the IZCI’s structure, operating modes, waveforms, and control modeling. Section 3 presents experimental results validating the topology under different loading conditions. Section 3 presents experimental results validating the topology under different loading conditions and offers a comparative analysis with other inverter topologies, and Section 4 concludes the work by highlighting the main findings and future perspectives.

2. IZCI: Structure and Operation

This section presents the operating principles and functionality of the IZCI, covering both the Zeta and Ćuk operating modes, its main waveforms, and the modeling and design of the employed controllers.

2.1. Operating Principles of the IZCI

The design targets standalone applications, such as DC microgrids, actively controlling and regulating the AC output voltage using a PI-MR controller, as illustrated in Figure 1. The IZCI was developed by combining modified Zeta and Ćuk converters, simultaneously performing DC/AC conversion with low total harmonic distortion (THD) and stepping up the input DC voltage.

The IZCI operates in DCM. In this way, the static gain maintains an approximately linear relationship with the duty cycle, facilitating the regulation of a sinusoidal reference. Moreover, this configuration reduces the influence of right-half-plane (RHP) zeros, resulting in a less complex control structure when compared to operation in continuous conduction mode (CCM), in which these zeros have a significant influence, and the static gain shows nonlinear behavior.

Figure 2 illustrates the control diagram of the AC output voltage $v_{C_o}$. A PI-MR controller regulates the duty cycle of the IZCI inverter, driving the power switches. The output voltage $v_{Co}$ is continuously compared to the reference voltage $v_{Co}^{*}$, defined as the product of a sinusoidal function $\sin \theta$ and the reference peak voltage $V_p$.

The IZCI operates with three distinct switching stages during the positive half-cycle and three additional stages during the negative half-cycle, as shown in Figure 3 and Figure 4. To accomplish this, the topology requires six switches, where during each half-cycle of the output voltage, only one switch operates at high frequency. In contrast, the others operate at low frequency or remain inactive.

Table 1. Switching logic of the power switches.

Power Switches	Positive Half-Cycle	Negative Half-Cycle
$S_1$	$D_a$	1
$S_2$	1	$D_a$
$S_{3,6}$	1	0
$S_{4,5}$	0	1

presents the corresponding switching logic.

2.1.1. IZCI—Zeta Operation Mode

In the IZCI topology, the switches $S_2$, ${\mathrm{S}}_3$ and $S_6$ remain always turned on during the positive half-cycle. The antiparallel diode in the switch $S_5$ operates as the diode of the Zeta converter. The switch $S_3$ connects the Zeta capacitor to the circuit.

First operating stage $\left(D_a{T}_s\right)$: In this stage, switches $S_1$, $S_2$, and $S_3$ are turned on. The inductors $L_m$ and $L_o$ are magnetized, as shown in Figure 3a. Additionally, the output inductor $L_o$ is magnetized according to the relationship $V_{Lo}=V_{in}{-V}_{cz}{-V}_{co}$. Assuming the equality of voltage in coupling and output capacitors, $L_o$ is magnetized by the input voltage only (i.e., the same voltage across the inductor $L_m$).

Second operation stage $\left(D_b{T}_s\right)$: In this stage, the switch $S_1$ is turned off, leading to the demagnetization of inductors $L_m$ and $L_o$. The output inductor $L_o$ demagnetizes into the output capacitor and the load. According to Figure 3b, the $L_m$ current flows to S₆ and the body diode of S₅ through the capacitor C_z, inverting the current flow in this capacitor, which must present a zero average value over the switching period. As a result, during the first and third operation stages, the current flows through the switch that remains continuously on during the whole positive half-cycle, and at the second operation stage, it flows through its antiparallel diode. Figure 3b shows this interval stage operation.

Third operating stage $\left(D_c{T}_s\right)$: In this stage, illustrated in Figure 3c, the sum of currents through $L_m$ and $L_o$ reaches zero, i.e., $i_{L_m}=-i_{L_o}$. As a result, the diode of the switch $S_5$ becomes reverse-biased, and only current exchange occurs between the inductors $L_m$ and $L_o$.

2.1.2. IZCI—Ćuk Operation Mode

During the negative half-cycle, switches $S_1$, $S_4$, and $S_5$ of the IZCI remain permanently turned on. The antiparallel diode with the switch $S_6$ operates as the diode of the Ćuk converter, and switch $S_4$ connects the Ćuk capacitor into the circuit.

First operating stage $\left(D_d{T}_s\right)$: In this stage (Figure 4a), the negative half-cycle occurs in a similar way; however, the high-frequency switch is now $S_2$. Switch $S_1$, which previously operated at high frequency, remains continuously turned on throughout the negative half-cycle, providing a current path for the inductor $L_m$ during the first stage. Inductors $L_m$ and $L_o$ are magnetized in this stage according to the relationships $V_{Lm}=V_S$ and $V_{Lo}=V_{Cc}+V_o$. The coupling capacitor is being discharged, supplying energy to both the load and the output inductor $L_o$. Considering the average voltage across the capacitor $C_c$, it corresponds to the sum of the input and output voltages, resulting in $V_{Cc}=V_S+V_o$. By substituting this into the output inductor voltage expression, both inductors are magnetized with the same voltage level.

Second operation stage $\left(D_e{T}_s\right)$: In this stage (Figure 4b), when the switch $S_2$ is turned off, the current previously stored in the inductors is finally demagnetized through the antiparallel diode of the switch $S_6$.

Third operating stage $\left(D_f{T}_s\right)$: In this stage (Figure 4c), the current in the equivalent inductance between $L_m$ and $L_o$ reaches zero, that is, $L_m=L_o$.

2.2. Main Waveforms of the IZCI

This section presents the main waveforms of the IZCI circuit, obtained by analyzing a switching period formed by the IZCI converter in stages $D_a{T}_s$, $D_b{T}_S$, and $D_c{T}_S$. The analysis also considers the converter in stages $D_d{T}_s$, $D_e{T}_s$, and $D_f{T}_s$, assuming ideal components to enhance understanding. As shown in Figure 5, the magnetization and demagnetization of the inductors occur during the first and second operating stages corresponding to each mode (Zeta and Ćuk), similar to traditional converters.

Figure 6 presents the voltage and current waveforms across the capacitors. The analysis of the operating stages shows that the same currents flowing through the inductors also flow through the capacitors. For capacitor $C_z$, during stage $D_a{T}_s$, it carries the same current that flows through the inductor $L_o$, which is a linearly varying current with low ripple. In stage $D_b{T}_s$, it assumes the current flowing through the inductor $L_m$, which has a higher ripple than in the previous stage, decreasing linearly until reaching a minimum value that remains constant until the end of the stage $D_c{T}_s$. Capacitor $C_o$, in turn, receives the high-frequency alternating component of the current flowing through the inductor $L_o$.

The voltages and currents through switches S₁ and S₂ and the intrinsic diodes $D_{S_1}$ and $D_{S_2}$ exhibit similar behavior. Thus, only the waveforms for the switch S₁ are shown in Figure 7. When the power switch $S_1$ operates in the Ćuk mode, the current flowing through it equals the input current, the same as the current flowing through the inductor $L_m$. In the Zeta mode, the current through the switch $S_1$ corresponds to the sum of the currents in the inductors $L_m$ and $L_o$. In contrast, the switch S₂ presents the same current as the $L_m$ inductor during the positive half-cycle of the output voltage as a conventional Zeta, and during the negative half-cycle of the output voltage, the current through the switch S₂ equals the sum of the current through L_m and L_o, as a conventional Ćuk converter.

Switches $S_3$ and $S_4$ exhibit similar behavior, as do the intrinsic diodes $D_{S_3}$ and $D_{S_4}$. Switch $S_3$ and diode $D_{S_3}$ operate during the positive half-cycle, where in the first stage, the switch S₃ conducts. During the second stage, the current flows through the antiparallel diode $D_{S_3}$. During the third stage, the current flows through switch S₃. The average current through the switch S₃ is null once this component is connected in series with the capacitor C_z. Meanwhile, the complementary semiconductor, S₆, operates similarly during the negative half-cycle. The switches $S_5$ and $S_6$ perform the role of the diodes in Zeta and Ćuk, allowing the current to flow during the second operation stage. Figure 8 illustrates the current and voltage behavior in the main switches of the IZCI.

2.3. Static Gain

During the positive half-cycle, the IZCI operates similarly to the conventional Zeta converter in CCM. To determine the converter’s static gain, the voltage across the magnetizing inductor is analyzed in each stage, summed, and equated to zero. In the first operation stage, the voltage across the magnetizing inductor equals the input voltage. $V_{L_m}=V_s$. In the second operation stage, $V_{L_m}=-V_{C_z}=-V_o$. In the third stage, it is observed that the voltage across the inductors becomes zero, and therefore, energy is exchanged solely between them, $V_{L_m}=-V_{C_z}+V_{L_o}+V_{C_o}=0$. As a result, the average of the operational stages leads to $V_S{D}_a-\left(V_o{D}_b\right)=0$, establishing the following relationship between the output and input voltage, as follows:

$${\displaystyle \frac{V_o}{V_s}}={\displaystyle \frac{D_a}{D_b}}$$

(1)

During the negative half-cycle, operating similarly to the conventional Ćuk converter in CCM, the same relationship as in the Zeta mode is obtained in the first operation stage, $V_{L_m}=V_s$. In the second operation stage, $V_{L_m}=V_s-\left(V_s+V_o\right)=-V_o$. In the third stage, there is no voltage across the magnetizing inductor. As a result, the average operating stages during the negative half-cycle lead to (1).

According to [36], it is possible to consider the duty cycle $D_b$ for a converter operating in CCM, by relating the equivalent inductance $L_{eq}$ is established based on the interaction between $L_m$ and $L_o$, and the switching frequency $f_S$, as derived in (2).

$$D_b=\sqrt{{\displaystyle \frac{2L_{eq}{f}_S}{R}}}$$

(2)

By substituting (2) into (1), resulting in (3) for the static gain of the circuit is obtained. The static gain depends on the inductances, the load, the switching frequency, and the control action.

$$G={\displaystyle \frac{V_{in}}{V_o}}=D_a\sqrt{{\displaystyle \frac{R}{2L_{eq}{f}_S}}}$$

(3)

The similar result between the average stages during the positive and negative half-cycles demonstrates the equivalence of the Zeta and Ćuk structures operating in the IZCI under DCM. According to (3), the static gain depends on factors such as the inductances, processed power, and switching frequency. The choice of these factors influences the operation mode and can provoke an unintentional CCM operation, losing the desired characteristics. The static gain depends on the power level, which limits the operation range of the topology. These dependencies and limitations are drawbacks compared to CCM converters.

2.4. Modeling and Control Design

The IZCI operates similarly to a conventional DC-DC Zeta converter during the positive half-cycle of the output voltage, presenting the same static gain, close dynamics, and similar behavior. Thus, an equivalent circuit (Figure 9) for this half-cycle can be adopted to obtain the mathematical model.

Initially, space-state averaging (SSA) was used to obtain the mathematical model of the IZCI. However, when a converter operates in DCM, errors occur in the average model due to the elevated difference between average and RMS current values in the inductors [36,37]. In [37], a method to mitigate these errors for the fourth-order converter is proposed. Thus, for the IZCI, it is possible to adopt the M matrix expressed by:

$$M=\left[\begin{array}{cccc}{\displaystyle \frac{1-D_a}{D_b}}& 0& 0& 0\\ 0& 1& 0& 0\\ 0& 0& 1& 0\\ 0& 0& 0& 1\end{array}\right]$$

(4)

Using the matrix M represented in (4), the initial SSA is represented by:

$$\dot{\overline{x}}=M{A}_m\overline{x}+B_m$$

(5)

$$y=C\overline{x}$$

(6)

The currents through the inductors L_m and L_o, and the voltage across the capacitors C_z and C_o, are adopted as state variables. The input voltage V_s is utilized as the input to the system, and the output voltage is chosen as the system’s output. The output voltage is the same as the voltage across the capacitor C_o, which is a state variable, making the output easy to obtain.

Using the IZCI equivalent circuit and multiplying the matrix M, then averaging between the three operation stages, the SSA model for the IZCI converter is obtained as follows:

$$\left[\begin{array}{c}{\dot{\overline{i}}}_{L_m}\\ {\dot{\overline{i}}}_{L_o}\\ {\dot{\overline{v}}}_{C_z}\\ {\dot{\overline{v}}}_{C_o}\end{array}\right]=\left[\begin{array}{cccc}0& 0& {\displaystyle \frac{-D_b}{L_m}}-{\displaystyle \frac{D_c}{L_m+L_o}}& {\displaystyle \frac{D_c}{L_m+L_o}}\\ 0& 0& {\displaystyle \frac{D_b}{L_o}}+{\displaystyle \frac{D_c}{L_m+L_o}}& {\displaystyle \frac{-D_a-D_b}{L_o}}-{\displaystyle \frac{D_c}{L_m+L_o}}\\ {\displaystyle \frac{D_b-{D_b}^2}{C_z{D}_a}}& {\displaystyle \frac{D_b-1}{C_z}}& 0& 0\\ 0& {\displaystyle \frac{1}{C_o}}& 0& {\displaystyle \frac{-1}{R{C}_o}}\end{array}\right]\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]+\left[\begin{array}{c}{\displaystyle \frac{D_a}{L_m}}\\ {\displaystyle \frac{D_a}{L_m}}\\ 0\\ 0\end{array}\right]{\overline{v}}_S$$

(7)

$$y=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]$$

(8)

During the negative half-cycle of the output voltage, the IZCI converter shows dynamics close to a Ćuk converter and can be represented by Figure 10.

The SSA obtained for the equivalent circuit of the IZCI for the negative half-cycle of the output voltage presents a close dynamic to that represented during the positive, exhibiting the same state matrix, A_m, as derived in (7).

$$\left[\begin{array}{c}{\dot{\overline{i}}}_{L_m}\\ {\dot{\overline{i}}}_{L_o}\\ {\dot{\overline{v}}}_{C_z}\\ {\dot{\overline{v}}}_{C_o}\end{array}\right]=A_m\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]+\left[\begin{array}{c}{\displaystyle \frac{D_a+D_b}{L_m}}+{\displaystyle \frac{D_c}{L_m+L_o}}\\ {\displaystyle \frac{{-D}_c}{L_m+L_o}}\\ 0\\ 0\end{array}\right]{\overline{v}}_S$$

(9)

$$y=\left[\begin{array}{cccc}0& 0& 0& 1\end{array}\right]\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]$$

(10)

Ref. [36] proposed the generalized switching averaging (GSA), which divides a converter operating in DCM into two systems: the first formed by the passive elements, represented through the conventional SSA, and the other formed by the semiconductors of the topology, switches, and diodes.

The system formed by the semiconductors for the IZCI operating DCM during the positive half-cycle of the output voltage requires three gains, which are obtained as described in [37], and are exhibited as follows:

$$k_{id}={\displaystyle \frac{-R_e{D_a}^2}{v_S{\left(D_a+D_c\right)}^2}}$$

(11)

$$k_{vs}={\displaystyle \frac{{D_{a}D}_b}{{v_S\left(D_a+D_c\right)}^2}}$$

(12)

$$k_c={\displaystyle \frac{2D_b}{{\left(D_a+D_c\right)}^2}}$$

(13)

Using the SSA with the GSA, the transfer function for the IZCI, which relates the output voltage and the duty cycle, is obtained by:

$$G_{vd}\left(s\right)={\displaystyle \frac{{\widehat{v}}_{Co}\left(s\right)}{\widehat{d}\left(s\right)}}=C{\left(sI-{MA}_m-{\displaystyle \frac{B_d{k}_{s}M{C}_m}{1-k_s{E}_d}}\right)}^{-1}{\displaystyle \frac{B_d{k}_c}{1-k_s{E}_d}}$$

(14)

where k_s = [k_id k_vs]. The matrices E_d and B_d are obtained by the GSA and are represented as follows:

$$E_d=\left[C_1-{\displaystyle \frac{D_b}{1-D_a}}{C}_2-{\displaystyle \frac{D_c}{1-D_a}}{C}_3\right]\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]+\left[E_1-{\displaystyle \frac{D_b}{1-D_a}}{E}_2-{\displaystyle \frac{D_c}{1-D_a}}{E}_3\right]{\overline{v}}_S$$

(15)

$$B_d=\left[A_1-{\displaystyle \frac{D_b}{1-D_a}}{A}_2-{\displaystyle \frac{D_c}{1-D_a}}{A}_3\right]\left[\begin{array}{c}{\overline{i}}_{L_m}\\ {\overline{i}}_{L_o}\\ {\overline{v}}_{C_z}\\ {\overline{v}}_o\end{array}\right]+\left[B_1-{\displaystyle \frac{D_b}{1-D_a}}{B}_2-{\displaystyle \frac{D_c}{1-D_a}}{B}_3\right]{\overline{v}}_S$$

(16)

where the matrices C₁, C₂, and C₃ represent the output matrices from the GSA for each operation stage, while the matrices E₁, E₂, and E₃ represent the transition matrices for each operation stage, the matrix C_m is obtained by the average of the three output matrices, i.e., C_m = C₁D_a + C₂D_b + C₃D_c. The matrices A₁, A₂, A₃, C₁, C₂, and C₃ are obtained by the SSA.

The similarity between the mathematical model is corroborated in Figure 11, which shows the open-loop frequency response for the transfer function represented by (14) and the switched equivalent circuit using the PSIM^® software, version 2022. The response shows a close behavior between the mathematical model and the switching converter. Additionally, the open-loop frequency response can be used for the control design.

The transfer function (14) obtained for the IZCI enables the voltage control loop design that ensures the topology’s correct operation. The IZCI output voltage is regulated by a proportional-integral multiresonant (PI-MR) controller, implemented in a single-loop structure, which maintains a stable and regulated output voltage with a low THD. Figure 12 presents the control diagram of IZCI, where the PI-MR controller is designed following the methodology presented in [38].

3. Experimental Results

An experimental setup was built to validate the functionality of the proposed IZCI. The topology employs six power switches, IGBTs IRG4PC50UD (Infineon, Neubiberg, Germany). The three gate driver circuits, DRO100D25A (supplier, Joinville, Brazil), control the power switches. The PI-MR control is embedded into a DSP TMS320F28335. The controlled source ITC6012C-800-50 (Itech, New Taipei City Taiwan) emulates the DC microgrid. The digital oscilloscope RTH1004 (Rohde & Schwarz, Munich, Germany) obtains the main waveforms. The power quality analyzer 435-II (Fluke, Everett, WA, USA) measures the THD and calculates the system efficiency. The IZCI prototype is shown in Figure 13, while

Table 2. Main experimental parameter for the IZCI.

Parameter	Value
Nominal output voltage	127 V
Nominal output frequency	60 Hz
Switching frequency	50 kHz
Input DC-Bus capacitance	2000 µF
Input DC voltage	140 V
Input inductance	70 µH
Output inductance	1.635 mH
Coupling capacitance	1 µF
Nominal power	280 W
Phase margin	85°
Crossover frequency	435 Hz
PI controller gains	Kp = 0.10
	Ki = 3.87
MR controller gains	R1 = 0.3810
	R3 = 0.0587
	R5 = 0.0267
	R7 = −0.0183
	R9 = 0.0114
PWM gain	1/2999
Sampling time A/D converter	1/60 kHz

organizes the main parameters involved in the experimental tests.

Figure 14 presents the experimental output voltage and current waveforms. Initially, two resistive loads are considered: Case 1—86.4 Ω and 187 W; Case 2—57.6 Ω and 280 W, as shown in Figure 14a and Figure 14b, respectively. Subsequently, a nonlinear load is analyzed (Case 3), consisting of a 120 Ω resistive load connected in parallel with a single-phase full-bridge rectifier supplying an RC load (R₃ = 250 Ω and C₃ = 100 µF), totaling 264 W, as illustrated in Figure 14c. As observed, the IZCI can maintain a regulated and sinusoidal output voltage in all three evaluated cases.

Figure 15a shows the dynamic result obtained when switching from load 1 to load 2, while the load step from load 2 to load 1 can be observed in Figure 15b. A slight oscillation is observed near the voltage peak during load transitions. Despite such oscillations during the load transitions, it can be seen that the controller used proved capable of readily adjusting the voltage levels.

The THD of the output voltage for the resistive loads does not exceed 3%, as shown in Figure 16a and Figure 16b for Cases 1 and 2, respectively. In Case 3, the IZCI achieves an output voltage THD of 3.7% when supplying a nonlinear load with 50.8% current THD.

The PI-MR controller demonstrated superior performance in reference tracking under nonlinear load conditions compared to the conventional PI controller, significantly reducing total harmonic distortion (THD). This is attributed to its resonant terms, which enhance error compensation at specific frequencies, making it well-suited for systems with periodic disturbances and harmonic rejection requirements.

The harmonic spectra of the output voltage and current for Case 3 are illustrated in Figure 16c and Figure 16d, respectively. The results confirm that the IZCI can deliver a sinusoidal output voltage with low THD for both linear and nonlinear loads.

The IZCI achieves an efficiency of approximately 90% at the nominal power. In comparison, a traditional two-stage system would require each stage to reach an efficiency of 95% to attain a similar overall performance. Furthermore, the IZCI maintains an efficiency of over 80% at power levels below 50 W. Figure 17 illustrates the IZCI efficiency using conventional silicon IGBT switching devices.

The conduction and switching losses of the semiconductor devices predominantly determine the converter’s efficiency. The power variation implies changes in the current level through switches related to the transition between the turn-on and turn-off instants. DCM operation guarantees ZCS during the turn-on instant, reducing the switching losses associated, whereas the turn-off losses increase with higher power levels. On the other hand, power variation significantly affects conduction losses, as they are directly related to the RMS currents flowing through the converter. Therefore, the efficiency is lower at low power levels, since the switching losses are more considerable. The efficiency increases for a range of power, reaching the maximum value. After this point, the conduction losses became higher, mainly due to a quadratic relation with the RMS current, reducing the efficiency. The DCM operation has an intrinsic power limitation, provoking, in some cases, an efficiency curve without a conventional convex shape, as presented in topologies operating in CCM.

Table 3. Comparative analysis of the IZCI with other integrated inverters.

Integrated Inverter Structures	IZCI	[11]	[24]	[25]	[26]	[27]	[28]	[29]	[30]	[31]	[32]	[33]	[34]
Maximum number of semiconductors conducting simultaneously [units]	4	2	3	4	4	3	3	1	3	1	4	4	2
Switching frequency [kHz]	50	50	10	20	10	100	15	50	20	50	20	20; 100	50
Rated power [W]	280	432	147	400	-	250	340	250	484	245	1000	2000	432
Input DC voltage [V]	139.2	139.2	100	200	100	40	71.2	140	200	123	150	400	139.2
High-frequency switches [units]	2	2	5	5	1	1	5	4	2	4	4	5	4
Low-frequency switches [units]	4	2	0	0	6	4	0	0	2	0	2	0	0
Diodes [units]	0	4	3	0	0	0	0	4	4	4	3	1	4
Inductors [units]	2	3	2	2	1	3	1	3	2	3	2	3	3
Capacitors [units]	3	3	2	1	1	3	1	5	3	4	3	3	4
Voltage sensors [units]	1	1	1	2	1	0	1	3	3	3	1	1	3
Current sensors [units]	0	0	0	2	1	1	1	0	3	0	0	0	0
Output Voltage [V]	180	180	180	156	156	311	311	180	120	180	311	311	180
THD	2.0%	1.6%	-	-	-	1.14%	-	0.7%	-	1.61%	3.9%	-	2.2%
Efficiency	90%	90%	-	-	-	-	90%	87.5%	-	-	94%	-	-

presents a comparative analysis of key parameters, considering other works that address integrated inverters similar to the IZCI. The analyzed topologies exhibited nominal power ratings ranging from 147 W to 2000 W, with the configurations proposed in [32,33] standing out for operating at higher power levels of 1000 W and 2000 W, respectively. None of the examined inverters employ high-frequency transformer components that, when present, directly affect the voltage stress on the semiconductor switches due to the associated transformation ratio.

In comparison to the works presented in [24,25,26,28,30,32,33], the IZCI exhibits a low THD for the output voltage synthesized by the converter. It can be noted that the converter proposed in [29] has a lower THD than the IZCI; however, it shows a higher rate when evaluated under a nonlinear load, reaching approximately 6.8%, compared to the previously reported 3.7%.

Another aspect to be evaluated is the output voltage in comparison to the input voltage, where once again the IZCI shows an advantage over the converters presented in [25,30,33], which were assessed in scenarios requiring voltage step-down.

4. Conclusions

This paper has proposed a novel single-phase integrated inverter topology designed for standalone applications. By combining the structural principles of the Zeta and Ćuk converters into a unified architecture, the IZCI achieves DC/AC conversion with inherent voltage step-up capability while maintaining high performance in terms of power quality and energy efficiency.

The IZCI operates by alternating between Zeta and Ćuk modes, depending on the half-cycle of the output voltage. This dual-mode behavior results in a more uniform component utilization, reduces current ripple, and mitigates stress on the power switches.

Experimental results validate the effectiveness of the proposed solution. The IZCI achieved output voltage THD levels below 4% across various loading scenarios, including nonlinear loads with significant current distortion. Furthermore, the inverter demonstrated high energy conversion efficiency, reaching approximately 90% at nominal load and maintaining over 80% under reduced power. These results highlight the IZCI’s suitability for energy-sensitive applications where power quality and efficiency are critical.

The IZCI topology is a technically viable and efficient solution for modern energy systems. Its compact design, high efficiency, low harmonic distortion, and control flexibility make it well-suited for distributed generation, UPS, and autonomous hybrid systems.