Statistical RF/Analog Integrated Circuit Design Using Combinatorial Randomness for Hardware Security Applications

Abstract

While integrated circuit technologies keep scaling aggressively, analog, mixed-signal, and radio-frequency (RF) circuits encounter challenges by creating robust designs in advanced complementary metal–oxide–semiconductor (CMOS) processes with the diminishing voltage headroom. The increasing random mismatch of smaller feature sizes in leading-edge technology nodes severely limit the benefits of scaling for (RF)/analog circuits. This paper describes the details of the combinatorial randomness by statistically selecting device elements that relies on the significant growth in subsets number of combinations. The randomness can be utilized to provide post-manufacturing reconfiguration of the selectable circuit elements to achieve required specifications for ultra-low-power systems. The calibration methodology is demonstrated with an ultra-low-voltage chaos-based true random number generator (TRNG) for energy-constrained Internet of things (IoT) devices in the secure communications.

1. Introduction

Although the CMOS technology reaches the deep-submicron regime, performance of digital circuits follows the prediction of Moore’s Law in the past decades. Performance of leading microprocessor doubles approximately every 18 months [1]. However, analog, mixed-signal circuits, and radio-frequency (RF) circuits are left far behind this trend. For example, performance of analog-to-digital converters (ADCs) takes 6.5 years to double [2]. Even the leading ADCs have a slightly faster progress rate of doubling every 4.7 years. Obviously, the RF and analog circuits are not able to take full advantage of process progress. Even the analog circuits cannot fully benefit from the technology scaling, analog circuits still play the quintessential role of interfacing digital signal processors to analog physical world in almost every electronic device, especially in the billions of Internet of things (IoT) devices. Challenges in the nano-meter scale would be even more rigid for RF/analog circuits since the power supply voltages decrease. Although threshold voltages in the advanced technology reduce as well, the available voltage headroom for these complicated mixed-signal functions still degrades rapidly. Besides, the problem of process variations is another challenge for robust design of RF/analog circuits due to aggressive technology scaling. In order to address matching issues in the nano-scale technology nodes, conventional sizing methods [3] that adopt large-size transistors for RF/analog circuits is still very popular even in advanced complementary metal–oxide–semiconductor (CMOS) processes. Although many of systematic variations can be predicted and tackled by utilizing careful circuit and layout techniques. The problems of large random variations are still needed to be addressed with alternate methods other than conventional up-sizing methods. The redundancy method [4] was proposed to address this issue and demonstrated in flash ADC designs. To achieve a better energy efficiency, statistical element selection (SES) [5,6] was proposed to exploit the combinations of random mismatches. In this paper, the combinatorial randomness will be utilized to efficiently the exploits subcomponents of the input differential pairs in the analog amplifiers to mitigate the impact of the process variations. A design example of a chaos-based true random number generator (TRNG) will be presented to demonstrate how the combinatorial randomness can be adopted to reduce the power consumption while the circuit is operating at ultra-low power supply voltage.

The remainder of this paper is organized as follows. Section 2 reviews the primary sources of random variations in advanced CMOS technology nodes and the effects RF/on analog circuits. In Section 3, the combinatorial randomness methodology that statistically selects circuit elements is analyzed in detail for the implementation of RF/analog circuits. A chaotic true random number generator (TRNG) for hardware security that demonstrates the potential for improved power efficiency with the combinatorial randomness is discussed in Section 4, and finally, the conclusions are drawn in Section 5.

2. Process Variations in CMOS Processes

2.1. Process Variations

In advanced CMOS technology nodes, the process variations are a significant problem and will become more serious in more advanced nodes. The process variations that might come from layout dependent effects or across-field effects result in the systematic variations [7]. For example, the threshold voltage of a metal–oxide–semiconductor field-effect transistor (MOSFET) far away from n-wells would be different from an identical one that is close to an n-well. The well proximity effect and other issues such as the polysilicon surrounding of the gates and shallow trench isolation (STI) stress [8,9,10] lead to the layout-dependent systematic variations of different characteristics for identical devices in the wafer. The other major source that results in systematic variations is the across-field effects that are due to lithography or etching. The location of different dies on the same wafer can result in a systematic offset in device characteristics although devices in the same vicinity would have the same effects on them. Through careful circuit and layout techniques, most of the systematic variations can be alleviated. Moreover, more and more restricted design rules in advanced CMOS technology nodes, such as single poly orientation, fixed gate lengths, and high regularity in the physical layers, are adopted to mitigate those systematic variations [11,12]. Emerging lithography and etching solutions, such as optical proximity correction and double patterning, are also used to provide better matching for leading-edge CMOS nodes.

On the contrary, random variations that are due to unpredictable and unrepeatable variations in manufacturing, such as random dopant fluctuation (RDF) in the transistor channel [13] and line edge roughness (LER) can result in uneven channel length in the poly line forming the gate across the width of the device and cause significant mismatch in the conductance constant among devices on the same die. Although many novel technologies have been proposed to address such problems including high-k metal gates, undoped channels, thin silicon-on-insulator devices, and Fin-FETs, threshold voltage variation in tens of milli-volts of is still expected [14,15,16,17,18].

2.2. Popular Methods for Mismatch Calibration

To reduce the local random mismatch, the traditional approach following Pelgrom’s seminal paper [3] is sizing up the device size because the standard deviation of random mismatch is inversely proportional to the square root of the device area. Figure 1 shows a typical circuit diagram of a comparator, which is called StrongArm comparator. The standard deviation of input offset voltage for the differential pair is characterized by Pelgrom in [3] as:

$$\sigma \left(V_{os}\right)=\sqrt{\frac{A_{VT}^2+0.25{\left(V_{GS}-V_{th}\right)}^2{A}_{\beta }^2}{WL}}$$

(1)

where A_VT and A_β are process-related coefficients, W and L are width and length of the differential pair. Assuming that the input offset voltages of the differential pair is the dominant sources of variations, the intuitive approach to reduce the offset voltages is to increase the device area. It means increasing area and current can lead to improved matching. With up-sized devices, the power consumption increases due to the larger current. Moreover, due to larger device loading capacitance and its parasitic capacitance, the required power would be increased further to achieve the bandwidth target. Hence, the power consumption is challenging for RF/analog circuits in advanced CMOS technology nodes even the devices can have higher operation speed. The problem is even worse while higher resolutions are required because the specifications rapidly increases the number of elements that need better matching.

Redundancy was proposed to achieve a better tradeoff between power consumption and device mismatch and demonstrated for flash ADCs in [4,19,20,21] with extra comparators to be able to select the best offset voltages of 2^N comparators for an N-bit design. Instead of putting one comparator for one comparison level, adding extra comparators to each level is implemented in the N-bit flash ADC, as shown in Figure 2. The calibration incorporating redundancy is to select and reassign the best $2^N-1$ comparators with the minimum offset for an N-bit design. If the standard deviation of comparator offset is at the order of 1 LSB, the probability distribution functions (PDFs) of the comparator offset will overlap with neighboring comparators. The comparator can be reassigned with the overlapping PDFs, which means a comparator nominally designed for one reference level can be used as another comparison level. For example, in Figure 2 comparator 2a can be used to represent Level 4 after fabrication. By utilizing the large number of redundancy comparators, this approach highly increases the probability that at least one comparator can satisfy the matching specification with a small area. However, the redundant comparators still occupy a large area although the unused comparators can be disabled and do not contribute power consumption.

The other method to achieve better tradeoff between power consumption and device matching for an input differential pair in comparators, the digital calibration digital-to-analog converters (DACs) is also very popular in advanced CMOS processes. DAC-based calibration can be implemented by adding a current DAC tapping to the drain nodes of the input differential pair as shown in Figure 3a [22]. The overhead of the current DAC can be very low and it injects current to change the offset voltage to achieve better matching. The internal nodes can be also adjusted with digitally controlled capacitive DACs [23], as shown in Figure 3b. The capacitor mismatch is added to the signal path to create a slight imbalance that results in an offset voltage. Therefore, the random offsets can be cancelled with the capacitive DAC. Meanwhile, the capacitive DACs can further create a systematic offset to eliminate the requirement of the reference ladder. However, the dynamic mismatch errors that occur during high speed operation cannot be characterized with this methodology.

In the more advanced CMOS nodes, the digital calibration with DACs and redundancy methods require significant overhead costs due to more serious problems of the random mismatch. Therefore, statistical element selection (SES) was proposed to mitigate the impact of extreme random variability through the implementation of combinatorial redundancy [5]. By choosing one subset from $2^N-1$ available subsets, each component in RF/analog circuits requiring better matching property is formed from N identically-designed subcomponents. For example, the input differential pair in a comparator is formed from a group of elemental pairs. For redundancy methodology, only one branch is selected individually. However, the digitally enabling selection of subcomponents, the combinatorial randomness can be implemented very efficiently. The search space of combinatorial randomness with statistical selections is much larger than using traditional redundancy methods because the exponential increase in the number of combinations leads to a significant improvement in probability to achieve the targeted matching specification at the little increased cost of statistical selection. In the following session, the combinatorial randomness with statistical element selection is discussed in more details.

3. Combinatorial Randomness

3.1. Expliotion of Random Mismatch

The basic concept of combinatorial randomness is to select a combination of identically designed elements for a critical circuit block, so it chooses one subset from the $2^N-1$ available subsets to meet the required specification. For example, a subset branch of input transistor pairs in an amplifier is selected to have a small input offset voltage, as shown in Figure 4 [5]. The differential amplifier with combinatorial randomness is composed of N pairs of input N-type metal-oxide-semiconductor (NMOS) transistors labeled as $M_{1a}\backslash M_{1b}$ through $M_{Na}\backslash M_{Nb}$ and selection NMOS transistors with gates tied to digital control signals $Se{l}_1$ through $Se{l}_N$. Each input pair can be selected by turning on or off with $Sel\langle 1:N\rangle$. Due to the random variations, each transistor would show different characteristics and, hence, the mismatches between the different input pairs leads to input offset voltages.

The aforementioned up-sizing approach based on the Pelgrom model and the redundancy methodology can be viewed as two extreme cases of the element selections. To realize the Pelgrom approach, all pairs from 1 to N are selected. Therefore, a lower effective variation can be achieved by utilizing the larger area by the selection of all branches, and the matching standard deviation can be improved by $1/\sqrt{N}$. To implement the redundancy approach, input pairs are grouped into predetermined identical blocks, and only one block is selected for each comparison level during post-manufacturing configuration. For example, the pair in Figure 4 with the best offset result is selected if one pair is predetermined to form one block and total number of selectable blocks is N. If $N/2$ pairs are predetermined to form one block, only two combinations cab be selected after manufacturing.

To achieve finer resolution, the presented methodology can individually select each element by using the efficient digital selection rather than grouping the elements into predetermined blocks. Therefore, the search space is much larger than that of the redundancy methodology described in [4]. Subsets can be selected by using the digital control signals if $N/2$ pairs are desired. If eight pairs are used to form a block from total 16 pairs, only two blocks can be used for selection with one redundancy element. A total 12,870 combinations, however, are available if any subset of eight elements can be selected. Moreover, the size of combinatorial subset is not limited to $N/2$, and any size of the subset from one to N can be used for selection, Therefore, total $2^N-1$ combinatorial subsets can be selected. The exponential increase in the number of total available combination subsets lead to a significant improvement in successfully finding a combination subset that can meet the desired specification.

For the differential amplifier as shown in Figure 4, the transconductances of all pairs are assumed to be the same. The overall input offset voltage of the differential amplifier can be expressed as:

$$V_{os}=\frac{1}{N}\times {\displaystyle \sum }_{i=1}^N{V}_{os,i}$$

(2)

where $V_{os,i}$ is the input offset voltage of the ith input pair. If the case of that only a subset selected from the N pairs is considered, the resulting input offset voltage equals to:

$$V_{os}=\frac{1}{{{\displaystyle \sum }}_{i=1}^N{k}_i}\times {\displaystyle \sum }_{i=1}^N{k}_i{V}_{os,i}$$

(3)

where $k_i=1$ if the ith pair is chosen, and $k_i=0$ otherwise.

Because the input offset voltage of the differential pair is generally dominated by the mismatch of threshold voltages, $V_{th}$, the input offset can be expressed as $V_{os,i}=\mathsf{\Delta }{V}_{th,i}$ [24]. Moreover, the input transistors are usually the dominant source of threshold voltage mismatch, so the input offset voltage of the differential amplifier can be determined to be $\mathcal{N}\left(0,{\sigma }_{os}^2\right)$, where ${\sigma }_{os}={\sigma }_{os,i}/\sqrt{{{\displaystyle \sum }}_{i=1}^N{k}_i}$ by using (3) and assuming that the distribution of $V_{os,i}$ is a Gaussian normal distribution with $\mathcal{N}\left(0,{\sigma }_{os,i}^2\right)$. It means that the overall offset voltage is smaller if more elements are selected, so matching of devices in proximity can be improved by $1/\sqrt{Area}$. The result matches was found by Pelgrom in [3]. To meet a desired specification such as a small input offset voltage with high probability like 99.5% with lowest possible power and area, some parameters, such as total number of elements selected (k) from selectable elements (N) and the size of each element, are required to be determined. Hence, the total number of sets among $\left(\begin{array}{c}N\\ k\end{array}\right)$ and needed calibration time can be calculated. The methodology to determine the parameters is described in the following section.

3.2. Methodology of Combinatorial Randomness

Figure 5 shows a latch type comparator with combinatorial randomness that is used in a flash type ADC and the dark sections are replicated N times [5]. Only one element among the N selectable elements that have an offset distribution of normal distribution $\mathcal{N}\left(0,{\sigma }_{os,i}^2\right)$ is selected. Hence, the probability that the offset voltage smaller than a given specification spec of one element can be expressed as:

$$p_{success}=erf\left(\frac{spec}{{\sigma }_{os,i}\times \sqrt{2}}\right)=1-p_{fail}$$

(4)

where $p_{fail}$ is the probability that the offset voltage of the element falls out of the given offset range (spec). For the comparators in a flash type ADC, spec should be less than ±0.5LSB to ensure good linearity. Because the offset voltage of each element is independent, the probability that the offset voltage of every element falls out of the given offset range can be calculated as:

$$p_{fail,total}={\left(p_{fail}\right)}^N$$

(5)

Equation (5) can be viewed as the case of the redundancy approach with N redundant elements. If all N elements are selected, the distribution of the offset voltage follows $\mathcal{N}\left(0,{\sigma }_{os,i}^2/N\right)$, and the probability that the offset is within spec can be calculated by substituting ${\sigma }_{os,i}$ in (4) with ${\sigma }_{os}={\sigma }_{os,i}/\sqrt{N}$. This case can be viewed as up-sizing method for reduction of random variability. Both approaches are the two extremes for combinatorial randomness by selecting one at a time (redundancy), or all at once (up-sizing).

Combinatorial randomness selects k elements among N selectable ones at a time ($1\le k\le N$). To show the efficiency of the presented methodology, the failure probability ($p_{fail,total}$) for different values of k is simulated with $N=20$, ${\sigma }_{os,i}=1$ and offset specification (spec) is ${10}^{-2}$ by using $1\times {10}^6$ Monte Carlo samples in MATLAB in Figure 6 [5]. The failure probability, $p_{fail}$, that an absolute offset voltage of each element is larger than 1/100 of the standard deviation can be calculated from (4) using ${\sigma }_{os,i}=1$ and $spec={10}^{-2}$.

The up-sizing method can correspond to the rightmost point in the contour where all the 20 elements are select and only one subset is available (select all elements, $k=N=20$). The failure probability for this subset with the up-sizing method can be calculated from (4) with $spec={10}^{-2}$ and ${\sigma }_{os,i}=1/\sqrt{20}$ because the standard deviation decreases by $1/\sqrt{Area}$ according to the result in [3]. The failure probability of the up-sizing method is simply $p_{fail,total}=p_{fail}$ because there is only one subset of 20 elements. The leftmost corresponds to the case with redundant elements and 20 independent subsets of only one element each ($k=1$) are available for selection. The failure probability of the redundancy approach can be calculated by $p_{fail,total}={\left(p_{fail}\right)}^{20}$. The failure probability of the combinatorial randomness is much lower than both redundancy and up-sizing approaches by several orders of magnitude if k is chosen between these two extremes, i.e., $1<k<N$. While both N and k are varied, the failure probability of the combinatorial randomness is shown in Figure 7 [5], where each blue contour corresponds to a different N value ($1<N<20$). The x-axis shows the number of the selected elements (k) among N selectable ones ($k\le N$). Each selectable element is assumed to follow $\mathcal{N}\left(0,1\right)$ and $spec={10}^{-2}$. The appropriate pair of N and k can be searched for a specific $p_{fail,total}$ while the highest $k/N$ ratio for each k can be reached to reduce the parasitic loading, as shown in Figure 7 with red circles for each k.

The comparison of abovementioned methods is shown in Figure 8 as normalized area is varied [5]. With Monte Carlo simulation with 10,000 samples in MATLAB, the yield for different methods can be estimated assuming that the offset voltage of each selectable element follows a normal distribution $\mathcal{N}\left(0,90\mathrm{mV}\right)$ with $spec=2\mathrm{mV}$. The yield for DAC-based calibration is:

$$p_{success}=erf\left(\frac{spec+LS{B}_{DAC}\times \left(2^{n-1}-1\right)}{{\sigma }_{os,i}\times \sqrt{2}}\right)$$

(6)

where $LS{B}_{DAC}$ is the calibration step size, and n is the resolution of the calibration DAC [25]. Significant improvement in success probability can be achieved with combinatorial randomness compared to the other methods.

4. Combinatorial Randomness Applications in RF/Analog Integrated Circuit Design for Hardware Security in Energy-Constrained Devices

4.1. In-Sensor Encryption with Reconfigurable Chaotic Systems

In the near future, the number of Internet of things (IoT) devices is expected to grow into billions that leads to revolutionize various applications, such as pervasive environmental sensing and continuous health monitoring. Particularly, with the extensive use of the radio-frequency identification (RFID) systems, many non-electronic objects could be turned into a wireless network of IoT sensors. Wireless connection increases the communication efficiency between pervasive sensors and the cloud [26,27,28,29]. Unfortunately, cyberattacks also increase due to a large amount of entry points in the network. Although software security patches can be used to fix vulnerabilities, users usually do not install them immediately. Devices lacked of physical un-clonable functions (PUF) can be attacked with inauthentic substitutions, physical tampering, and reverse engineering [30]. Side-channel analysis attacks are one of the typical attacks that analyze the hardware runtime characteristics, such as power consumption and electromagnetic wave, of a cryptographic device to obtain secret information [31]. For example, a strong advanced encryption standard (AES) key can be measured by correlation power analysis (CPA) [32]. Analog sensors not under the protection of crypto-enabled digital systems are particularly vulnerable to cyberattacks. For instance, an adversary may capture the confidential data and modify critical decisions [33,34]. Although advanced cryptographic algorithms can guarantee the integrity and confidentiality of sensor data [35], computation capabilities of sensors are constrained by a low power budget. Hence, a significant gap exists to integrate complete security measures into energy-constrained sensors. Recently, true random number generators (TRNGs) have been utilized as the important building block of many wireless networks with RFID systems. To enable cryptographic algorithms, random numbers play a critical role to generate encryption keys that need to be extremely resilient to the malicious attacks.

A sensor system with RFID is usually composed of a sensor front end, a transceiver, and a random number generator for data encryption, as shown in Figure 9. A strong encryption algorithm can prevent from an external attack. However, due to limited resources, such as power consumption, in wireless sensor networks for RFID wearable and implantable systems [36,37], pseudo-random number generators (PRNGs) were typically adopted instead of TRNGs for the simpler architecture. PRNG algorithms generate repeating random-like sequences with using an initial seed. Leaks of the random seed can make the PRNG outputs predictable [38]. Moreover, the PRNG output would be predictable if the internal state and the periodicity of the structure are known. On the contrary, TRNGs generate the random numbers from an observable activity or a physical process with true randomness. The conventional approach is power consuming because it requires a high-gain and wide-bandwidth amplifier to magnify the small noise voltages [39]. Utilizing energy harvested from an ambient environment to avoid frequent battery replacement provides a compelling solution for many distributed devices. However, the harvested power is limited and not stable while environmental conditions and energy sources vary. For example, energy harvested from thermoelectric generators (TEGs) is highly temperature dependent [40,41]. Therefore, the system for IoT applications to be powered by energy harvesters requires to consume very low power and operate at an ultra-low voltage of less than 0.5 V [41,42,43]. In addition, ubiquitous computing opens a new door for hackers to enter the central network through unprotected pervasive devices. Hence, the critical need is to integrate security measures into each connected device with minimum increase of power consumption. However, a gap exists to implement power-hungry advanced encryption standard (AES) in sensors. Moreover, to protect the key from being stolen through side-channel detection, advanced digital encryption may require additional circuits to shield fluctuations in the power source. On the other hand, the discrete-time chaos-based true random number generators (TRNGs) are not affected by statistics of the entropy source and resilient to the presence of the deterministic noise [44], which would be the promising security module that can be integrated onto resource-limited devices to provide complete security measures.

4.2. Approach

Whitening the primary features is how creatures efficiently communicate and hide themselves from predators, which appears to be a ubiquitous property of nature. Such effective ways to encrypt the signal, also known as the phenomenon of Chaos, can as essentially be thought of as “deterministic noise”. Dynamics of discrete-time chaotic systems can be governed by nonlinear maps. Figure 10a shows the self-feedback discrete-time chaotic system with a piecewise linear map shown in Figure 10b. The output of the chaotic generator, $x\left[n\right]$, is connected to the input of the map function, $f\left(x\right)$, as next input $x\left[n+1\right]$. The transformation function, $f\left(x\right)$, is given as $x\left[n+1\right]=G·\left(x\left[n\right]-sign\left(x\left[n\right]\right)·V_{ref}\right)$, where $sign\left(x\left[n\right]\right)$ is equal to 1 when $x\left[n\right]\ge 0$; $sign\left(x\left[n\right]\right)$ is equal to −1 when $x\left[n\right]<0$. “$G·V_{ref}$” is the maximum output voltage so that the output is bounded by $+G·V_{ref}$ and $-G·V_{ref}$. S_i is the signal to encrypt and it is sampled at f_c, while $f\left(x\right)$ is clocked at f_s. When fs is several times higher than f_c, the sampled signal will be scrambled and permutated in the loop. The dynamic signal evolves from the underlying principle of self-similarity at different scales, as shown in Figure 10b, where the orbit is generated from an initial condition of 0.7 with a gain close to 2 and $V_{ref}$ as 0.5. Figure 10c shows the output signal is aperiodic and noise-like in time domain, while it is continuous and wideband in frequency domain. The state space trajectories originating from two closely spaced initial conditions diverge exponentially, showing high sensitivity to initial conditions, as shown in Figure 10d. Hence, different deterministic noises can be created with different initial inputs. With matched chaotic generators integrated in both sensors and receivers, the signals can be encrypted and decrypted in real time. Chaotic encryption can be performed before transmission via the edge node radio to produce a transformed waveform that is unintelligible. The receiving node correspondingly performs the converse decryption to recover the original signal, as shown in Figure 11a. The initial states and targeted maps can be setup through synchronization to ensure that two chaotic systems have the same trajectories. The chaotic generator can be realized with the topology similar to the residue amplifier in pipeline ADCs, where the parameter G represents gain, $V_{ref}$ is the reference voltage, and $V_c$ is the offset voltage. To make the system more dynamic, multiple maps can be cascaded to increase the overall gain, as shown in Figure 11b,c. To avoid using power-hungry close-loop amplifiers, multiple-stage architectures using reconfigurable open-loop amplifiers can be utilized to increase the overall gain. The open-loop gain, G, is equal to transconductance, g_m, times output impedance, Z_L.

In order to minimize power consumption, combinatorial randomness of intrinsic transconductance from minimum-sized devices will be deployed to provide maximum programmability, as shown in Figure 12a. Process variations result in a wide-range g_m from the selectable devices, where the combinatorial g_m can be characterized with decision windows to generate different gains for the transformation function. When signals propagate to the next stage, the first map will be reconfigured to ensure that the overall gain follows the dynamic law without interrupting its operation. Figure 12b shows the control loop to train the transformation function with different maps. The algorithm compares the X_ref and X_trained to update the selection of the combinatorial subset until the average of X_diff is equal to zero. The transformation functions can be updated from time to time so that the signal can travel in time-varying orbits to enhance the strength of the security. Given that devices are with various intrinsic transconductances after fabrication, different subsets will be enabled for different devices. Hence, every device is unique so that it is inherently embedded with un-clonability. The reconfigurable chaotic system is expected to achieve sub-nW operations by exploring nonlinear dynamical effects and combinatorial intrinsic transconductance.

4.3. Simulation Results

To assess the proposed reconfigurable chaotic system, we have created a compact simulation model of two-stage residue amplifiers based on physical characteristics and different noise levels. Each residue amplifier works at difference phase. As the simulation results shown in Figure 13a, the output signals appear to have the chaotic behavior with zero cross-correlation and impulse-like auto-correlation. To determine how often the chaotic systems need to be synchronized, the internal noise is set to different levels from 6-bit to 16-bit resolution, where the internal clock of the transformation function is 100 times of the input signal. Therefore, for each sampled data, the internal noise is integrated in the loop for one hundred cycles. Figure 13b shows that synchronization rate increases when the internal noise level is higher. For instance, with a 6-bit noise-level, the system needs to be synchronized every ten sampling periods, while with 16-bit resolution, the synchronization cycle extends to 20 sampling periods. The signal can be transformed effectively into deterministic noise without showing intelligible patterns on the power supply. Figure 13c illustrates unsuccessful CPA attacks on the proposed chaotic system with 50,000 traces. These simulation results demonstrate that this approach can counter side-channel attacks. With synchronization between two chaotic systems with combinatorial randomness, the decoded signal has been recovered with less than 1% performance degradation comparing to signals without being scrambled. This data confirms that the proposed approach for improving sensory-interface security with combinatorial randomness is feasible and effective.

5. Conclusions

A calibration methodology based on combinatorial randomness by statistically selecting elements offers an effective approach to mitigate random variation impact on mismatch. While combinatorial randomness has been demonstrated in this paper for comparator offset calibration in flash ADCs and differential pairs in chaos-based TRNGs, the approach can be generally applied to matching of any two or more components for integrated circuit design. The simulation results show that the combinatorial randomness approach for any matching design problem can achieve several orders of magnitude of improvement as compared to other calibration approaches. The fundamental analog differential amplifier validated the mathematical models, and the benefits from random process variations will be more prominent in more advanced technology nodes, such as 28 nm nodes and beyond. The efficacy of combinatorial randomness will increase while more effort is placed on the hardware-algorithm co-design of the integrated circuits.