A Novel Low-Power Mixed-Mode Universal Filter Design Using Multiple-Input Operational Transconductance Amplifiers
Abstract
1. Introduction
2. Proposed Circuit
2.1. Multiple-Input Operational Transconductance Amplifier
2.2. Proposed Mixed-Mode Universal Filter
- •
- Voltage-mode
- •
- Transimpedance-mode
- •
- Transadmittance-mode:
- •
- Current-mode
2.3. Non-Idealities Analysis
3. Results
3.1. Simulation Result
3.2. Applications
3.3. Experimental Result
4. Discussion and Comparison
- •
- Sensitivity to Process and Temperature Variations: Because the transistors operate in the subthreshold region, the circuit is inherently sensitive to temperature-induced exponential current variations. However, for targeted biomedical applications (such as wearable or implantable medical devices), the ambient temperature environment remains highly stable. To verify robustness against unpredictable variations, the design functionality was thoroughly validated across rigorous Process–Voltage–Temperature (PVT) corners, with a specific focus on temperature corners, proving stable filter operation under realistic deployment conditions.
- •
- Scalability to Higher Frequencies: The proposed circuit is specifically optimized for low-frequency biomedical applications (ranging from sub-Hertz up to 10 kHz). In this low-frequency domain, the small bulk-driven transconductance () is highly beneficial for achieving ultra-low cutoff frequencies without requiring excessively large capacitors. If scaling to higher operating frequencies is required for other applications, the multiple-input (MI) technique can be readily adapted to a conventional gate-driven MOS architecture to leverage its higher transconductance ().
- •
- Noise Performance: The bulk-driven architecture experiences a higher input-referred noise floor compared to conventional gate-driven topologies due to the lower value of . However, the capacitive division of the multiple-input network simultaneously expands the linear input voltage range by the exact same scaling ratio. As a result, the signal-handling capacity increases proportionally with the noise floor, ensuring that the overall Dynamic Range (DR) remains unaffected and fully compliant with system requirements.
- •
- Limitations Associated with Bulk-Driven MOS Transistors: While the reduced transconductance () of bulk-driven devices relative to gate-driven devices is traditionally viewed as a limitation, it serves as a core design advantage in this application. Minimizing the filter cutoff frequency (fc) fundamentally requires establishing an exceptionally low transconductance-to-capacitance ratio (). Utilizing the smaller offers an ideal architectural solution, enabling sub-Hertz pole realization while maintaining highly manageable on-chip capacitance values.
- •
- Implementation Complexity in Integrated Circuits: The proposed design exhibits lower overall circuit complexity compared to conventional highly linearized low-frequency filters. Although the multiple-input (MI) capacitive network marginally increases the silicon area of the input stage, it uses the exact same compact core amplifier circuit. By using a single differential pair combined with the MI network rather than complex multi-stage distortion cancellation techniques, the structural complexity of the integrated circuit is significantly minimized.
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Acknowledgments
Conflicts of Interest
Appendix A
References
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| Mode | Filtering Function | Input | Output | Condition | |
|---|---|---|---|---|---|
| VM | LPF | Non-inverting | = = = = 0, = = 0 | ||
| Inverting | = = = = 0, = = 0 | ||||
| HPF | Non-inverting | = = = = 0, = = 0 | |||
| Inverting | = = = = 0, = = 0 | ||||
| BPF | Non-inverting | = = = = 0, = = 0 | |||
| Inverting | = = = = 0, = = 0 | ||||
| BSF | Non-inverting | = = = = 0, = = 0 | |||
| Inverting | = = = = 0, = = 0 | ||||
| APF | Non-inverting | = = = = 0, = = 0 | |||
| Inverting | = = = = 0, = = 0 | ||||
| TIM | LPF | Non-inverting | = = = = = 0, = 0 | ||
| Inverting | = = = = = 0, = 0 | ||||
| HPF | Non-inverting | = = = = = 0, = 0 | |||
| Inverting | = = = = = 0, = 0 | ||||
| BPF | Non-inverting | = = = = = 0, = 0 | |||
| Inverting | = = = = = 0, = 0 | ||||
| BSF | Non-inverting | = = = = = 0, = 0 | |||
| Inverting | = = = = = 0, = 0 | ||||
| APF | Non-inverting | = = = = = 0, = 0 | |||
| Inverting | = = = = = 0, = 0 | ||||
| TAM | LPF | Non-inverting | = 0, = , = 0, = , = = 0 | ||
| Inverting | = 0, = , = 0, = , = = 0 | ||||
| HPF | Non-inverting | = 0, = , = , = 0, = = 0 | |||
| Inverting | = 0, = , = , = 0, = = 0 | ||||
| BPF | Non-inverting | = 0, = , = , = , = = 0 | |||
| Inverting | = 0, = , = , = , = = 0 | ||||
| BSF | Non-inverting | = 0, = , = = 0, = = 0 | |||
| Inverting | = 0, = , = = 0, = = 0 | ||||
| APF | Non-inverting | = = = = 0, = = 0 | |||
| Inverting | = = = = 0, = = 0 | ||||
| CM | LPF | Non-inverting | = = 0, = , = 0, = , = 0 | ||
| Inverting | = = 0, = , = 0, = , = 0 | ||||
| HPF | Non-inverting | = = 0, = , = , = 0, = 0 | |||
| Inverting | = = 0, = , = , = 0, = 0 | ||||
| BPF | Non-inverting | = = 0, = , = , = , = 0 | |||
| Inverting | = = 0, = , = , = , = 0 | ||||
| BSF | Non-inverting | = = 0, = , = = 0, = 0 | |||
| Inverting | = = 0, = , = = 0, = 0 | ||||
| APF | Non-inverting | = = = = = 0, = 0 | |||
| Inverting | = = = = = 0, = 0 | ||||
| Component | W/L (µm/µm) |
|---|---|
| M1,2 | 2 × 30/3 |
| M11,12 | 30/3 |
| M3–6, M3c–6c | 10/5 |
| M7–10, M13 | 15/5 |
| M7c–10c, M13c | 2 × 15/5 |
| MR | 6/5 |
| CB = 0.4 pF | |
| Factor | Proposed | [17] 2020 | [19] 2025 | [22] 2021 | [25] 2017 | [29] 2025 | [31] 2025 |
|---|---|---|---|---|---|---|---|
| Number of active devices | 7-MI-OTA | 5-OTA | 10-OTA | 2-VDBA | 3-CCCCTA | 2-DVCCTA | 1-VDGA |
| Realization | 65 nm CMOS | 0.35 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS |
| Passive components | 2-C | 2-C | 2-C | 2-C, 2-R | 2-C | 2-C, 6-R | 2-C |
| Number of offered responses | 40 | 20 | 5 | 17 | 18 | 20 | 13 |
| Offer five standard responses of VM, TAM, CM, TIM | Yes | Yes | Yes | No | No | Yes | No |
| All grounded passive components | Yes | Yes | Yes | No | Yes | No | No |
| High input impedances for VM | Yes | Yes | Yes | No | Yes | No | Yes |
| Electronic tunning capability | Yes | Yes | Yes | Yes | Yes | Yes | Yes |
| Natural frequency (Hz) | 156 | 3.39 × 106 | 50.6–1270 | 1.44 × 106 | 3.183 × 106 | 3.98 × 106 | 1.59 × 106 |
| Power supply (V) | 0.5 | ±0.9 | 0.5–1.2 | ±0.75 | ±0.9 | ±0.9 | ±0.9 |
| Power dissipation (W) | 450 × 10−9 | - | 48 × 10−9 | 0.373 × 10−3 | 1.99 × 10−3 | 4.69 × 10−3 | 2.84 × 10−3 |
| THD ([%]@mV) | 1@50 | - | 0.93@50 | 2.2@100 | 2.16@200 | <6@120 | - |
| Dynamic range (dB) | 37 | - | 53.46 | - | - | - | - |
| Verification of result | Sim/Exp | Sim/Post-Layout | Sim/Post-Layout | Sim/Exp | Sim/Post-Layout | Sim/Post-Layout | Sim/Exp |
| Application area | Bio. | Comm. | Bio. | Comm. | Comm. | Comm. | Comm. |
| Factor | Proposed | [32] 2022 | [33] 2023 | [34] 2024 | [35] 2024 | [36] 2024 |
|---|---|---|---|---|---|---|
| Number of active devices | 7-MI-OTA | 5-DDTA | 2-MO-OTA, 2-MIMO-OTA | 2-DDTA, 2 MO-DDTA | 3-MIMO-DDCCTA | 3-MI-OTA, 1-MIMO-OTA |
| Realization | 65 nm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS | 0.18 µm CMOS |
| Passive components | 2-C | 2-C | 2-C | 2-C | 2-C, 3-R | 2-C, 1-R |
| Number of offered responses | 40 | 36 | 35 | 61 | 179 | 40 |
| Offer five standard responses of VM, TAM, CM, TIM | Yes | Yes | Yes | Yes | Yes | Yes |
| Offer both non-inverting and inverting transfer functions | Yes | No | No | No | Yes | Yes |
| Without dual/triple input current signals | Yes | Yes | No | No | No | No |
| Natural frequency (Hz) | 156 | 1.04 × 103 | 114 | 211 | 1.59 × 103 | 5.95 × 103 |
| Power supply (V) | 0.5 | 1.2 | 0.5 | 0.5 | 1 | 1 |
| Power dissipation (W) | 450 × 10−9 | 330 × 10−6 | 58 × 10−9 | 281 × 10−9 | 374 × 10−3 | 156.8 × 10−6 |
| THD ([%]@mV) | 1@50 | 1.09@325 | 1@85 | 1@150 | 0.983@170 | 1@220 |
| Dynamic range (dB) | 37 | 63.69 | 53.2 | 58.23 | 57.7 | 40.2 |
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Share and Cite
Khateb, F.; Suksaibul, P.; Kulej, T.; Kumngern, M. A Novel Low-Power Mixed-Mode Universal Filter Design Using Multiple-Input Operational Transconductance Amplifiers. Technologies 2026, 14, 352. https://doi.org/10.3390/technologies14060352
Khateb F, Suksaibul P, Kulej T, Kumngern M. A Novel Low-Power Mixed-Mode Universal Filter Design Using Multiple-Input Operational Transconductance Amplifiers. Technologies. 2026; 14(6):352. https://doi.org/10.3390/technologies14060352
Chicago/Turabian StyleKhateb, Fabian, Pichai Suksaibul, Tomasz Kulej, and Montree Kumngern. 2026. "A Novel Low-Power Mixed-Mode Universal Filter Design Using Multiple-Input Operational Transconductance Amplifiers" Technologies 14, no. 6: 352. https://doi.org/10.3390/technologies14060352
APA StyleKhateb, F., Suksaibul, P., Kulej, T., & Kumngern, M. (2026). A Novel Low-Power Mixed-Mode Universal Filter Design Using Multiple-Input Operational Transconductance Amplifiers. Technologies, 14(6), 352. https://doi.org/10.3390/technologies14060352

