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Open AccessArticle

Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair

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Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea
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Design Technology Team, Samsung Electronics CO., Ltd., Hwaseong-Si 445-330, Korea
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Author to whom correspondence should be addressed.
Electronics 2020, 9(2), 338; https://doi.org/10.3390/electronics9020338
Received: 22 January 2020 / Revised: 8 February 2020 / Accepted: 13 February 2020 / Published: 15 February 2020
(This article belongs to the Special Issue Hardware and Architecture Ⅱ)
Neural-network computing has revolutionized the field of machine learning. The systolic-array architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability of the systolic-array architecture should be guaranteed. This paper proposes an efficient systolic-array redundancy architecture that is based on systolic-array partitioning and rearranging connections of the systolic-array elements. The proposed architecture allows both offline and online repair with an extended redundancy architecture and programmable fuses and can ensure reliability even in an online situation, for which the previous fault-tolerant schemes have not been considered. View Full-Text
Keywords: offline repair; online repair; parallel processing; redundancy; systolic-arrays offline repair; online repair; parallel processing; redundancy; systolic-arrays
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Cho, K.; Lee, I.; Lim, H.; Kang, S. Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair. Electronics 2020, 9, 338.

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