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Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM

Instituto ITACA, Universitat Politècnica de València, Camino de Vera s/n, 46022 Valencia, Spain
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Electronics 2020, 9(12), 2074; https://doi.org/10.3390/electronics9122074
Received: 29 October 2020 / Revised: 30 November 2020 / Accepted: 3 December 2020 / Published: 5 December 2020
(This article belongs to the Section Computer Science & Engineering)
Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault tolerance mechanism based on error correction codes (ECC), able to modify its behavior when the error conditions change without increasing the redundancy. As a case example, we have designed a mechanism that can detect intermittent faults and swap from an initial generic ECC to a specific ECC capable of tolerating one intermittent fault. We have inserted the mechanism in the memory system of a 32-bit RISC processor and validated it by using VHDL simulation-based fault injection. We have used two (39, 32) codes: a single error correction–double error detection (SEC–DED) and a code developed by our research group, called EPB3932, capable of correcting single errors and double and triple adjacent errors that include a bit previously tagged as error-prone. The results of injecting transient, intermittent, and combinations of intermittent and transient faults show that the proposed mechanism works properly. As an example, the percentage of failures and latent errors is 0% when injecting a triple adjacent fault after an intermittent stuck-at fault. We have synthesized the adaptive fault tolerance mechanism proposed in two types of FPGAs: non-reconfigurable and partially reconfigurable. In both cases, the overhead introduced is affordable in terms of hardware, time and power consumption. View Full-Text
Keywords: fault tolerance; error control codes; fault injection; hardware description languages; logic circuits; FPGA fault tolerance; error control codes; fault injection; hardware description languages; logic circuits; FPGA
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MDPI and ACS Style

Baraza-Calvo, J.-C.; Gracia-Morán, J.; Saiz-Adalid, L.-J.; Gil-Tomás, D.; Gil-Vicente, P.-J. Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. Electronics 2020, 9, 2074. https://doi.org/10.3390/electronics9122074

AMA Style

Baraza-Calvo J-C, Gracia-Morán J, Saiz-Adalid L-J, Gil-Tomás D, Gil-Vicente P-J. Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM. Electronics. 2020; 9(12):2074. https://doi.org/10.3390/electronics9122074

Chicago/Turabian Style

Baraza-Calvo, J.-Carlos, Joaquín Gracia-Morán, Luis-J. Saiz-Adalid, Daniel Gil-Tomás, and Pedro-J. Gil-Vicente 2020. "Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM" Electronics 9, no. 12: 2074. https://doi.org/10.3390/electronics9122074

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