Next Article in Journal
New Application of an Instantaneous Frequency Parameter for Assessing Far Infrared Fabric Effects in Aged Subjects
Previous Article in Journal
Deep Learning-Based Stacked Denoising and Autoencoder for ECG Heartbeat Classification
Open AccessArticle

Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM

by Bo Gao 1, Xin Li 1, Jie Sun 2 and Jianhui Wu 1,*
1
National ASIC System Engineering Center, Southeast University, Nanjing 210096, China
2
School of electronics and information engineering, Nanjing University of Aeronautics and Astronautics, Nanjing 210096, China
*
Author to whom correspondence should be addressed.
Electronics 2020, 9(1), 137; https://doi.org/10.3390/electronics9010137
Received: 9 November 2019 / Revised: 5 January 2020 / Accepted: 7 January 2020 / Published: 10 January 2020
(This article belongs to the Section Circuit and Signal Processing)
The features of high-resolution and high-bandwidth are in an increasing demand considering to the wide range application fields based on high performance data converters. In this paper, a modeling of high-resolution hybrid analog-to-digital converter (ADC) is proposed to meet those requirements, and a 16-bit two-step pipelined successive approximation register (SAR) analog-to-digital converter (ADC) with first-order continuous-time incremental sigma-delta modulator (ISDM) assisted is presented to verify this modeling. The combination of high-bandwidth two-step pipelined-SAR ADC with low noise ISDM and background comparator offset calibration can achieve higher signal-to-noise ratio (SNR) without sacrificing the speed and plenty of hardware. The usage of a sub-ranging scheme consists of a coarse SAR ADC followed by an fine ISDM, can not only provide better suppression of the noise added in 2nd stage during conversion but also alleviate the demands of comparator’s resolution in both stages for a given power budget, compared with a conventional Pipelined-SAR ADC. At 1.2 V/1.8 V supply, 33.3 MS/s and 16 MHz input sinusoidal signal in the 40 nm complementary metal oxide semiconductor (CMOS) process, the post-layout simulation results show that the proposed hybrid ADC achieves a signal-to-noise distortion ratio (SNDR) and a spurious free dynamic range (SFDR) of 86.3 dB and 102.5 dBc respectively with a total power consumption of 19.2 mW. View Full-Text
Keywords: Pipelined-SAR ADC; ISDM; noise enhancement; redundant and offset calibration Pipelined-SAR ADC; ISDM; noise enhancement; redundant and offset calibration
Show Figures

Figure 1

MDPI and ACS Style

Gao, B.; Li, X.; Sun, J.; Wu, J. Modeling of High-Resolution Data Converter: Two-Step Pipelined-SAR ADC based on ISDM. Electronics 2020, 9, 137.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop