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Open AccessArticle

Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation

School of Microelectronics, Tianjin University, Tianjin 300072, China
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Electronics 2020, 9(1), 122; https://doi.org/10.3390/electronics9010122
Received: 31 October 2019 / Revised: 30 December 2019 / Accepted: 5 January 2020 / Published: 8 January 2020
(This article belongs to the Special Issue Optical Communications and Networks)
Low-density parity-check (LDPC) codes have the potential for applications in future high throughput optical communications due to their significant error correction capability and the parallel decoding. However, they are not able to satisfy the very low bit error rate (BER) requirement due to the error floor phenomenon. In this paper, we propose a low-complexity iterative decoding scheme for product codes consisting of very high rate outer codes and LDPC codes. The outer codes aim at eliminating the residual error floor of LDPC codes with quite low implementation costs. Furthermore, considering the long simulation time of computer simulation for evaluating very low BER, the hardware platform is built to accelerate the evaluation of the proposed iterative decoding methods. Simultaneously, the fixed-point effects of the decoding algorithms are also be evaluated. The experimental results show that the iterative decoding of the product codes can achieve a quite low bit error rate. The evaluation using field programmable gate array (FPGA) also proves that product codes with LDPC codes and high-rate algebraic codes can achieve a good trade-off between complexity and throughput. View Full-Text
Keywords: low-density parity-check codes; error floor; product codes; field programmable gate array low-density parity-check codes; error floor; product codes; field programmable gate array
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Chen, W.; Zhao, W.; Li, H.; Dai, S.; Han, C.; Yang, J. Iterative Decoding of LDPC-Based Product Codes and FPGA-Based Performance Evaluation. Electronics 2020, 9, 122.

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