Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors
Abstract
:1. Introduction
2. Device Structure and Simulation Methodology
3. Results
3.1. Principle of Operation
3.2. Effect of Lateral Gate Length (LG) Variation
3.2.1. Depletion Regime
3.2.2. Accumulation Regime
3.3. Effect of Gate Gap Variation
4. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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Parameter | Value |
---|---|
Gate length (LG) | 50, 200, 300, 400 nm |
Gate Gap (GG) | 50, 100, 150 nm |
Contact work function | 5.12 eV |
Gate voltage | −2 V to +2 V |
Drain Voltage | −0.05 V to −1 V |
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Larki, F.; Islam, M.S.; Dehzangi, A.; Tariqul Islam, M.; Wong, H.Y. Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors. Electronics 2019, 8, 538. https://doi.org/10.3390/electronics8050538
Larki F, Islam MS, Dehzangi A, Tariqul Islam M, Wong HY. Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors. Electronics. 2019; 8(5):538. https://doi.org/10.3390/electronics8050538
Chicago/Turabian StyleLarki, Farhad, Md Shabiul Islam, Arash Dehzangi, Mohammad Tariqul Islam, and Hin Yong Wong. 2019. "Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors" Electronics 8, no. 5: 538. https://doi.org/10.3390/electronics8050538