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Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors

1
Department of Physics, Isfahan University of Technology, Isfahan 84156–83111, Iran
2
Faculty of Engineering, Multimedia University, Cyberjaya 63100, Malaysia
3
Center for Quantum Devices, Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, IL 60208, USA
4
Nour, LLC, Wilmette, IL 60091, USA
5
Faculty of Engineering and Built Environment, Universiti Kebangsaan Malaysia (UKM), Bangi 43600, Selangor, Malaysia
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(5), 538; https://doi.org/10.3390/electronics8050538
Received: 12 March 2019 / Revised: 2 April 2019 / Accepted: 2 April 2019 / Published: 13 May 2019
(This article belongs to the Section Semiconductors and Quantum)
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PDF [3795 KB, uploaded 13 May 2019]
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Abstract

In this paper, we investigate the effect of lateral gate design on performance of a p-type double lateral gate junctionless transistors (DGJLTs) with an air gate gap. The impact of lateral gate length, which modifies the real channel length of the device and gate gap variation down to 50 nm which have been found to be the most influential factors in the performance of the device have been comprehensively investigated. The characteristics are demonstrated and compared with a nominal DGJLTs through three-dimensional technology computer-aided design (TCAD) simulation. At constant channel geometry (thickness and width), when the lateral gate length decreases, the results show constant flatband drain current characteristics while the OFF state current (IOFF) increases significantly. On the other hand, by decreasing the air gap the subthreshold current considerably decreases while the flatband current is constant. Moreover, at a certain gate gap, the gates lose control over the channel and the device simply works as a resistor. Electric field component, carriers’ density, band edge energies, and recombination rate of the carriers inside the channel in depletion and accumulation regimes are analysed to interpret the variation of output characteristics. View Full-Text
Keywords: double lateral gate; junctionless transistors (JLTs); lateral gate length; air gap double lateral gate; junctionless transistors (JLTs); lateral gate length; air gap
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This is an open access article distributed under the Creative Commons Attribution License which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited (CC BY 4.0).
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Larki, F.; Islam, M.S.; Dehzangi, A.; Tariqul Islam, M.; Wong, H.Y. Effect of lateral Gate Design on the Performance of Junctionless Lateral Gate Transistors. Electronics 2019, 8, 538.

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