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Open AccessArticle

Distributed-Memory-Based FFT Architecture and FPGA Implementations

Centar LLC, Los Angeles, CA 90077, USA
Electronics 2018, 7(7), 116; https://doi.org/10.3390/electronics7070116
Received: 11 June 2018 / Revised: 12 July 2018 / Accepted: 13 July 2018 / Published: 17 July 2018
A new class of fast Fourier transform (FFT) architecture, based on the use of distributed memories, is proposed for field-programmable gate arrays (FPGAs). Prominent features are high clock speeds, programmability, reduced look-up-table (LUT) and register usage, simplicity of design, and a capability to do both power-of-two and non-power-of-two FFTs. Higher clock speeds are a consequence of new algorithms and a more fine-grained structure compared to traditional pipelined FFTs, so clock speeds are typically >500 MHz in 65 nm FPGA technology. The programmability derives from the memory-based architecture, which is also scalable. Reduced LUT and register usage arises from a unique methodology to control word growth during computation that achieves high dynamic range, along with inherent systolic circuit characteristics: simple, regular, uniform arrays of processing elements, connected in nearest-neighbor fashion to minimize wiring lengths. The circuit goal was to maximize throughput and minimize the use of the FPGA LUT and register logic fabric. Comparison results from seven different designs, covering a spectrum of functionality (fixed-size, variable, floating-point and variable non-power-of-two FFTs), different FPGA vendors (Intel and Xilinx) and different FPGA types, showed increases in throughput per logic cell up to 181% with an average improvement of 94%. View Full-Text
Keywords: FFT; FPGA; memory-based FFT; systolic array; pipelined FFT; fast Fourier transform; FFT circuit; FFT implementation; variable FFT; Long Term Evolution FFT; FPGA; memory-based FFT; systolic array; pipelined FFT; fast Fourier transform; FFT circuit; FFT implementation; variable FFT; Long Term Evolution
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Nash, J.G. Distributed-Memory-Based FFT Architecture and FPGA Implementations. Electronics 2018, 7, 116.

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