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Open AccessFeature PaperArticle

Implementation of a Single-Phase SST for the Interface between a 13.2 kV MVAC Network and a 750 V Bipolar DC Distribution

1
Department of Electrical Engineering, Pusan National University, Busan 46241, Korea
2
Power Conversion and Control Research Center, HVDC Research Division, KERI, Changwon 51543, Korea
3
Smart Power Distribution Lab, Power Distribution ICT Group, Daejeon 305-760, KEPCO, Korea
*
Author to whom correspondence should be addressed.
Electronics 2018, 7(5), 62; https://doi.org/10.3390/electronics7050062
Received: 12 April 2018 / Revised: 29 April 2018 / Accepted: 30 April 2018 / Published: 4 May 2018
(This article belongs to the Special Issue Renewable Electric Energy Systems)

Abstract

This paper presents the implementation of a single-phase solid-state transformer (SST) for the interface between a 13.2 kV medium voltage alternative current (MVAC) network and a 750 V bipolar DC distribution. The SST has ten cascaded subunits in consideration of the device rating and modulation index (MI). Each subunit consists of an AC/DC stage and a DC/DC stage with a high frequency isolated transformer (HFIT). The AC/DC stage consists of cascaded H-bridges (CHBs) to cope with the MVAC. The DC/DC stage employs a triple active bridge (TAB) converter for bipolar DC distribution. Topology analysis and controller design for this specific structure are discussed. In addition, the insulation of HFIT used in DC/DC converters is also discussed. A simple balancing controller at the AC/DC stage and a current sharing controller at the DC/DC stage are used to prevent DC-link voltage unbalance caused by the cascaded structure. The discussions are validated using a 150 kW single-phase 21-level SST prototype at the laboratory level.
Keywords: balancing controller; CHB; DAB; SST balancing controller; CHB; DAB; SST

1. Introduction

In recent decades, DC distribution has received increased attention for many applications because it is considered advantageous and superior to AC distribution in some cases, such as interfacing between renewable energy sources and DC loads, lower line losses, and so on [1,2,3,4,5]. There are two types of DC distribution systems: unipolar distribution and bipolar distribution. This paper focuses on the bipolar system due to its prominent advantages. The bipolar DC system can provide different voltage levels to loads, which allows connecting high- and low-power devices at a suited voltage level. In addition, this concept reduces the voltage level with respect to ground, which makes the distribution system safer for users [6]. To construct a bipolar DC distribution system with these many advantages, there is a need for additional power conversion devices that can be connected to an already existing AC grid.
The SST based on power electronics is a popular scheme to access to the AC grid and DC distribution system. It decreases the size of the system and provides instantaneous voltage regulation, bidirectional power flow, voltage sag and reactive power compensations, harmonic reduction, and so on [7,8,9,10].
Many researchers have developed some prototypes to implement SSTs. For example, Ref. [11] introduced a 7.2 kV 20 kVA single-phase SST prototype with customized 6.5 kV 25 A dual insulated gate bipolar transistor (IGBT) packages for high-voltage and low-current application, and Ref. [12] presented a 3.3 kV 300 kVA back-to-back three-phase SST prototype for universal and flexible power management. In Ref. [13], a 15 kV 1.2 MVA single-phase SST prototype was designed for a railway grid. These prototypes have different structures depending on the purpose of use. In other words, the SST prototypes were designed to be suitable for specific applications.
This paper introduces a single-phase 150 kW prototype of an SST for the connection between a 13.2 kV MVAC grid and a bipolar 750 V DC distribution system. This SST prototype consists of an AC/DC stage and a DC/DC stage. The AC/DC stage employs the CHB rectifiers and is responsible for power factor control, voltage regulation, and the voltage balancing of DC-links. The DC/DC stage employs a specially designed TAB converter for connecting to the bipolar DC distribution system. In addition, it is responsible for voltage control, and current sharing in parallel-connected outputs. This paper also discusses the insulation of the HFIT used in the TAB converter.
The rest of this paper is organized as follows: the overall structure of the SST system used in this paper is briefly introduced in Section 2. Section 3 provides the details about the controller of AC/DC stage for the voltage balancing of DC-links. In Section 4, the DC/DC stage is analyzed including the characteristics of the topology, modeling, and controller design. In Section 5, the HFIT design for high-voltage insulation is discussed. The simulations and experimental results using a 150 kW SST prototype are presented in Section 6 and Section 7, respectively. Finally, the conclusions are provided in Section 8.

2. Structure of the SST Prototype

The upstream grid is a 13.2 kV single-phase MVAC network, but the loads work under the 750 V bipolar DC distribution system. To meet this requirement, the SST prototype is assembled by several subunits that are connected in a cascaded structure (as shown in Figure 1a). Figure 1b shows one subunit consisting of one H-bridge rectifier and one TAB converter. The AC/DC stage is realized using an interfacing inductor and several CHB rectifiers to support the 13.2 kV MVAC. The DC/DC stage consists of three parts, which, organized from left to right, are the medium voltage direct current (MVDC), HFIT, and low voltage direct current (LVDC). On the MVDC side, a neutral point clamped (NPC) circuit is employed to handle a DC-link voltage higher than the rating of semiconductor devices. The NPC generates a 3-level voltage to the HFIT, where the voltage applied to the semiconductor devices is half of the DC-link. In addition, for application to bipolar DC distribution, the HFIT coupled with three windings and the LVDC side is configured as a multi-terminal in which two half-bridge circuits are connected in series. The outputs of the DC/DC stage are connected in parallel, and each subunit has to be rated for only a fraction of the full power.
The voltage of the DC-link is controlled to 2.2 kV in consideration of the topology and the rating of the semiconductor device. In this case, a minimum of ten modules are needed to take into account the line voltage [14], the second harmonic ripple in the DC-link voltages, and the margin reserved for the control strategy [15].

3. A Simple and Practical Voltage Balancing Controller for CHB

One of the main problems that arises when the AC/DC rectifier stage is configured as CHBs in a SST system is the voltage imbalance between DC-links. This imbalance can be caused by unbalanced load conditions, mismatch of the active and passive components, or the floating structure of the high voltage DC-links [16,17,18,19]. This imbalance also increases the stress of the semiconductor device and causes over-voltage or over-current problems that can lead to the collapse of the entire system. The imbalance issue particularly worsens when the SST operates under no load or light load conditions because a small power difference is a significant percentage of the real power and will result in a large voltage imbalance.
To avoid this imbalance problem, an adequate control strategy should be needed to adjust the amount of active power transferred to the individual DC-links. There are several references including control strategies to solve the voltage imbalance of DC-links. In Ref. [20], based on a single-phase d–q control, a voltage balancing controller that adjusts the individual modulation signals is proposed to balance the DC-links. Ref. [21] presented an individual voltage balancing strategy for single-phase STATCOM devices that is based on the CHB multi-level topology. This balancing technique achieves control and balance of the individual DC-links, maintaining among them an equal distribution of the reactive power provided by the H-bridges. In Ref. [22], a voltage balancing controller in the d–q coordinate is proposed to reduce the coupling effect between the voltage balancing controller and the original system controller for the single phase CHB multi-level topology. However, these conventional methods require additional balancing controllers as many as the number of CHB modules. Therefore, as the number of modules increases, the computation time of the additional balancing controllers increases.
In this paper, a simple and practical voltage balancing controller for DC-links is proposed. The proposed balancing controller does not require additional sensors, and no additional control loops required for module expansion. The entire control block diagram for an AC/DC stage is shown in Figure 2. The controller is divided into three parts. The first part is the voltage error compensator for total DC-links. This voltage error compensator is responsible for rectifying MVAC to MVDC. In this process, the voltage error compensator only controls the voltage of the total DC-links, so an additional controller is required for voltage balancing between individual DC-links. The second part is the balancing controller for DC-links. The balancing controller monitors the voltage of all DC-links and sorts them in order of magnitude. Through this sorting process, the maximum voltage and the minimum voltage are obtained. A compensation value proportional to the difference between these two values is generated for DC-link balancing, as shown in the following equations:
I AC _ max _ mag * = I AC _ mag * K p · ( V O _ max V O _ min ) ,
I AC _ min _ mag * = I AC _ mag * + K p · ( V O _ max V O _ min ) .
According to the Figure 2 and Equations (1) to (2), the balancing controller transfers more active power to the DC-link with minimum voltage and less active power to the DC-link with maximum voltage. The voltage deviation of the individual DC-links gradually converges to zero over the processes of voltage sorting, detection of maximum and minimum values, and compensation of active power. The last part is the current error compensator. The current error compensator is responsible for power factor control between the grid voltage and current. The proportional-resonant (PR) controller is used to improve the total harmonic distortion (THD) of the single-phase current and to reduce the steady state error [23]. Finally, the AC current reference values from the current error compensator were applied to the CHB by the phase shift pulse width modulation (PSPWM) scheme for ease of expansion and implementation [24].

4. Analysis of the TAB Converter

The dual active bridge (DAB) converter has been widely used because of its various advantages such as high power density, bidirectional power flow, galvanic isolation, and so on [25,26]. Most DAB converters consist of half-bridge or full-bridge circuits, which produce 2-level square waves across the HFIT. These 2-level DAB converters are usually cascaded for medium and high voltage applications [27,28]. In this structure, the individual voltage of DC-links cannot be higher than the voltage rating of the switching devices used in the 2-level DAB converters. Therefore, there is a disadvantage in that the number of required subunits increases due to the voltage rating of the switching devices when 2-level DAB converters are cascaded in an SST system.
The 3-level DAB converters can overcome this voltage constraint of semiconductor switches to a great extent. Power converters synthesizing more than two voltage levels, such as NPC, and flying capacitor converter (FCC), are traditionally known as 3-level converters. The FCC has a disadvantage in that a complicated switching scheme is required to keep the flying capacitor voltage charged at the appropriate constant level [29]. On the other hand, NPC has an advantage in that all of the switching devices in a leg withstand only half of the individual DC-link voltage using simple switching scheme. Therefore, in this paper, a 3-level NPC circuit is employed on the primary side of the DC/DC converter.
The loads of this DC/DC converter should work under a bipolar DC distribution system. To simply meet this requirement, two 2-port DC/DC converters can be connected in parallel to the individual DC-link. However, this structure has the disadvantage of increasing the number of HFITs and converters. In addition, when a power transfer occurs between the two bipolar DC outputs, the losses are increased because the circulating power is transmitted through two primary circuits. Therefore, the TAB converter using a three windings coupled transformer is advantageous for bipolar DC distribution. Studies have been conducted to expand to a TAB converter using 2-level DAB converters [30,31].
However, unlike the conventional 2-level TAB, the TAB converter used in this paper is configured as follows: a 3-level NPC circuit on the primary side, a three windings coupled transformer, and a secondary side is configured as a multi-terminal in which two half-bridge circuits are connected in series (as shown in Figure 1b). In addition, the outputs of the each TAB converter are connected in parallel, and each subunit has to be rated for only a fraction of the full power.
This section discusses the modeling and controller design procedure of the TAB for this particular structure.

4.1. Modeling of the Three Windings Coupled Transformer

Conceptually, the 2-port DAB converter can be viewed as an interfacing inductor driven at either end by a controlled square-wave voltage source [32]. In the 2-port DAB converter, the interfacing inductance is the sum of the transformer leakage inductance and the external inductance that is needed in order to adjust the output power as well as to extend the zero-voltage switching operation [33]. The interfacing inductor between each port is a dominant parameter as the energy transfer component in the DAB converter [32,33]. Therefore, interfacing inductances between each port should be obtained for the power transfer modeling of the TAB converter.
Theoretically, the extended cantilever model (ECM) for the transformer is convenient in terms of the parameter extraction, since each model parameter can be extracted from a single measurement of an open-circuit voltage or a short-circuit current [34]. For this reason, the ECM is applied for the three windings coupled transformer to extract interfacing inductances between each port, as shown in Figure 3, where L W 1 is the magnetizing inductance seen from the primary winding, W 1 ( L i j , i, j = 0∼2, ij) is the leakage inductance between each pair of windings, and n 2 and n 3 are turns ratios and have the same value in this application.
The equivalent circuit of the TAB converter using an extended cantilever is shown in Figure 4, where ( L i j , i, j = 0∼2, ij) is the leakage inductance between each pair of windings referred to secondary and tertiary sides, the 3-level voltage at its primary NPC circuit is referred to secondary and tertiary sides and it is denoted as V 0 . V 1 and V 2 are the square-wave voltage at its secondary and tertiary bridges, respectively, and P 0 is the amount of power transferred from the DC-link to the input port. P 1 and P 2 are the amount of power supplied to each load from the bipolar output ports.

4.2. Power Transfer Modeling of the TAB Converter

According to the equivalent circuit shown in Figure 4, it can be seen that the power flow paths between any two of the three ports P i j (the power transferred from port i to port j; i, j = 0∼2, ij). P 01 and P 02 are the power flow from the primary side to each bipolar output, respectively. They can be represented by the power flowing through the 2-port DAB converter, consisting of a primary NPC leg and a secondary half-bridge leg. Figure 5a,b show the theoretical voltage and current waveforms of this 2-port DAB converter, where V ac . P is the 3-level voltage produced by the primary NPC leg, α is half of the angular distance for zero state, V ac . S j is the 2-level voltage produced by the secondary or tertiary half-bridge leg, ϕ 0 j is the phase-shift angle between the active bridges, and V L 0 j and I L 0 j are the voltage and current of the interfacing inductor between port 0 and port j, respectively. I o j is the current of the each bipolar output.
The switching scheme for the 2-port DAB converter with a 3-level NPC topology was presented in Refs. [35,36]. Based on the value of ϕ 0 j , there may be two cases such as Case I: 0 ≤ ϕ 0 j α , Case II: α < ϕ 0 j π /2. Referring to Figure 5, the power equations for two cases can be obtained as follows:
Case I : P 0 j = n V 0 V j 2 ω L 0 j ϕ 0 j · ( 1 2 α π ) ,
Case II : P 0 j = n V 0 V j 2 ω L 0 j · ( ϕ 0 j ϕ 0 j 2 π α 2 π ) , ( j = 1 , 2 ) ,
where ω is the switching angular frequency.
According to Equations (3) and (4), the smaller the value of α , the more power can be transferred to the load. Therefore, α should theoretically have the minimum value for freewheeling. This means that the 2-port DAB converter with a 3-level NPC topology works in Case I over a very short interval in practice. In addition, the amount of power calculated by Equations (3) and (4) are almost the same under light load conditions. Considering the above statements, the power equation of the 2-port DAB converter with a 3-level NPC topology may be considered as the generalized equation and can be rewritten as follows:
P 0 j n V 0 V j 2 ω L 0 j · ( ϕ 0 j ϕ 0 j 2 π ) , ( j = 1 , 2 ) , ( 0 ϕ 0 j π 2 ) .
Equation (5) is equivalent to the equation of a 2-level half-bridge DAB converter because the α term that generates the zero-state in the NPC leg is removed. Therefore, P 12 , which is another power flow between two bipolar DC outputs, can also be obtained from Equation (5). As a result, in the TAB converter, the amount of power between any two of the three ports can be obtained from Equation (5). To reduce computing burden, (5) can be simplified as follows through the fundamental approximation in Ref. [32]:
P i j 4 V i V j π 2 ω L i j · ϕ i j , ( i , j = 0 2 , i j ) , ( 0 ϕ i j π 2 ) .
According to (6), the amount of power flowing through port 1 and port 2 are calculated as follows, respectively:
P 1 = P 01 + P 21 = ( 4 V 0 V 1 π 2 ω L 01 + 4 V 1 V 2 π 2 ω L 12 ) · ϕ 01 4 V 1 V 2 π 2 ω L 12 · ϕ 02 ,
P 2 = P 02 + P 12 = 4 V 1 V 2 π 2 ω L 12 · ϕ 01 + ( 4 V 0 V 2 π 2 ω L 02 + 4 V 1 V 2 π 2 ω L 12 ) · ϕ 02 .
Equations (7) and (8) can be rewritten in matrix form as follows:
P = G · ϕ , P = p 1 p 2 , ϕ = ϕ 01 ϕ 02 , G = g 11 g 12 g 21 g 22 ,
where G is the transfer function matrix that describes the system parameters.
As shown in (9), the TAB converter is a two-input and two-output (TITO) system. The TITO system is characterized by significant interactions between their inputs and outputs. Because of these interactions, a control action in one loop gets transmitted to the other loop as a disturbance. Therefore, decoupling techniques are required to eliminate or minimize the interaction. The simplified decoupling technique is most widely used in practice because of its robustness and simple decoupling network for TITO systems [37]. Figure 6 shows the control block diagram with simplified decoupling. The decoupler transfer function matrix D and the decoupled transfer function matrix T can be given as in (10) and (11), respectively:
D = G 1 · T = 1 g 12 g 11 g 21 g 22 1 ,
T = g 11 g 12 g 21 g 22 0 0 g 22 g 12 g 21 g 11 .

4.3. Controller Design

After applying the simplified decoupling, the decoupled controller is represented by two single-input and single-output (SISO) controllers as shown in Figure 7. Two SISO controllers hold each bipolar DC output voltage at a set point by automatically adjusting control signals as follows. The reference voltage and the measured voltage are given as inputs to the comparator, from which an error signal is passed as input to the integral proportional (IP) controller. The use of the IP controller enhances the system dynamic response and reduces undesirable peak overshoot compared to the proportional integral (PI) controller [38]. The IP controller generates the control signal based on the error signal. The output of the IP controller sets the output current of the converter required to keep the output capacitor voltage at the appropriate constant level. In addition, a load current feedforward is added into the controller to improve the dynamic response against the load changes [39].
Using the formula of the IP controller and the mathematical relationship between the voltage and current of the capacitor, the closed-loop transfer function is given by:
H ( s ) = V o j V o j * = K i C o j s 2 + K p C o j s + K i C o j ,
where C o j is the output capacitance, K p and K i , all non-negative, denote the coefficients for the proportional and integral terms, respectively. To order the closed-loop system, it is necessary to choose the coefficients K p and K i .
The transfer function of a second-order system in standard form is given by:
F ( s ) = ω n 2 s 2 + 2 ζ ω n s + ω n 2 .
By comparing (12) and (13), the resulting IP controller parameters are obtained by:
K p = 2 ζ ω n 2 C o j , K i = C o j ω n 2 ,
where ζ is the damping factor and ω n is the natural frequency.
The outputs of the DC/DC stage are connected in parallel, and each subunit has to be rated for only a fraction of the full power. The primary goal of these parallel-connected converters is to share the load current among the constituent converters. Improper load sharing can lead to the converter overloading and overheating, which decreases the system reliability and can eventually lead to the failure of the overall system [40]. Therefore, a robust control technique that ensures synchronizing and proper load sharing is essential to ensure the stability and reliability of the system. Figure 8 shows the control block diagram of the current-sharing controller based on the outer loop regulation (OLR) mode studied in Ref. [41]. The OLR mode uses the current-sharing error signal to adjust the voltage reference of the outer voltage loop until equal load current distribution is achieved. The current data of each module is transmitted via the CAN protocol, and the average current value can be calculated based on this information. The current-sharing error signal is processed through the average current method (ACM), which compares the difference between the average current and the individual current. The key features of the scheme, generally, are that the reference voltage, output voltage feedback, and the voltage compensator of each converter module are independent.

5. Transformer

The primary windings of the HFIT are electrically connected to the 13.2 kV MVAC network, as shown in Figure 1a. In addition, the secondary and tertiary windings of the HFIT are electrically connected to the 750 V bipolar LVDC and are floated with respect to the ground of the MVAC network. In this structure, the minimum requirement of dielectric strength between the primary and other windings is 22 kV, which corresponds to the total DC-link voltage [42]. Similarly, the minimum requirement of dielectric strength between the core and windings is 22 kV. The dielectric strength of the HFIT was selected to be 50 kV, which is about 2.3 the former strength of 22 kV, according to the IEEE standard in Ref. [43].
Figure 9 shows the guard and bobbin structure of the HFIT to ensure the high dielectric strength. The guard provides an electrical insulation between the core and the windings. The bobbin provides an electrical insulation between the windings through the section structure. Both guard and bobbin were made of Teflon material considering processability, low permittivity, and high voltage insulation [44]. The thickness of the insulator was determined by electric field distribution and intensity, which is difficult to calculate due to the nonuniform electric field. Therefore, to determine the thickness of the guard and section layer, the electric field distribution and intensity were simulated via ElecNet as shown in Figure 10. Based on the structure of Figure 9, the thickness of guard and section layer was temporarily set to 5 mm and 50 kV is applied between the primary and other windings. It can be seen that the maximum field strength induced in the guard and section layer was 17 kV/mm, while the dielectric strength of Teflon material is usually 20 kV/mm in vacuum. Therefore, the thickness of the guard and section layer was selected as 5 mm considering margin. In addition, the empty space between the bobbin, guard, and windings was filled with molding fluid to prevent partial discharge and surface discharge. SYLGARD 170 A/B was selected as the molding fluid, considering the thermal conductivity, dielectric strength, viscosity [45].

6. Simulation

Figure 11 shows the simulation waveform employed to verify the DC-link voltage balancing capability of the AC/DC stage. Simulation parameters are listed in Table 1. The AC/DC stage was realized using an interfacing inductor and ten CHB rectifiers to support the 13.2 kV MVAC. As mentioned in Section 3, this structure can cause the voltage imbalance between DC-links. The simulation sequence is as follows. Initially, the active power flowing through all of the CHB rectifiers is 150 kW (rated power) and the voltage imbalance is caused by unbalanced load conditions (up to 20%). The voltage of DC-links remains unbalanced because the balancing algorithm is forcedly deactivated until t = 0.4 s. The balancing algorithm is activated at t = 0.4 s, and the voltage of DC-links gradually converges to 2.2 kV. At t = 0.6 s, the load of subunit10 is increases from 13.6 kW to 15.8 kW, and the load of subunit6 is reduced from 16.6 kW to 14.4 kW. At t = 0.8 s, the CHB rectifiers act like an inverter to transfer 150 kW of power from the DC-links to the MVAC. It can be seen that the DC-link voltage is balanced in all sequences after the balancing algorithm is activated.
Figure 12 shows the simulation waveform used to verify the decoupling capability of the DC/DC stage. Simulation parameters are also listed in Table 1. The simulation sequence is as follows. At t = 0.1 s, the voltage reference of port 1 is changed from 720 to 750. At t = 0.14 s, the voltage reference of port 2 is changed from 780 to 750. At t = 0.18 s, the load of port 1 is increased from no load to full load (7.5 kW) in a stepwise manner. At t = 0.22 s, the load of port 2 is also increased from no load to full load (7.5 kW). At t = 0.26 s, full power is injected into the power grid through port 1 (−7.5 kW). At t = 0.3 s, full power is injected into the power grid through port 2 (−7.5 kW). It can be seen that two SISO controllers hold each bipolar DC output voltage at a set point in all sequences. In addition, the results indicate that interactions between their inputs and outputs are well suppressed.
Figure 13 shows the simulation waveform employed to verify the current sharing controller of the DC/DC stage. In the simulation, the number of output parallel-connected TAB converters is limited to two because of the computing burden. At t = 0.06 s, the improper load-sharing is caused by the non-identical voltage sensors (difference up to 2%). Initially, improper load-sharing occurs, but soon all load currents gradually converge to their average value. In addition, at a random timing, the load of each port is increased from no load to full load and full power is injected into the DC-links through TAB converters. It can be seen that the load sharing is good in all sequences after the current sharing controller is activated.

7. Experiment

In order to test the hardware and software beyond the numerical simulations, a 150 kW single-phase 21-level SST prototype was designed and assembled, and is shown in Figure 14. As mentioned in Section 2, the AC/DC stage was realized using an interfacing inductor and ten CHB rectifiers to support the 13.2 kV MVAC. In the DC/DC stage, for application to bipolar DC distribution, the HFIT coupled with three windings and the LVDC side is configured as a multi-terminal in which two half-bridge circuits are connected in series. The outputs of DC/DC stage are connected in parallel, and ten subunits have to be rated for only a fraction of the full power. The entire operation of the SST system was programmed by DSP and CPLD processors. The AC/DC stage and DC/DC stage have its own DSP and CPLD controllers. The required data between them is shared by CAN protocol. The parameters adopted in both simulation and experiment are the same.
Figure 15 shows a waveform used to verify the DC-link voltage balancing capability of the AC/DC stage. Due to the limitations of the measuring equipment, only V dclink 1 V dclink 3 was measured by the oscilloscope. The remaining voltage of DC-links was monitored via software such as LabVIEW (Ver 13.0, National Instrument, Austin, TX, USA). It can be seen that the voltage of DC-links was initially unbalanced due to finite tolerances in the power stage and control parameters when the balancing controller was deactivated. However, the voltage of DC-links started converging to set point after the balancing controller was activated. This indicates that the balancing controller works properly.
The steady-state waveform of a TAB converter in several load conditions are depicted as follows. Figure 16a shows a waveform when the TAB converter is operating under no load conditions. Figure 16b shows a waveform when the amount of power transferred from port 1 to load is 7.5 kW, while port 2 has no load. Figure 16c shows a waveform when the amount of power transferred from port 2 to load is 7.5 kW, while port 1 has no load. Figure 16d shows a waveform when the amount of power transferred from each port to load is 7.5 kW (total 15 kW, rated power of one subunit). The TAB converter holds each bipolar DC output voltage at a set point in several load conditions. In addition, the experimental voltage and current waveforms have a close match with the aforementioned analysis in Section 4.
Figure 17 shows a waveform used to verify the decoupling capability of the TAB converter. The loads of each port are changed in a stepwise manner at a random timing. Due to the limitation of the load device, the load that is changed stepwise on each port is limited to a maximum of 20 kW. It can be seen that the result indicates that interaction between each port is well suppressed.
The paralleling experiment performed to verify the current-sharing controller of the DC/DC stage is as follows. The number of output parallel-connected TAB converters was ten. However, there are two limitations to measure the waveforms at the laboratory level. First, only the output currents of five subunits are measured in the oscilloscope due to the limitations of the measuring equipment. The remaining output currents were monitored via software such as LabVIEW. Second, due to the limitation of the load device, the amount of power transferred from the ten subunits to loads was limited to 50 kW, which corresponds to 1/3 of the rated power. The rated operation of the SST prototype will be verified later through a field test. Figure 18a,b show the current waveforms of the bipolar DC/DC output stage (denoted as I O _ 1 y , I O _ 2 y , y is the subunit index, y = 1∼5). It can be seen that all output currents remain balanced under various load conditions.

8. Conclusions

This paper presents the implementation of a single-phase 150 kW prototype of an SST for application between a 13.2 kV MVAC network and a 750 V bipolar DC distribution. The prototype of the SST has ten cascaded subunits in consideration of the device rating and MI. Each subunit consists of an AC/DC stage and a DC/DC stage. In the AC/DC stage, a simple balancing controller is provided to prevent the voltage imbalance of DC-links due to the cascade structure. In the DC/DC stage, a simplified decoupling technique is provided to suppress the interaction between bipolar DC outputs. A paralleling scheme to ensure proper load sharing is provided for the parallel-connected DC/DC stage. In addition, the design of the HFIT to ensure high dielectric strength is discussed. All algorithms were validated through simulations and experiments.

Author Contributions

All the authors gave equal contributions in writing and revising the paper.

Acknowledgments

This research was supported by the KEPCO research institute.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Structure of the SST prototype system: (a) simplified structure of the overall SST prototype system; (b) detailed structure of one subunit.
Figure 1. Structure of the SST prototype system: (a) simplified structure of the overall SST prototype system; (b) detailed structure of one subunit.
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Figure 2. The entire control block diagram for AC/DC stage.
Figure 2. The entire control block diagram for AC/DC stage.
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Figure 3. Extended cantilever model for the three windings coupled transformer.
Figure 3. Extended cantilever model for the three windings coupled transformer.
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Figure 4. Equivalent circuit for the TAB converter.
Figure 4. Equivalent circuit for the TAB converter.
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Figure 5. Theoretical waveforms of the 2-port DC/DC converter: (a) Case I (0 ≤ ϕ 0 j α ); (b) Case II ( α < ϕ 0 j π /2).
Figure 5. Theoretical waveforms of the 2-port DC/DC converter: (a) Case I (0 ≤ ϕ 0 j α ); (b) Case II ( α < ϕ 0 j π /2).
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Figure 6. Control block diagram with simplified decoupling.
Figure 6. Control block diagram with simplified decoupling.
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Figure 7. Block diagram of the voltage controller converted to SISO system.
Figure 7. Block diagram of the voltage controller converted to SISO system.
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Figure 8. Control block diagram of current sharing controller.
Figure 8. Control block diagram of current sharing controller.
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Figure 9. Arrangement of windings and structure of bobbin.
Figure 9. Arrangement of windings and structure of bobbin.
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Figure 10. Electric field simulation results of section bobbin structure.
Figure 10. Electric field simulation results of section bobbin structure.
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Figure 11. Simulation waveform to verify the voltage balancing capability of the AC/DC stage.
Figure 11. Simulation waveform to verify the voltage balancing capability of the AC/DC stage.
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Figure 12. Simulation waveform to verify the decoupling capability of the DC/DC stage.
Figure 12. Simulation waveform to verify the decoupling capability of the DC/DC stage.
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Figure 13. Simulation waveform to verify the current sharing controller.
Figure 13. Simulation waveform to verify the current sharing controller.
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Figure 14. Single-phase 21-level SST prototype.
Figure 14. Single-phase 21-level SST prototype.
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Figure 15. DC-link voltage waveform when balancing controller is activated.
Figure 15. DC-link voltage waveform when balancing controller is activated.
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Figure 16. Steady-state waveform of a TAB converter: (a) under the no load condition; (b) when the amount of power transferred from port 1 to load is 7.5 kW; (c) when the amount of power transferred from port 2 to load is 7.5 kW; (d) when the amount of power transferred from each port to load is 7.5 kW.
Figure 16. Steady-state waveform of a TAB converter: (a) under the no load condition; (b) when the amount of power transferred from port 1 to load is 7.5 kW; (c) when the amount of power transferred from port 2 to load is 7.5 kW; (d) when the amount of power transferred from each port to load is 7.5 kW.
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Figure 17. The decoupling waveform of the TAB converter when the loads of each port are changed at a random timing (n is the subunit index, n = 1∼10).
Figure 17. The decoupling waveform of the TAB converter when the loads of each port are changed at a random timing (n is the subunit index, n = 1∼10).
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Figure 18. Current sharing waveforms: (a) output currents corresponding to Port 1; (b) output currents corresponding to Port 2.
Figure 18. Current sharing waveforms: (a) output currents corresponding to Port 1; (b) output currents corresponding to Port 2.
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Table 1. System parameters.
Table 1. System parameters.
ParameterSymbolValueUnit
Number of subunits 10
Line inductance L in 40mH
DC capacitance in DC-link C link 370uF
Rated DC voltage of DC-link V link 2.2kV
Switching frequency of the AC/DC stage f sw . rec 1.8kHz
DC capacitance in LVDC C o 1mF
Rated DC voltage of LVDC V o ±750V
Switching frequency of the DC/DC stage f sw . conv 10kHz
HFIT turn ration0.34
Interfacing inductance between MVDC and LVDC L 0 j 140uH
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