Next Article in Journal
An SAR-ISAR Hybrid Imaging Method for Ship Targets Based on FDE-AJTF Decomposition
Previous Article in Journal
Supercapacitor Electro-Mathematical and Machine Learning Modelling for Low Power Applications
Article

Design and Application Space Exploration of a Domain-Specific Accelerator System

1
School of Electronic Science and Engineering, Nanjing University, Nanjing 210023, China
2
Nanjing Research Institute of Electronics Technology, Nanjing 210013, China
*
Author to whom correspondence should be addressed.
Electronics 2018, 7(4), 45; https://doi.org/10.3390/electronics7040045
Received: 23 January 2018 / Revised: 18 March 2018 / Accepted: 27 March 2018 / Published: 29 March 2018
Domain-specific accelerators are a reaction adapting to device scaling and the dark silicon era. This paper describes a radar signal processing oriented configurable accelerator and the application space exploration of the system. The system is built around accelerator engines and general-purpose processors (GPPs) that make it suitable for intensive computing kernel acceleration and complex control tasks. It is geared toward high-performance radar digital signal processing; we characterize the applications and find that each of them contains a series of serializable kernels. Taking advantage of this discovery, we design an algorithm pool that shares the same computation resource and memory resource, and each algorithm is size reconfigurable. On the other hand, shared on-chip addressable scratchpad memory eliminates unnecessary explicit data copy between accelerators. Performance of the system is evaluated from measurements performed both on an FPGA SoC test chip and on a prototype chip fabricated by CMOS 40 nm technology. The experimental results show that for different algorithms, the proposed system achieves 1.9× to 10.1× performance gain compared with a state-of-the-art TI DSP chip. In order to characterize the application of the system, a complex real-life task is adopted, and the results show that it can obtain high throughput and desirable precision. View Full-Text
Keywords: dark silicon; accelerator system; high-performance radar processing; shared scratchpad memory; FPGA prototyping; chip testing; application space exploration dark silicon; accelerator system; high-performance radar processing; shared scratchpad memory; FPGA prototyping; chip testing; application space exploration
Show Figures

Figure 1

MDPI and ACS Style

Feng, F.; Li, L.; Wang, K.; Fu, Y.; He, G.; Pan, H. Design and Application Space Exploration of a Domain-Specific Accelerator System. Electronics 2018, 7, 45. https://doi.org/10.3390/electronics7040045

AMA Style

Feng F, Li L, Wang K, Fu Y, He G, Pan H. Design and Application Space Exploration of a Domain-Specific Accelerator System. Electronics. 2018; 7(4):45. https://doi.org/10.3390/electronics7040045

Chicago/Turabian Style

Feng, Fan, Li Li, Kun Wang, Yuxiang Fu, Guoqiang He, and Hongbing Pan. 2018. "Design and Application Space Exploration of a Domain-Specific Accelerator System" Electronics 7, no. 4: 45. https://doi.org/10.3390/electronics7040045

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop