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Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study

by Denis Becker 1,2,3,*, Matthieu Moy 2,3 and Jérôme Cornet 1
STMicroelectronics, F-38019 Grenoble, France
Univ. Grenoble Alpes, VERIMAG, F-38000 Grenoble, France
CNRS, VERIMAG, F-38000 Grenoble, France
Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in the IEEE International Symposium on Rapid System Prototyping (RSP) as Becker, D.; Moy, M.; Cornet, J. “Challenges for the Parallelization of Loosely-Timed SystemC Programs”. RSP, October 2015. It also contains material presented at DUHDe 2016 (Workshop on Design Automation for Understanding Hardware Designs, without proceedings) as “SycView: Visualize and Profile SystemC Simulations”.
Academic Editors: Frédéric Rousseau, Gabriela Nicolescu, Amer Baghdadi and Mostafa Bassiouni
Electronics 2016, 5(2), 22;
Received: 31 March 2016 / Revised: 28 April 2016 / Accepted: 10 May 2016 / Published: 17 May 2016
Transaction level models of systems-on-chip in SystemC are commonly used in the industry to provide an early simulation environment. The SystemC standard imposes coroutine semantics for the scheduling of simulated processes, to ensure determinism and reproducibility of simulations. However, because of this, sequential implementations have, for a long time, been the only option available, and still now the reference implementation is sequential. With the increasing size and complexity of models, and the multiplication of computation cores on recent machines, the parallelization of SystemC simulations is a major research concern. There have been several proposals for SystemC parallelization, but most of them are limited to cycle-accurate models. In this paper we focus on loosely timed models, which are commonly used in the industry. We present an industrial context and show that, unfortunately, most of the existing approaches for SystemC parallelization can fundamentally not apply in this context. We support this claim with a set of measurements performed on a platform used in production at STMicroelectronics. This paper surveys existing techniques, presents a visualization and profiling tool and identifies unsolved challenges in the parallelization of SystemC models at transaction level. View Full-Text
Keywords: SystemC; TLM; hardware modeling; parallelization; simulation; loose timing SystemC; TLM; hardware modeling; parallelization; simulation; loose timing
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Becker, D.; Moy, M.; Cornet, J. Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study. Electronics 2016, 5, 22.

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