Beyond the Interconnections: Split Manufacturing in RF Designs
Abstract
:1. Introduction
2. Split Manufacturing in the Digital Domain
3. RF Design Flow
3.1. RF Design Procedures
3.2. Power Amplifier Modeling and Analysis
4. Split Manufacturing in RF Circuits
- Scenario I: Remove only the top metal layer from the layers to generate FEOL. Since the inductors are often located in the top layer, the FEOL foundry does not have the information of interconnections through the top metal layer, as well as the inductor locations and sizes.
- Scenario II: Remove both the top and the second from the top metal layers. In this scenario, two upper metal layers are removed so that both inductors and capacitors are missing from the FEOL layout, because the capacitors are often built through the top two metal layers.
- Scenario III: Design obfuscation. For RF designs, inductors are always located in metal rings, and lower metal layers will be removed inside the rings for performance optimization. Therefore, the rings themselves, which contain multiple metal layers, would indicate the positions and approximate sizes of inductors. Similarly, the lower metal layers will not be used where capacitors are located. Therefore, attackers in both Scenarios I and II may learn the precise positions of the removed inductors/capacitors and may even further estimate their sizes. To further increase the security level, but still avoid performance overhead, we propose an obfuscation technique during the design phase to insert non-functional rings and to create empty zones in the original design. Using this method, it becomes more difficult for attackers to pin down the location, the count and the sizes of passive components.
4.1. The First Example
4.1.1. Scenario I: Removal of Metal6 Layers (Inductors)
4.1.2. Scenario II: Removal of Metal5 and Metal6 Layers (Capacitors and Inductors)
4.1.3. Scenario III: Obfuscation Techniques
5. Experimentation
5.1. Scenario I: Removal of Metal6 Layers (Inductors)
5.2. Scenario II: Removal of Metal5 and Metal6 Layers (Capacitors and Inductors)
5.3. Scenario III: Obfuscation Techniques
6. Discussion
7. Conclusions
Author Contributions
Conflicts of Interest
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Bi, Y.; Yuan, J.S.; Jin, Y. Beyond the Interconnections: Split Manufacturing in RF Designs. Electronics 2015, 4, 541-564. https://doi.org/10.3390/electronics4030541
Bi Y, Yuan JS, Jin Y. Beyond the Interconnections: Split Manufacturing in RF Designs. Electronics. 2015; 4(3):541-564. https://doi.org/10.3390/electronics4030541
Chicago/Turabian StyleBi, Yu, Jiann S. Yuan, and Yier Jin. 2015. "Beyond the Interconnections: Split Manufacturing in RF Designs" Electronics 4, no. 3: 541-564. https://doi.org/10.3390/electronics4030541
APA StyleBi, Y., Yuan, J. S., & Jin, Y. (2015). Beyond the Interconnections: Split Manufacturing in RF Designs. Electronics, 4(3), 541-564. https://doi.org/10.3390/electronics4030541