Design and Analysis of FSM-Based AES Encryption on FPGA Versus MATLAB Environment

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The manuscript reports an FSM-based implementation of AES-128 encryption/decryption developed and validated in MATLAB and synthesized for an Artix‑7 FPGA using VHDL. The authors claim functional equivalence between MATLAB and FPGA outputs, and present performance metrics (execution time, throughput, area usage, and an efficiency metric in Mbps/slice). The paper positions the FSM approach as a resource‑efficient alternative to fully pipelined FPGA AES designs and argues its suitability for lightweight embedded cryptography.

Some suggestions for improving the manuscript:

Please check that you have followed all the requirements of the manuscript formatting template.
Please check that you have interpreted all abbreviations in the text at their first appearance.
Please cite the specific literary source from which they were borrowed for each table/figure/algorithm, etc., that are not the author's.
The quality of some figures and formulas is unsatisfactory (they look very blurry and are not readable). Please improve the quality. Some figures are located before their citation in the text. There is a citation of non-existent figures - Figure 4.20.
There is some text that is repeated - for example, lines 207, 208: The Advanced Encryption Standard (AES) is one of the most widely used symmetric encryption algorithms, known for its security, speed, and efficiency in both hardware and software implementations. Line 227: The AES is a symmetric key cryptographic algorithm widely adopted for securing digital data. The text could be cleared.
The subfigure text in Fig. 1 and Fig. 2 is the same! Fig. 2 should be for decryption.
mS -> ms (for seconds).

The Methods lack sufficient detail to reproduce the work. Please provide:

Full VHDL design organization (entity/module names, interfaces, clock/reset scheme).

Testbench description and how inputs were applied (timing, stimulus vectors).

Exact FPGA part number and toolchain settings (device package, speed grade). Please clarify which tools and versions were actually used for synthesis/place‑and‑route and provide the implementation flow (synthesis, implementation, bitstream generation).

Clock frequency constraints and how Fmax was determined (post‑place‑and‑route timing report or synthesis estimate?).

How many independent runs were performed, and whether reported timings are averages, minima, or single measurements.

The throughput and efficiency calculations need to be shown step‑by‑step with numeric values.

The efficiency metric (Mbps/slice) must be computed from clearly reported occupied slices and throughput. Provide a table listing LUTs, FFs, BRAM, DSPs, slices used, and the clock frequency for the reported design. Without these, the efficiency claim cannot be verified.

The manuscript cites several prior FPGA AES implementations but does not present a rigorous, side‑by‑side comparison. Provide a comparative table that lists for each referenced work: device family, resource usage, Fmax, latency (cycles), throughput, and efficiency (Mbps/slice). Discuss differences in architecture (iterative/FSM vs pipelined vs partially parallel) and justify why the proposed FSM design is preferable for the target application domain.

The MATLAB timing methodology is not described in sufficient detail. State the MATLAB version, the hardware used for the MATLAB tests (CPU model, RAM), and whether MATLAB timings were measured using tic/toc or other profiling tools. Clarify whether MATLAB used vectorized operations or a byte‑oriented implementation and whether any MATLAB JIT or MEX acceleration was used. These details are necessary to make fair comparisons.

The manuscript briefly mentions a PN sequence generator and LFSR-based S‑box/key generation in the literature review, but does not discuss the security implications of design choices. If the authors propose any non-standard modifications to AES (e.g., dynamic S‑box), they must provide a security analysis or explicitly state that the implementation uses the standard AES S‑box and key schedule. Any deviation from the AES standard must be justified and analyzed for cryptographic strength.

Comments on the Quality of English Language

English could be improved to more clearly express the research.

Author Response

All the response can be found in the file uploaded.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

1. Eliminate unnecessary explanations of current MATLAB studies. Clearly define the specific gap that this paper addresses in 1–2 sentences.
2. FSM diagrams (Figures 1 and 2) must be clear and not duplicated. Descriptions of FPGA memory blocks are overly detailed and can be condensed. MATLAB pseudo-code and algorithms should be abbreviated or relocated to an appendix.
3. Enhance the quality of figures for waveforms and RTL schematics. Ensure consistent time units (ms versus seconds). Specify precisely how MATLAB time was measured—was it a single block, averaged runs, or the entire dataset?
4. Refrain from reiterating paragraphs already mentioned in the introduction. Compare your architecture not only with MATLAB-based studies but also with recent lightweight AES FPGA designs.
5. There are inconsistencies in figure numbering (Figure 1 is repeated). The formatting of tables (especially Table 6) needs better alignment and a consistent layout.
6. Include a complete list of VHDL modules, simulation environment settings, and tool versions in a concise table. Indicate the FPGA IO timing constraints applied during synthesis.
7. Highlight the distinctive FSM-controlled reusable component architecture as your primary contribution.

Comments on the Quality of English Language

1. Several sentences are lengthy and grammatically incorrect. A professional language edit is advisable.

Author Response

All response can be found in the file uploaded.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Dear Authors,
thank you for the corrections you made to the manuscript and for your responses! I think the quality of the manuscript has improved significantly, but there is still room for some work in the following areas:

1) Reproducibility gaps – key implementation details are missing (full VHDL/module names and interfaces, testbench stimulus, exact post-implementation timing/resource reports).

2) Benchmarking clarity – MATLAB timing and FPGA timing provenance are not reported in a verifiable way.

3) Statistical rigor – results appear to come from a single run; variability and averaging are not shown.

4) Language and presentation – English needs polishing and some text is repetitive.

The study is promising and of interest to readers working on embedded cryptography and FPGA implementations, but the authors must substantially improve methodological transparency, figures/tables, and English before the manuscript can be accepted.

 

Comments on the Quality of English Language

English could be improved.

Author Response

All the response can be found in the file uploaded.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The manuscript has been sufficiently improved to warrant publication in Electronics.

Comments on the Quality of English Language

The manuscript has been sufficiently improved to warrant publication in Electronics.

Author Response

All the response can be found in the file uploaded.

Author Response File: Author Response.pdf