Research Progress and Design Considerations of High-Speed Current-Mode Driver ICs

Abstract

The current-mode logic (CML) driver has evolved alongside integrated circuit (IC) technology. Its typical structure contains a tail current source, differential amplifying transistors, and load resistors. It is widely used in modern optical transceivers and other serial link transceivers, and is compatible with various processes, including CMOS, SiGe BiCMOS, and InP DHBT. The basic performance indicators of CML driver include gain, bandwidth, power, and total harmonic distortion (THD). For different application scenarios, different tail currents and load resistance are required. Nowadays, as the performance requirements for drivers in various applications continue to increase, more techniques need to be employed to balance high speed, high output amplitude, high linearity, and low power, such as bandwidth expansion techniques, linearity improvement techniques, and gain control techniques. In this review, the electrical characteristics of basic CML circuits are highlighted and compared with other interface level standards. The advancement of CML drivers is summarized. Emerging CML structures and performance enhancement technologies are introduced and analyzed. Design considerations are concluded in terms of the challenges faced by high-speed drivers. The review provides comparative study and comprehensive reference for designers.

1. Introduction

Analog or digital signal transmission is inevitable in modern electronic equipment. Many interface standards have been proposed for different application scenarios, from low-speed Transistor–Transistor Logic (TTL) [1], Complementary Metal-Oxide–Semiconductor (CMOS) logic standards to high-speed Low-Voltage Differential Signal (LVDS) [2], Low-Voltage Positive Emitter Couple Logic (LVPECL), and Current Mode Logic (CML) standards. These interface standards are different in level, transfer rate, and coupling, as summarized in

Table 1. Comparison of typical interface standards.

	TTL	CMOS	LVDS	ECL PECL LVPECL	CML
Level range (V)	0∼5	0∼VCC	0.85∼1.55	−1.72∼−0.88 3.28∼4.12 1.58∼2.42	VCC-0.4 ∼VCC
Max. rate level (Hz)	100 M	100 M	1 G	10 G	10 G
Power level	High	Low	Low	High	Medium
Single/differential	Single	Single	Dif.	Dif.	Dif.
Coupling	AC	DC	DC	DC/AC	DC/AC

. In the early days of the electronics industry, TTL and CMOS standards were commonly applied to computing and industrial control equipment. As the data rates in these applications increased, TTL gradually became obsolete. With the continuous scaling of CMOS processes, the maximum switching rate of MOS transistors is continuously increasing, and the CMOS logic level has gradually dropped from 5 V to below 1.2 V due to the falling of transistors’ breakdown voltage, which cuts the power consumption, and also noise margin. Currently, CMOS logic level is widely used in digital circuits such as analog-to-digital/digital-to-analog converters (ADC/DAC), sensors, and memory devices. ECL differential circuit has strong driving strength and high speed, but consumes a relatively large amount of power. PECL evolves from the ECL standard and uses a +5 V power supply, which simplifies power system design. LVPECL reduces the supply voltage to 3.3 V or 2.5 V, further lowering power consumption. It is commonly used for clock distribution networks and fiber optic communication module interfaces. LVDS is specifically designed for low-voltage, low-power, differential, end-to-end signal transmission. It is used for electronic products such as PCB-level interfaces. CML is featured by high speed, medium power consumption, and compatibility with process and interfaces. Its simple differential structure has the advantages of common-mode noise rejection and low parasitics, enabling data transmission at tens of gigabits per second. After minor structural modifications, different logical functions can be achieved, such as latch, flip-flop (FF), multiplier, multiplexer, divider, and exclusive OR [3,4,5,6].

The main amplifying transistors in the CML circuit operate in switching mode when transmitting digital “0/1” signals and in linear amplification mode when transmitting analog signals. Similarly, analog functional circuits, such as comparator, mixer, and active balun, can be implemented through slight structural adaptations of CML-based topologies. As for high-speed CML drivers, the criteria for evaluating the performance include input and output return loss, bandwidth, gain, power consumption, energy efficiency, and total harmonic distortion (THD). Indicators for RF amplifiers such as 1 dB compression point ($P_{1\mathrm{dB}}$) can also be used for driver linearity evaluation. As data rate increases, more and more design challenges occur to meet and balance these criteria. Moreover, drivers are required to implement more complex functions to cater to a wide variety of scenarios. In recent years, many studies have focused on innovative optimization of CML drivers for higher data rates and more diverse voltage level standards. The objective of this review is to summarize these innovative advancements and practical experiences. The overview diagram is depicted in Figure 1. Section 2 introduces the basic structure, principles, and definitions of various technical parameters of the CML driver, and recent CML research progress is summarized. Section 3 and Section 4 discuss the bandwidth and amplitude optimization techniques in typical CML structures. Section 5 introduces various CML driver structures for different applications. Design considerations of CML circuits are discussed in Section 6, and Section 7 finally concludes the review and discusses future prospects.

2. Research Background and Progress

2.1. CML Circuit Principles

As shown in Figure 2, the basic CML structure is an HBT or MOS differential pair with a constant current source and load resistors, where the logic function is implemented by steering the current between alternate paths. Common-base or common-gate transistors can be employed to construct a cascode structure for high-supply headroom applications. When $V_{in}$ and $V_{ip}$ are equal, the two branches are symmetrical, and the currents are equal to $I_s/2$, resulting in equal $V_{on}$ and $V_{op}$. When a differential small signal is input into the amplifier, the circular current across the two branches is $g_m{v}_{in,dm}/2$. Thus, the differential output voltage can be derived by calculating the voltage difference across the resistors R:

$$v_{out}=2R{i}_c=g_{m}R{v}_{in,dm}$$

(1)

Thus, the voltage gain $A_v$ is $g_{m}R$. The difference is that the transconductance $g_m$ is $I_s/(V_{GS}-V_{th})$ for the MOSFET pair, and $I_s/(2kT/q)$ for the heterojunction bipolar transistor (HBT) pair. The input impedance of MOSFET is infinite while HBT is not. When the input signal is large enough to drive the tail current through only one branch, the differential pair works as a limiting amplifier (LA), whose output amplitude depends on the tail current and load resistor ($I_{s}R$).

For the HBT-based differential pair, the linear input range is around $4v_T$, while the counterpart for the MOSFET differential pair is $\sqrt{2}(V_{GS}-V_{th})$ [7]. Under the same conditions, the linear input range of the HBT differential pair is smaller than that of the MOSFET differential pair, while the gain is opposite, which means that the input amplitude of the MOSFET amplifier reaching the maximum output amplitude is higher.

The transfer function considering the output capacitance is

$$H\left(s\right)={\displaystyle \frac{V_{out}}{V_{in}}}={\displaystyle \frac{g_{m}R}{1+sR{C}_L}}$$

(2)

Typically, the dominant pole that determines the small signal bandwidth depends on the RC constant of the output node: ${\omega }_{-3\mathrm{dB}}=1/R{C}_L$. $C_L$ consists of parasitic capacitance and load capacitance [8]. The input pole induced by the Miller effect of the C-B or D-G parasitic capacitor can also influence the overall bandwidth. In addition to bandwidth, group delay $\tau$ is another important frequency-related indicator that can be derived from the phase-frequency characteristics $\phi \left(\omega \right)$ of a system:

$$\tau \left(\omega \right)=-{\displaystyle \frac{\mathrm{d}\phi \left(\omega \right)}{\mathrm{d}\omega }}$$

(3)

During circuit design of drivers, group delay should be carefully evaluated to prevent signal distortion.

The DC characteristics of CML drivers are measured by a voltage source and a multimeter. The AC performances, such as gain, bandwidth, and group delay, are characterized by S parameters measured by vector network analyzers. The transient waveform properties are characterized by an eye diagram plotted by oscilloscopes. Signal quality factors like eye height, eye width, jitter, and ratio of level mismatch (RLM) can be measured from the eye diagram.

2.2. Various Load Characteristics of CML Drivers

As high-speed CML drivers are used in optical transceivers, serializer–deserializer (SerDes), and other data transmitting systems, different load characteristics need to be considered, including the following aspects:

• Coupling: DC or AC. If the driver is directly coupled to the load, it is necessary to set the output DC operating point according to the load characteristics. Open-drain (OD) or open-collector (OC) structures can be adopted to place the terminating resistors at the far-end. If not, the circuit can be self-biased at a proper level. For optical transmitter applications, emerging silicon photonics (SiPh) technologies heterogeneously integrate photonic devices and electronic devices on the same substrate. As a consequence, the driver output can be directly coupled to the optical modulator without the need for DC block and packaging wires, which increases the integration, power efficiency, and signal quality.
• Wiring: single-ended or differential. If the load is single-ended, only one terminal is connected out, which is not conducive to the balance of current signals flowing across differential branches. Integrating a dummy load to another terminal is a feasible solution. An unbalanced CML structure can also be adopted to fit the DC point and AC performance with a specific load [9,10]. For CMOS technologies scaling down to 7 nm or below, differential connection is more essential given the limited voltage headroom below 0.8 V.
• Impedance matching. Regardless of the coupling and wiring method, it is crucial to maintain the continuity of the characteristic impedance on the signal transmission link. For a standard circuit system, the terminating resistor R is fixed to 50 $\mathsf{\Omega }$, and the output amplitude is determined by the tail current. But drivers used for optical modulators and other non-electrical devices have a non-standard load impedance. For load characteristic impedance higher than 50 $\mathsf{\Omega }$, the terminating resistor R can be set higher to match output load and lower tail current while maintaining the same output amplitude [11]. If the characteristic impedance is very low, on the other hand, the implementation of high-swing CML drivers is very power-consuming. Optimized structures such as push–pull CML can be adopted to improve the driving strength. The driver structures suitable for different load characteristics are described in Section 5.

2.3. Research Progress

Since the 1980s, a 100x increase in data rates has been witnessed [12]. Driven by advances in circuit topologies, packages, manufacturing processes, encoding, and modulation, the industrial signal baud rate evolves by doubling in approximately 6 years, as depicted in Figure 3. The feature size of CMOS technology has been scaled down to 2 nm [13]. High-order signal modulation technologies enable data transmission over long distances with lower bandwidth demand. For example, four-level pulse amplitude modulation (PAM4) has twice the data rate of non-return-to-zero (NRZ) signal at the same baud rate. Packages such as Co-packaged Optics (CPO), Wafer level Chip Scale Package (WLCSP), and Chiplet improve the connection density and data throughput among chips [14]. Circuit innovations are also required to address more issues brought by high data rates. Table 2 summarizes state-of-the-art CML drivers used for different applications from the following aspects:

• Technology. CMOS is the most common technology, where the feature size of MOSFET plays the major role in the cut-off frequency $f_T$. For SiGe HBT, GaAs pHEMT, and InP DHBT, $f_T$ is determined by many device properties aside from feature size. The breakdown voltage of the transistors limits the driver’s maximum swing.
• Data rate. Basically, the maximum achievable data rate is limited by the transistor’s cut-off frequency $f_T$, unless numerous bandwidth extension techniques are adopted, whereas PAM4 and PAM8 signal modulation reduce bandwidth demand with minimal increases in circuit complexity, thereby improving power efficiency (FoM).
• Output swing, power supply, and FoM. Generally, the higher the required signal amplitude, the greater the power supply and power consumption, and the more difficult it is to achieve high linearity. Typically, driver ICs in CMOS technology have better FoM because of the advantageous structures and low power supply.
• Application. For serial links, high data rate and power efficiency are the top priorities, so CMOS technologies are most commonly chosen. For EOMs such as MZM and MRM, the load characteristic impedance is not the standard 50 $\mathsf{\Omega }$, and high electrical amplitude is required to achieve high optical modulation amplitude (OMA), so SiGe BiCMOS, InP DHBT, and pHEMT technologies are more advantageous for their high $f_T$, $g_m$, and breakdown voltage. Especially, direct modulation lasers such as VCSEL and DFB are single-ended current-driven modulators, so the corresponding driver has a relatively low voltage swing and high power consumption.
• Architecture and technique. Some driver ICs only amplify the input signal, so their structures typically comprise VGA, EQ, PreAmp, and output driver. Some transmitter ICs incorporate additional functions such as multiplexing and PAM4 encoding, so their architectures include serializers. Most designs focus on innovations in equalization, bandwidth expansion, gain control, and termination strategies, resulting in improvements in equalizer tuning range, driver linearity, data rate, and power efficiency. Notably, equalizers have become essential in modern communication systems to extend the system-level channel capacity. Among the diverse equalizer architectures, CTLE and FFE are most commonly integrated in CML drivers and transmitters. Structured as a digital or analog high-pass finite impulse response (FIR) filter, FFE increases complexity, power, and area compared to CTLE, but it can be precisely tuned to counteract the loss of a known channel without amplifying noise.

Table 2. Summary of representative CML drivers for various applications.

Technology	Year	Data Rate & Modulation	Swing (${\mathit{V}}_{\mathit{pp}}$)	Power Supply (V)	FoM (pJ/bit)	Application	Architecture & Technical Highlights
65 nm CMOS	2020 [15]	112 Gb/s PAM4	0.72 (Dif.)	1.2	2.17	Serial link	Serializer + linearity-optimized driver with fractional-spaced FFE
40 nm CMOS	2025 [16]	96 Gb/s PAM8	1.6 (Dif.)	1.2 & 2.2	3.64	Serial link	Serializer + cascode driver with variable FFE
28 nm CMOS	2019 [17]	40 Gb/s PAM4	0.9 (Dif.)	0.9	0.5	Serial link	Serializer + SST-CML driver with 3-tap hybrid-path FFE
28 nm CMOS	2025 [18]	50 Gb/s PAM4	1.07 (Dif.)	1 & 1.1	1.45	Serial link	Serializer + two-type hybrid driver + pre-emphasis EQ
65 nm CMOS	2017 [19]	80 Gb/s PAM4	2 (Dif.)	2.5	2.25	EOMs	VGA + variable EQ + OD driver
150 nm 110 GHz GaAs pHEMT	2021 [20]	30 Gb/s PAM4	3	-5.2	40.9	Laser Diode	Two-slice CML driver with back-termination
65 nm CMOS	2024 [21]	32 Gb/s NRZ	$\sim 0.08$	/	12	DFB	CTLE + buffer + Output driver with active back-termination
65 nm CMOS	2023 [9]	25 Gb/s NRZ	0.4	2.2	0.83	VCSEL	Unbalanced CML driver
28 nm CMOS	2017 [22]	40 Gb/s NRZ	/	1 & −1.1	0.5	VCSEL	Tunable EQ + CML driver
14 nm CMOS	2017 [23]	42 Gb/s NRZ	0.6	/	1.94	VCSEL	Unbalanced driver + edge detector with differentiator
130 nm 250 GHz SiGe BiCMOS	2023 [24]	25 Gb/s NRZ	0.32	1.8 & 2.5 & 3.3	5.49	VCSEL	CML drivers with pre-equalization
130 nm 250 GHz SiGe BiCMOS	2016 [25]	40 Gb/s NRZ	2 (Dif.)	2.5	2.25	MRM	Cascaded drivers with current-density optimization
250 nm 220 GHz SiGe BiCMOS	2021 [26]	25 Gb/s NRZ	3 (Dif.)	2.5 & 4.5	13.16	MRM	Cascaded CML buffers
250 nm 190 GHz SiGe BiCMOS	2022 [27]	37 Gb/s NRZ	7.6 (Dif.)	6.4	39	MZM	CML OC driver with negative capacitor
180 nm 290 GHz SiGe BiCMOS	2024 [28]	4 × 112 Gb/s PAM4	3 (Dif.)	3.3	4.8	MZM	Active feedback CTLE + VGA + OC driver
55 nm 300 GHz SiGe BiCMOS	2017 [29]	168 Gb/s PAM8	3.8 (Dif.)	2.5 & 3.3 & 6	4.88	MZM	PreAmp + SSEFPP driver
90 nm 310 GHz SiGe BiCMOS	2024 [30]	80 Gb/s PAM4	3.2 (Dif.)	3.3 & 6.5	13.75	MZM	VGA + CTLE + SEFPP driver with asymmetric T-coil peaking
250 nm 400 GHz InP DHBT	2016 [31]	112 Gb/s PAM4	1.8 (Dif.)	5	7.5	MZM	VGA + distributed CML Bufs
500 nm 350 GHz InP DHBT	2025 [32]	200 Gb/s PAM4	4 (Dif.)	−5.2	4.3	EOMs	PreAmp + OC driver with R-C base ballast

DHBT: Double Hetero-junction Bipolar Transistor; pHEMT: pseudomorphic High Electron Mobility Transistor; VCSEL: Vertical Cavity Surface Emitting Laser; BiCMOS: Bipolar CMOS; MRM: Micro-Ring Modulator; MZM: Mach–Zehnder Modulator; DFB: Distributed Feedback Laser; VGA: Variable Gain Amplifier; SST: Source-Series Terminated; CTLE: Continuous Time Linear Equalizer; FFE: Feed Forward Equalizer; EQ: Equalizer; OD: Open drain; OC: Open collector; PreAmp: pre-amplifier; SEFPP: single emitter follower push–pull; SSEFPP: Series-stacked EF push–pull; EOM: Electro-optic modulator; Dif: Differential; Figure of Merit (FoM) = Power/Data-Rate.

Table 2. Summary of representative CML drivers for various applications.

Technology	Year	Data Rate & Modulation	Swing (${\mathit{V}}_{\mathit{pp}}$)	Power Supply (V)	FoM (pJ/bit)	Application	Architecture & Technical Highlights
65 nm CMOS	2020 [15]	112 Gb/s PAM4	0.72 (Dif.)	1.2	2.17	Serial link	Serializer + linearity-optimized driver with fractional-spaced FFE
40 nm CMOS	2025 [16]	96 Gb/s PAM8	1.6 (Dif.)	1.2 & 2.2	3.64	Serial link	Serializer + cascode driver with variable FFE
28 nm CMOS	2019 [17]	40 Gb/s PAM4	0.9 (Dif.)	0.9	0.5	Serial link	Serializer + SST-CML driver with 3-tap hybrid-path FFE
28 nm CMOS	2025 [18]	50 Gb/s PAM4	1.07 (Dif.)	1 & 1.1	1.45	Serial link	Serializer + two-type hybrid driver + pre-emphasis EQ
65 nm CMOS	2017 [19]	80 Gb/s PAM4	2 (Dif.)	2.5	2.25	EOMs	VGA + variable EQ + OD driver
150 nm 110 GHz GaAs pHEMT	2021 [20]	30 Gb/s PAM4	3	-5.2	40.9	Laser Diode	Two-slice CML driver with back-termination
65 nm CMOS	2024 [21]	32 Gb/s NRZ	$\sim 0.08$	/	12	DFB	CTLE + buffer + Output driver with active back-termination
65 nm CMOS	2023 [9]	25 Gb/s NRZ	0.4	2.2	0.83	VCSEL	Unbalanced CML driver
28 nm CMOS	2017 [22]	40 Gb/s NRZ	/	1 & −1.1	0.5	VCSEL	Tunable EQ + CML driver
14 nm CMOS	2017 [23]	42 Gb/s NRZ	0.6	/	1.94	VCSEL	Unbalanced driver + edge detector with differentiator
130 nm 250 GHz SiGe BiCMOS	2023 [24]	25 Gb/s NRZ	0.32	1.8 & 2.5 & 3.3	5.49	VCSEL	CML drivers with pre-equalization
130 nm 250 GHz SiGe BiCMOS	2016 [25]	40 Gb/s NRZ	2 (Dif.)	2.5	2.25	MRM	Cascaded drivers with current-density optimization
250 nm 220 GHz SiGe BiCMOS	2021 [26]	25 Gb/s NRZ	3 (Dif.)	2.5 & 4.5	13.16	MRM	Cascaded CML buffers
250 nm 190 GHz SiGe BiCMOS	2022 [27]	37 Gb/s NRZ	7.6 (Dif.)	6.4	39	MZM	CML OC driver with negative capacitor
180 nm 290 GHz SiGe BiCMOS	2024 [28]	4 × 112 Gb/s PAM4	3 (Dif.)	3.3	4.8	MZM	Active feedback CTLE + VGA + OC driver
55 nm 300 GHz SiGe BiCMOS	2017 [29]	168 Gb/s PAM8	3.8 (Dif.)	2.5 & 3.3 & 6	4.88	MZM	PreAmp + SSEFPP driver
90 nm 310 GHz SiGe BiCMOS	2024 [30]	80 Gb/s PAM4	3.2 (Dif.)	3.3 & 6.5	13.75	MZM	VGA + CTLE + SEFPP driver with asymmetric T-coil peaking
250 nm 400 GHz InP DHBT	2016 [31]	112 Gb/s PAM4	1.8 (Dif.)	5	7.5	MZM	VGA + distributed CML Bufs
500 nm 350 GHz InP DHBT	2025 [32]	200 Gb/s PAM4	4 (Dif.)	−5.2	4.3	EOMs	PreAmp + OC driver with R-C base ballast

DHBT: Double Hetero-junction Bipolar Transistor; pHEMT: pseudomorphic High Electron Mobility Transistor; VCSEL: Vertical Cavity Surface Emitting Laser; BiCMOS: Bipolar CMOS; MRM: Micro-Ring Modulator; MZM: Mach–Zehnder Modulator; DFB: Distributed Feedback Laser; VGA: Variable Gain Amplifier; SST: Source-Series Terminated; CTLE: Continuous Time Linear Equalizer; FFE: Feed Forward Equalizer; EQ: Equalizer; OD: Open drain; OC: Open collector; PreAmp: pre-amplifier; SEFPP: single emitter follower push–pull; SSEFPP: Series-stacked EF push–pull; EOM: Electro-optic modulator; Dif: Differential; Figure of Merit (FoM) = Power/Data-Rate.

Figure 3. The evolution of serial communication rate.

Figure 3. The evolution of serial communication rate.

3. Bandwidth Expansion Techniques

3.1. Shunt Inductive and T-Coil Peaking Technique

The CML circuit with shunt inductive peaking technique employed is depicted in Figure 4a. Load inductors expand the bandwidth by introducing a zero $L/2\pi R$ at high frequency, as shown in Equation (4). It partly compensates for the pole of load capacitor. As for the design of the inductor, the line width, Q factor, and area occupation need to be balanced to ensure the performance and reliability. Sometimes, active inductors can take the place of passive inductors to save area at the expense of supply voltage margin. Its equivalent inductance is $L\approx R_f{C}_p/g_{m1}$ [33].

$$H\left(s\right)=G_m{Z}_{out}=g_m\left({\displaystyle \frac{1}{s{C}_L}}\right)\left|\right|(R+sL)={\displaystyle \frac{g_m\left(R+sL\right)}{L{C}_L{s}^2+R{C}_{L}s+1}}$$

(4)

T-coil is another inductor-based method to further compensate for the influence of load capacitance, as shown in Figure 4b. According to [34], its transfer function has four poles and two zeros that are related to $L_1$, $L_2$, and $C_L$. By properly selecting the inductors’ values, two poles and two zeros can be canceled. The optimal bandwidth of the T-coil-based driver is commonly better than that of the shunt-inductive-based driver. But excessive peaking inductance may cause signal overshoot and deteriorate eye diagram opening, which needs to be designed according to actual chip and channel conditions [35].

3.2. Capacitor and Resistor Degeneration Technique

Capacitors and resistors can also be used for expanding the bandwidth. As shown in Figure 5a, a capacitor and a resistor separate the tail current of the differential pair into two branches. This configuration is also referred to as CTLE. The negative feedback yields a zero and two poles in the transfer function Equation (5), which improves linearity and bandwidth at a slight cost of low-frequency gain.

$$\begin{array}{c}H\left(s\right)={\displaystyle \frac{g_m\left(R_L\left|\right|\frac{1}{s{C}_L}\right)}{1+g_m\left(R_s\left|\right|\frac{1}{s{C}_s}\right)/2}}\\ ={\displaystyle \frac{g_m{R}_L}{1+g_m{R}_s/2}}{\displaystyle \frac{1+s{R}_s{C}_s}{(1+s{R}_L{C}_L)\left[1+s{R}_s{C}_s/\left(1+g_m{R}_s/2\right)\right]}}\end{array}$$

(5)

The low-frequency gain is approximately $2R/R_s$ given the negative feedback. In practical design, varactors and MOS linear resistors are usually selected as degeneration resistors and capacitors to make gain and bandwidth adjustable in practical applications, as shown in the dashed box of Figure 5a [36]. Resistor and capacitor array with MOS switches is another scheme used to digitally trim the resistance and capacitance [37,38]. Its typical effect on AC response of the differential pair is shown in Figure 5b, where the resistance mainly affects the low-frequency gain and the capacitance primarily influences the high-frequency peaking. During layout design, both ends of the capacitor and resistor should be regarded as high-speed nodes, and unwanted parasitic capacitance should be avoided as much as possible.

3.3. Negative Capacitor Technique

Input capacitance can be lowered by a negative Miller capacitor. As shown in Figure 6, each Miller capacitor is connected across one input and the other output of the differential pair. According to the Miller effect, the equivalent input capacitance can be expressed as

$$C_{c,in}=C_c(1-g_m{R}_L)$$

(6)

The equivalent input parasitic capacitance of the original differential pair is

$$C_{p,in}=C_x+C_y(1+g_m{R}_L)$$

(7)

Thus, the total input capacitance is

$$C_{in}=C_{c,in}+C_{p,in}=C_c(1-g_m{R}_L)+C_y(1+g_m{R}_L)+C_x$$

(8)

By selecting an appropriate $C_c$ capacitance to make it equal to $C_y$, total input capacitance can be reduced to

$$C_{in}=2C_y+C_x$$

(9)

The key to fully leveraging this technique lies in comprehensive simulation to guarantee consistency among circuit design, layout, and manufacturing implementation. Moreover, the positive output Miller capacitor introduced by $C_c$ causes the output pole to shift forward, which requires balancing overall bandwidth during system design. Output capacitance can be lowered by negative capacitor circuit consisting of cross-coupled transistors with a degeneration capacitor, as shown in the dashed box of Figure 6. As $|s{C}_x^{\prime }|$ is much smaller than $g_m^{\prime }$, the impedance looking into this circuit can be simplified as follows:

$$Z_{nc}=-{\displaystyle \frac{1}{s{C}_n}}{\displaystyle \frac{g_m^{\prime }+s(C_x^{\prime }+2C_n)}{g_m^{\prime }-s{C}_x^{\prime }}}\approx -{\displaystyle \frac{1}{s{C}_n}}-\left({\displaystyle \frac{C_x^{\prime }}{C_n}}+2\right){\displaystyle \frac{1}{g_m^{\prime }}}$$

(10)

The negative capacitor and resistor create a zero (${\omega }_{\mathrm{z}}=1/C_n\left(C_x^{\prime }/C_n+2\right)/g_m^{\prime }$) in the transfer function, which improves the gain and bandwidth [39,40,41].

3.4. $f_T$ Doubling Technique

The $f_T$ doubling technique is another technique used to lower input capacitance [37,40]. As shown in Figure 7a, the differential signals are fed into two differential pairs with parallel output. The other side of each differential pair is fed with common-mode bias voltage. Its gain is identical to a single differential pair as the transistors’ size and load resistance are the same, whereas its input capacitance halves, as depicted in Figure 7b. This phenomenon is similar to doubling the transition frequency $f_T$ of transistors. However, this structure doubles the power and increases the parasitic capacitance from the tail current nodes and output nodes, which may worsen the actual performance. Thus, it is vital to plan the layout rationally to minimize parasitic capacitance.

The above bandwidth expansion techniques are compared in

Table 3. Comparison of the bandwidth expansion techniques.

Techniques	Simplicity	Bandwidth Improvement	Additional Power	Area Cost	Challenges
Shunt inductive & T-coil peaking	+++	∼1.8×, 2.8×	-	+++	Inductor SRF; Consistency between simulation and measurement
Capacitor and resistor degeneration	+++	vary by R, C	-	+	Lowered gain
Cross-coupled negative capacitor	+	∼1.3×	✓	++	Capacitor value selection; layout symmetry
Negative Miller capacitor	++	∼1.3×	-	+	Capacitor value selection; layout symmetry
$f_T$ doubling	+	∼2×	✓	++	Higher output capacitance; layout symmetry

+: low; ++: moderate; +++: high; -: not required; ✓: required

. The voltage headroom of these techniques is largely associated with the adopted driver architecture. The techniques are usually employed in combination to adapt to different loads and channel characteristics, especially for communication links above 80 GBaud. But increasing the high-frequency peak is not always beneficial given the group-delay flatness and other stability issues, which need to be considered and optimized during electromagnetic simulations. For example, the maximum group delay variation should be limited to a 0.2 unit interval (UI) within the bandwidth for VCSEL transmitters [42], and the self-resonant frequency (SRF) of inductors and capacitors should be designed far beyond the signal bandwidth in case of oscillation.

4. Amplitude and DC Level Adjustment Techniques

Apart from bandwidth, gain and output level are other important driver performance indicators that need to be adjustable in applications such as automatic test equipment (ATE). As $V_{out}=VCC-I_{s}R$, $A_v=g_m{R}_{out}$, $g_{m,MOS}\propto \sqrt{I_s}$, and $g_{m,HBT}\propto I_s$, gain adjustment mainly focuses on changing tail current, transconductance, and output resistance. As mentioned earlier, the gain can be roughly adjusted by degeneration resistor or enhanced by negative resistor. More accurate and flexible adjustments can be realized with the following methods.

4.1. Manual Control

4.1.1. Basic Ideas

As the output signal levels are defined by output DC point, input amplitude, and gain of the amplifier, output level adjustment techniques mainly focus on changing these parameters. The input amplitude and DC level are determined by amplifier from prior stages. The output DC level is mainly determined by the tail current and termination resistor R. With regard to the output stage, R is fixed at 50 $\mathsf{\Omega }$ for impedance matching. Tail current can be adjusted by MOS switches S<n> in an array of MOS current mirrors, the reference current, or a DAC controlling the gate voltage of the MOS current array, which are the most effective digital and analog methods to control the output DC level (and gain). However, changing output DC level on a large scale may push the amplifying transistors into an unwanted operating region, which requires synchronous change of transistor size and input DC level, as shown in Figure 8. Furthermore, the sensitive analog signal transmission from DAC to the gate of MOS current array needs additional shielding like filter capacitors to prevent noise crosstalk, and the resolution and output range of the DAC need to be carefully decided as the variation of tail current with MOS gate voltage follows a square law relationship.

4.1.2. Cross-Coupled Pair Arrays

A CML circuit with cross-coupled pairs can be used for gain adjustment, which is always referred to as VGA. It can be structured as a thermometric array in Figure 9 [43], where only one of the cross-coupled differential pairs in each element is turned on. It can also be structured as a Gilbert cell, as shown in Figure 10. Their basic principles are both to divide input signal into two paths with different current intensities and superpose them inversely at the output node; thus, the output amplitude is relevant to the gain difference of two paths. For the thermometric array, if k and M, respectively, denote the number of turned-on cells and total cells in a half path, the total gain is given by

$$A_{tot}=(2k-M)R\sqrt{k_n^{\prime }{\displaystyle \frac{W}{L}}{I}_s}$$

(11)

where W, L, and $k_n^{\prime }$ are the width, length, and technology-related parameters of the transistors, respectively.

4.1.3. Gilbert Cell

Compared to the digital-controlled thermometric array, the Gilbert-cell-based VGA is a continuous-controlled analog solution that does not need large array layout with relatively high input and output parasitic capacitance. To further lower the output capacitance, some designs connect the half output path of the cross-coupled pair directly to power supply (see Figure 10a [40,44,45]). The disadvantages of these structures are that they require relatively high power supply to support desired operating region of the stacked transistors. Non-uniform gain modification and signal distortion may occur at the upper and lower limits of the control voltage because of the operating region change of the common-base transistors. Some VGA designs combine Gilbert cell and cross-coupled array, which make use of the advantages of both structures to realize a more flexible and linear gain adjustment range [36]. In the Gilbert cell, the signal can be input from the common-emitter transistors (Figure 10b) or the cross-coupled pair (Figure 10c). The latter has lower input capacitance and better reverse isolation. Its principle is derived in Appendix A, which demonstrates that the gain of VGA can be controlled by the difference between $V_{ctrlp}$ and $V_{ctrln}$.

4.2. Automatic Control Loop

4.2.1. Automatic Gain Control (AGC)

For many applications like optical receivers, output amplitude is supposed to be stable automatically irrespective of input amplitude changes, which can be realized by VGAs with a feedback mechanism. As shown in Figure 11a, a typical AGC loop consists of a peak detector to extract the output peak amplitude as a voltage signal, a difference amplifier to generate VGA gain control signal by comparing the voltage signal with a reference voltage, and a filter capacitor to stabilize the control signal. An exponential function generator can be integrated to realize linear control of VGA gain. The loop model can be abstracted in Figure 11b [40], and the loop gain is given by

$$L.G.=-{\displaystyle \frac{d{V}_1}{d{V}_c}}{A}_v{k}_{p}F\left(s\right)=-k_{p}F\left(s\right)V_o^0{\displaystyle \frac{1}{G\left(V_c\right)}}{\displaystyle \frac{\mathrm{d}G\left(V_c\right)}{\mathrm{d}{V}_c}}$$

(12)

where $F\left(s\right)$ is the loop filter transfer function, $G\left(V_c\right)$ is the VGA gain, and $V_o^0$ denotes a constant peak-to-peak voltage set at the output of the AGC circuit by the external reference voltage $V_{ref}$. The derived settling time of the control loop is

$$\tau ={\displaystyle \frac{C}{k_2{G}_m{V}_{ref}}}$$

(13)

where $G_m$ is the transconductance of the difference amplifier, and $k_2$ indicates the dB-linear gain control slope of the exponential function generator. The main concern of the AGC is that the loop gain should remain stable and the lower cut-off frequency $\sim 1/\tau$ of the high-pass settling time function should be smaller than the lowest operating frequency. To this end, the parameters C, $G_m$, and $k_2$ should be precisely balanced.

4.2.2. DC Offset Cancellation

For cascaded CML drivers constituting LA, mismatch voltage from input transistors could be amplified and bring about tens of millivolts of DC offset at the output. A single DC offset cancellation (DCOC) loop or multiple loops should be adopted to balance differential output DC points. As shown in Figure 12, it is constructed of an RF low-pass filter to extract the center level of signals and a $g_m$ cell to compensate for input DC offset [33,37]. With the negative feedback, in theory, the output offset voltage $V_{os}$ can be reduced to $V_{os}/(1+A{A}_1)$. Given the large RC parameters to make the loop bandwidth far below the lowest frequency content of the input signal, some designs leverage MOS resistors and capacitors or Miller capacitive multiplication with the error amplifier to reduce this filter area [46].

5. CML Variants for Different Applications

5.1. CML Circuits for High-Order Modulation Signal Combination

For the generation of differential high-order modulation signals like PAM4 and PAM8, original MSB and LSB data are combined into multi-amplitude modulation signals by a cascaded CML circuit [16]. Taking the PAM4 combiner in Figure 13 as an example, the switch states of two differential input signals form four output levels like a DAC. The ideal tail current ratio of 2:1 between MSB and LSB branches results in three uniformly distributed eyes in the eye diagram. In practical conditions, non-ideal transistor characteristics like channel length modulation effect deteriorate linearity (RLM). Furthermore, the load characteristics of some optical modulators are not simple resistors/capacitors. The electro-optic conversion curve is non-linear, such as MRM [47]; therefore, the tail current ratio needs to be adjustable to pre-distort the eyes with exactly the opposite non-linearity. Auxiliary adjustable FFE or calibration circuits can be employed jointly with main drivers to superpose a signal that precisely compensates for non-ideal characteristics on the output [15,48]. For PAM8 and higher-order modulation, the basic circuit approach is to wire more differential pairs in parallel to generate multi-level output. The higher the modulation order, the lower the required system bandwidth; yet, the encoding, driving, receiving, data recovery, and decoding schemes in the transceiver become far more complex. Also, such a system is more sensitive to noise, linearity, and crosstalk. Consequently, the evolution of modulation has to trade off system complexity, cost, technical feasibility, and power efficiency together.

5.2. Open-Drain (Open-Collector) Driver

OD/OC and push–pull are common topologies used for digital IO interfaces. With regard to CML drivers, OD/OC structures can be used in direct coupled modulators, which place the terminating resistors at the far end of the load, as shown in Figure 14 [27]. As the entire tail current of the driver flows through the load, only half of the tail current and power consumption are required at the same output swing condition, which is more power efficient than back termination topologies. But the impedance of the driver and transmission lines should be carefully designed to match the load characteristic impedance, and the current density through the load should be considered [28].

5.3. Push–Pull CML Driver

The push–pull amplifier is another topology used to save power and improve the driving capability. The CMOS push–pull driver provides tail currents at both the power and ground sides, as shown in Figure 15a. $V_{cm}$ defines the output signal center level, and $R_L$ together with tail current determine the output swing [49,50]. Compared to the voltage-mode (VM) push–pull driver, it has better differential symmetry. As for bipolar technologies, because PNP transistors are not suitable for high-speed drivers, NPN transistors are used for both push-up and pull-down networks, as shown in Figure 15b. The push–pull CML structures listed in Table 2 are derived from switched emitter follower (SEF) topology [29]. A cascode CML PreAmp is required to supply EF transistors with proper DC voltage and AC swing. Peaking inductors can be employed to broaden the bandwidth. The current signals driven by cascode transistors and EF transistors are summed at the output node. The transmission delays of the two paths should be matched, otherwise the gain may degrade [30]. Optimized push–pull structures such as SSEFPP provide high swing to drive low-impedance loads such as MZMs without compromising linearity and power efficiency.

5.4. Stacked and Unstacked Tailless CML Driver

For single-ended PAM4 signaling, tailless CML is a more power-efficient structure as it eliminates tail current and reduces static power. As shown in Figure 16, the four PAM4 levels are generated by adding the currents of the MSB or LSB branch to the terminating resistor, similar to a current-steering DAC. The MSB branch provides twice the current of that in the LSB branch [51,52]. Compared to the stacked CML driver (Figure 16a), the unstacked CML driver (Figure 16b) uses one transistor in each branch to achieve both switch and current source functions, which is more compact in size and suitable for <7 nm FinFET technologies with even lower power supply margin. But it supports a smaller output swing tuning range and suffers from impedance mismatch when the switching transistors are turned on. Some studies proposed a hybrid structure [53] and a trimmable termination resistor scheme [54] as solutions. Typically, the N-type CML driver has better bandwidth as NFET has better $g_m$ and $f_T$ than PFET (Figure 16c). Compared to the CML differential pair, it is more suitable for digital interface applications such as double data rate (DDR) memory.

5.5. CML-SST Hybrid Driver

CML circuits support high-swing applications but lack linearity and power efficiency. SST drivers feature better power efficiency and linearity but have difficulties in increasing output swing, minimizing parasitic capacitance in the output node, and impedance matching. In order to combine the advantages of CML and SST structures, SST-CML-Hybrid (SCH) structures have become recent research highlights [17,55,56]. Figure 17a shows the basic structure of the PAM4 SCH circuit, and its working principle is depicted in Figure 17b–e. Without current sources, the voltage-mode inverters realize the output amplitude of $3V_{DD}/4-V_{DD}/4=V_{DD}/2$ with a uniform eye height of $V_{DD}/6$. Combining the CML drivers, the output swing is expanded to $V_{DD}/2+(I_L+I_M)R_T$. To obtain a uniform PAM4 eye diagram, the output levels satisfy

$$(I_L+I_M)R_T/2-(I_M-I_L)R_T/2=(I_M-I_L)R_T$$

(14)

Thus, the relation of the tail currents is $I_M=2I_L$. The structure has the potential of generating output swings larger than $V_{DD}$ through proper design of the tail currents, thereby improving the driving strength and power efficiency under a limited power supply in <14 nm FinFET technologies.

The advantages of different structures are compared in

Table 4. Comparison of CML structures.

Structure	Simplicity	Power Efficiency	Output Swing	Matching Methods	Preferred Applications
(Cascode) differential pair	+++	+	+++	Internal resistors	Widely applicable
OC/OD	+++	++	+++	External resistors	Need external termination
Push–pull	++	++	++	Parallel transistors	Low load resistance
Tailless	++	+++	+	Internal resistors	In CMOS technology, low power supply
CML-SST hybrid	+	+++	+	Internal series resistors + parallel transistors	In CMOS technology

+: low; ++: moderate; +++: high

based on previous studies. In general, tailless topologies exhibit better power efficiency relative to conventional constant-tail-current architectures. The maximum swing is limited by the power supply and breakdown voltages of HBTs and MOSFETs, and internal resistor terminating is a simple and accurate impedance matching method among the output driver terminating methods.

6. Key Design Considerations for High-Speed High-Swing CML Circuits

6.1. General Design Rules

• The DC current and voltage of transistors in the high-speed path should be biased at peak $f_T$ based on device models. Technology non-ideal characteristics and reliability issues should be considered during layout and post simulation according to technology design guidelines, such as latch-up, hot carrier degradation, and MOSFET well proximity effect.
• Differential high-speed interconnects should be as short and symmetrical as possible, and isolated from other low-speed modules. During parasitics extraction, parasitic inductance should be extracted and simulated more accurately by electromagnetic tools such as ADS and EMX in addition to RC extraction tools such as xRC, qRC, and StarRC.
• The resistance of on-die power grids and package-level interconnects causes a localized reduction in the effective $V_{DD}$ seen by internal circuits, which is an increasingly severe issue with the relentless scaling of CMOS processes to 7 nm and below. Advanced chip fabrication technologies such as backside power delivery network effectively improve localized power delivery [57], but they require co-design of crosstalk reduction, thermal management, and mechanical stress protection. For chip-level design, power supply and ground wires can be meshed with multiple metal layers to reduce wiring resistance and increase filtering capacitance through power-ground parasitics. Electromigration and IR-drop (EMIR) simulations should be conducted to ensure power integrity.

6.2. Cascode Structure for High-Swing Drivers

The cascode structure is often adopted in CML drivers, as shown in Figure 18. In the cascode current mirror, $V_{gs3}\approx V_{gs4}$ and $V_{ds1}\approx V_{ds2}$, the influence of channel modulation effect on current replication accuracy is suppressed. Also, it has high output impedance, $r_{ds2}{g}_{m4}{r}_{ds4}$, which enhances the stability of the tail current [25]. A cascode or series-stacked amplifier can prevent transistors from breakdown in high-power-supply high-swing drivers, and reduce output parasitic capacitor by suppressing the Miller effect of input transistors [39,58]. However, parasitic inductance from bias and power wiring needs to be taken into account in high-speed or high-frequency circuits. According to the small signal model of the half cascode amplifier, if we ignore $C_{gd}$ and abstract M6 as an RC parallel network, the impedance looking into the gate of M7 and M8 is

$$Z_{in}={\displaystyle \frac{1}{j\omega C_{gs}}}+{\displaystyle \frac{R_6}{j\omega R_6{C}_6+1}}\left(1+g_m{\displaystyle \frac{1}{j\omega C_{gs}}}\right)$$

(15)

The real part is given by the following:

$$R_{in}\cong {\displaystyle \frac{R_6}{{\left(\omega R_6{C}_6\right)}^2+1}}-{\displaystyle \frac{g_m{\left(\omega R_6\right)}^2{C}_6{C}_{gs}}{{\left({\omega }^2{R}_6{C}_6{C}_{gs}\right)}^2+{\left(\omega C_{gs}\right)}^2}}$$

(16)

The input resistance could be negative in some conditions. Long wiring of bias voltage introduces a parasitic inductance $L_p$ at the gate of M7/M8 and forms a Colpitts oscillator [59]. Especially, biasing at high tail current for high-swing applications accounts for high $g_m$ and increases the possibility of negative impedance. A feasible solution is to connect a small resistor $R_t$ in series with the M7/M8 gate and a decoupling capacitor $C_t$ in parallel to reduce the reflection coefficient looking out of the M7/M8 gate without changing the operating point significantly [45,60,61,62,63].

6.3. Input and Output Interface

As signal integrity is a critical consideration in high-speed systems, the chip package model needs to be integrated at every stage of circuit simulation. The parasitic inductance induced by long bonding wires and interconnects is beneficial to bandwidth boosting. However, for drivers operating above 50 Gbaud, this inductance, along with parasitic capacitance, overwhelmingly acts as a limiting factor that deteriorates the total system bandwidth and introduces severe signal reflections. Certain circuits such as CTLE or FFE with proper bandwidth-compensation coefficients need to be integrated to adapt to practical channel characteristics. Advanced packages such as WLCSP and CPO shorten the electrical connection between ICs, which dramatically reduces parasitic inductance from hundreds of picohenries to around ten picohenries. The load seen by the driver shifts from distributed transmission lines to an almost purely lumped capacitive load, which eases the compensation of equalizers. But the chip power efficiency needs to be taken into account, as these complex packages increase thermal density and are not conducive to chip heat dissipation and peripheral thermal-sensitive devices. For SiPh transmitters [27], especially distributed modulator drivers [64], the output transmission lines’ geometry needs to be specially designed to match the propagation delays in the optical and electrical paths. Moreover, ESD devices in high-speed I/O interfaces increasingly affect link bandwidth, which requires the T-coil bandwidth-compensation technique [65]. End-to-end impedance matching should be thoroughly evaluated through return loss or time domain reflectometry (TDR) simulations.

7. Conclusions and Future Outlook

This review summarizes CML circuits for wireline transceivers, optical modulators, and other data transmitting systems. Basic principles and performance indicators are described and derived. Their performance advancements in recent years are summarized. Common technical principles to enhance bandwidth, improve linearity, and adjust amplitude are discussed, derived, and compared for high-speed applications. Emerging structures for better power efficiency, driving strength, and simplification are introduced. Design considerations to avoid unexpected failures in high-frequency circuits are mentioned. The review covers theoretical basis, cutting-edge progress, and various design techniques of CML circuits for transceivers and optical communication systems.

Although SST drivers and other structures have been favored in continuously scaling CMOS technologies, CML circuits still play an important role in high-swing differential applications, especially for SiGe and InP technologies. As the minimum transistor size and interconnection bandwidth have their physical limitations, more innovations will be focused on packages with high integration density and multi-lane optical solutions. More complex modulation formats will be widely applied to release bandwidth requirements. CML circuits are expected to be designed with better linearity and power efficiency. It is essential to combine the experience and techniques in digital, analog, and RF circuit design, while thoroughly leveraging the advantages of processes and packaging, to achieve driver circuit innovation and performance breakthroughs.