System Design for On-Board Multi-Mission Compatibility of Spaceborne SAR

Abstract

To meet the real-time, multi-task processing demands of spaceborne synthetic aperture radar (SAR) systems under limited onboard resources, this paper presents a configurable field-programmable gate array (FPGA) architecture that supports both water body and oil spill detection. First, an efficient computing engine partitioning method at coarse and fine granularities is proposed. The operations of the water body and oil spill detection algorithms are clustered and analyzed at two levels, and both general-purpose and specialized computing engines are designed to minimize resource usage. Second, a high-reuse storage optimization strategy is introduced. Based on the data buffering cycle, a shared on-chip memory is designed to minimize storage resource consumption. Building upon these foundations, a software and hardware co-programmable efficient processing system is developed, successfully mapping both detection algorithms onto the FPGA. Finally, the effectiveness of the proposed architecture is confirmed through experimentation, and processing performance is analyzed. Processing times for a 16K × 16K water body scene and a 16K × 16K oil spill scene are 15 s and 13 s, respectively, at a clock frequency of 100 MHz, meeting the real-time multi-task processing requirements of on-board operations.

1. Introduction

Spaceborne Synthetic Aperture Radar (SAR) features all-time, all-weather, and high-resolution capabilities, making it an important tool for surface monitoring, especially playing a significant role in disaster monitoring. To meet the urgent demand for high timeliness in flood disasters and oil spill accidents, it is necessary to quickly complete water area and oil spill detection tasks on-board to achieve timely acquisition of key information. In on-board SAR processing systems, FPGA (Field-Programmable Gate Array), ASIC (Application Specific Integrated Circuit), and DSP (Digital Signal Processor) can be used as core processors. Among them, FPGA, with its rich parallel computing resources, high efficiency, and reconfigurability, has shown significant advantages in rapid algorithm deployment and iterative updates, and thus it is widely adopted and applied [1]. However, the radiation-hardened FPGAs suitable for on-board applications have very limited computing and storage resources, making it impossible to implement both water area and oil spill detection tasks in a single FPGA, thus requiring multiple FPGAs. With the future development of satellites moving towards miniaturization and low cost [2,3], satellite power consumption and cost are strictly constrained. Therefore, this paper focuses on researching the implementation of both water area and oil spill detection tasks in a single radiation-hardened FPGA, which cannot only meet the multi-task requirements of disaster monitoring but also reduce on-board overhead.

Currently, several studies have explored the implementation of water area or oil spill detection algorithms on FPGA platforms. For water area detection algorithms, Refs. [4,5] successfully implemented simple land–water segmentation algorithms on Xilinx FPGAs, and Refs. [6,7] successfully mapped water area extraction algorithms to Xilinx FPGA platforms. Ref. [8] implemented a land–water segmentation algorithm using empirical parameters for iterative calculation of adaptive thresholds on an FPGA and DSP heterogeneous system. Ref. [9] proposed a parallel iterative computing structure design method that balances computing efficiency and on-chip cache, successfully implementing a multi-threshold hierarchical sea–land segmentation algorithm in Xilinx Zynq FPGA. Ref. [10] proposed a multi-dimensional parallel high-throughput hardware architecture, which implemented the multi-threshold hierarchical sea–land segmentation algorithm on Xilinx Zynq FPGA. Ref. [11] utilized the data parallel processing characteristics of an FPGA, proposed a hardware mapping method for a water area detection algorithm based on Sobel edge detection, and successfully deployed it on the Xilinx Zynq 7020 FPGA development board. For oil spill detection algorithms, Refs. [12,13,14] proposed oil spill detection algorithms suitable for deployment on embedded platforms. Ref. [15] proposed a multi-level oil spill detection algorithm combining gray features and edge features, which was successfully deployed on an Xilinx Zynq 7020 FPGA development board. Ref. [16] proposed a low-complexity artificial neural network-based oil spill detection method, which was successfully deployed on Xilinx Zynq-7020 FPGA through a fully parallel mapping scheme. Although the above references have realized the mapping of water area or oil spill detection algorithms through parallel processing, they occupy high computing and storage resources, making them unsuitable for radiation-hardened FPGAs with limited resources.

Therefore, aiming at the real-time processing requirements under on-board resource constraints, this paper proposes a hardware–software co-programmable efficient processing system. To reduce the occupation of computing resources, through analyzing the operation steps of water area and oil spill detection algorithms, an efficient general computing engine partitioning method based on coarse and fine granularity is designed. In addition, to optimize the consumption of storage resources, a shared on-chip memory is designed. Experimental verification shows that under a 100 MHz clock frequency, the processing time is 15 s for 16K × 16K water area scene images and 13 s for 16K × 16K oil spill scene images, meeting the on-board real-time requirements.

2. On-Board Detection Algorithms

2.1. Water Area Detection Algorithm

The water area detection algorithm analyzes and processes the features of water area targets, extracts key information of water area targets, and realizes water area observation and disaster early warning. The water area detection algorithm adopted in this paper [11] is shown in Figure 1. After preprocessing, the input image first uses the texture features of large-scale image blocks to extract water area candidate regions, then uses the texture features of small-scale image blocks to achieve fine-water area extraction, and finally obtains the final detection result through false alarm elimination based on target-connected domain features and gray mean features. The algorithm mainly consists of four parts, and the function breakdown of each part is shown in

Table 1. Overview Table of water body detection algorithm functions.

Serial Number	Step Name	Processing Functions
1	Data Preprocessing	4 × 4 mean filtering, zero-value padding
2	Block-Level Texture Feature Extraction	32 × 32 block texture feature extraction, 4096 × 4096 regional grayscale feature extraction, 4096 × 4096 rough water area segmentation, correction of rough segmentation results
3	Fine-Water Area Extraction	Fine extraction, 7 × 7 dilation and 7 × 7 erosion
4	False Alarm Elimination	Connected domain false alarm elimination, secondary false alarm elimination, tertiary false alarm elimination

.

• Data Preprocessing

According to the characteristics of water area images, 4 × 4 mean filtering with a small-scale window is used to remove large noise points. After that, the filtered data is segmented into fixed sizes. For an input image with dimensions of 16,384 × 16,384, the fixed patch size was set to 4096 × 4096, and insufficient data is padded with zeros.

2.

Block-Level Texture Feature Extraction

For the filtered image data of SAR images, 32 × 32 block texture extraction is performed. Based on the block textures, an integral image is calculated, which is then used for rough segmentation of water areas. The results of the rough water area segmentation are further corrected using texture information. Specifically, the 32 × 32 block texture feature extraction function includes the calculation of block mean and variance features; the 4096 × 4096 regional grayscale feature extraction function includes the calculation of regional mean and variance features. The expression for integral image calculation is as follows, where $I(x_0,y_0)$ represents the pixel value in the original image. For large-scale block-level texture feature extraction, it is mainly used to quickly extract water area candidate regions, while the extraction of small-scale block-level texture features is mainly used for fine-water area extraction:

$$SAT(x,y)={\displaystyle \sum _{x_0=1}^x{\displaystyle \sum _{y_0=1}^{y}I(x_0,y_0)}}$$

(1)

3.

Fine-Water Area Extraction

Guided by large-scale water area candidate regions, areas are classified as water based on texture information, distinguishing water from non-water areas. Fine-water area discrimination is performed using 4 × 4 mean and variance texture information from small-scale image blocks. The percentages of uncertain regions, suspected water areas, and land regions relative to non-zero pixels within the window are calculated. According to specific criteria, uncertain regions are corrected to either land or suspected water areas. Finally, 7 × 7 dilation and erosion operations are applied to refine the processing results.

4.

False Alarm Elimination

Due to the presence of small non-target regions, such as ponds or water-like areas, in SAR images, a hierarchical false alarm elimination method is designed based on the 8-directional connected domain labeling algorithm. Through three-level false alarm elimination, small-area false alarm regions are removed.

2.2. Oil Spill Detection Algorithm

The oil spill detection algorithm detects oil spill areas at sea and outputs a binary image with the same size as the original image, where the white areas represent the detected oil spills. The oil spill detection algorithm adopted in this paper [14] is shown in Figure 2. In the preprocessing stage, known geographical information is first used to remove the land part from the remote sensing image, and then Gaussian filtering is applied to remove noise in the image and smooth the edges of the target to be detected. In the oil spill extraction stage, the bottom-hat transform is first performed on the image to highlight the target areas. Then, the maximum entropy threshold of the image is calculated, and the image is threshold-segmented into a binary map. The initial oil spill extraction result is obtained through mode filtering. Finally, the false alarm regions are eliminated using the gray mean and connected domain area features of the targets of interest in the mode-filtered image, and the final oil spill detection result is obtained. The algorithm mainly consists of three parts, and the function breakdown of each part is shown in

Table 2. Overview Table of oil spill detection algorithm functions.

Serial Number	Step Name	Processing Functions
1	Data Preprocessing	7 × 7 Gaussian filtering, ocean region segmentation
2	Oil Spill Extraction	7 × 7 Bottom-hat transform, 4096 × 4096 maximum entropy threshold segmentation, 7 × 7 mode filtering
3	False Alarm Elimination	Gray mean-based false alarm elimination, connected domain area-based false alarm elimination

.

• Data Preprocessing

In actual on-board application scenarios, remote sensing images of the sea surface captured by SAR satellites may include some land areas, which will cause great interference to the subsequent oil spill target extraction. Therefore, before extracting oil spill candidate areas, the land areas in the original image can be removed by a mask operation according to the land–sea template binary image corresponding to the geographical location of the remote sensing image obtained from the land–sea database based on geographic information. Then, Gaussian filtering is used to remove noise from the SAR image. The Gaussian filtering expression is as follows, where $R$ is the gray value of the filtered pixel, $w_i$ is the Gaussian filter weight, and $n$ is the filter size, which is set to 7 in this work:

$$R={\displaystyle \sum _{i=1}^{n\times n}{w}_i{x}_i}$$

(2)

2.

Oil Spill Extraction

The oil spill target detection algorithm mainly extracts targets based on the threshold segmentation method. Therefore, the bottom-hat transform is first used to highlight the areas to be detected in the image, then the maximum entropy threshold segmentation is used to extract the targets of interest, and finally, the initial oil spill extraction results are obtained through multiple 7 × 7 mode filtering. The bottom-hat transform mainly performs pixel-by-pixel gray-level 7 × 7 dilation and erosion calculations on the input image. The calculation formula of maximum entropy threshold segmentation is as follows, where $H(x)$ represents the information entropy of the image and $p(x_i)$ is the probability distribution of pixel value $x_i$. Maximum entropy threshold segmentation selects a specific grayscale threshold to perform binary segmentation on an image. Pixels with intensity values lower than the threshold are classified as the oil spill target, while the remaining pixels are assigned to the sea background. The segmentation threshold is derived from the statistical grayscale histogram:

$$H(x)=-{\displaystyle \sum _{i=1}^{n}p(x_i)\log [p(x_i)]}$$

(3)

3.

False Alarm Elimination

Due to the complex actual sea surface conditions, there may be some non-oil spill targets, such as islands. Therefore, combined with the gray mean value and connected domain area information of the region of interest initially extracted by maximum entropy threshold segmentation, non-oil spills are eliminated to obtain the final detection binary result map. It mainly includes gray mean false alarm elimination and 8-directional connected domain area false alarm elimination.

3. Implementation Plan

The on-board radiation-hardened FPGA chip features a small logic scale and low storage capacity, while the water area and oil spill detection algorithms are computationally complex and generate a large number of intermediate results. How to implement these two algorithms under the condition of limited computing and storage resources has become an urgent problem to be solved. To address this issue, this paper conducts in-depth research on the optimal design strategies of computing engines, storage units, and processing architectures, aiming to improve the operation and storage efficiency of FPGA implementation and provide innovative ideas and methods for the implementation of complex on-board algorithms.

3.1. Efficient and Universal Computing Engine Design

Aiming at the problem that the limited on-board computing resources make it difficult to implement the two algorithms of water area and oil spill detection, an efficient and universal computing engine partitioning method based on coarse and fine granularity is proposed. By analyzing the processing flow and characteristics of the two algorithms, engine reuse design is carried out from both coarse-grained and fine-grained levels.

At the coarse-grained level, the processing flows of the two algorithms (water area detection and oil spill detection) are first split into basic operation steps. Then, to reduce computational redundancy and save processing resources, a universal computing engine is designed to handle the common operation steps of the two algorithms, such as filtering, downsampling, dilation, erosion, mean calculation, connected component labeling, and other operation steps. Furthermore, a dedicated computing engine is designed to handle the specific and non-reusable operations in each algorithm. Finally, the basic operation steps of the two algorithms are divided into three types of engines, as shown in

Table 3. Algorithm processing step statistics.

Processing Engine Category	Implemented Operation Steps
Universal Computing Engine	Downsampling, Filtering, Padding, Segmentation, Mean, Variance, Logical Operation, Threshold Calculation, Dilation, Erosion, Connected Component Labeling, and False Alarm Elimination
Dedicated Computing Engine for Water Area Detection Algorithm	Fine Extraction, and Secondary and Tertiary False Alarm Elimination
Dedicated Computing Engine for Oil Spill Detection Algorithm	Gray Mean False Alarm Elimination

.

To further reduce computing resources, a fine-grained engine partitioning method is proposed. By in-depth analysis of the complexity of data operations and the specific data reading methods within a single algorithm, it is found that the algorithm has strong regularity in data operation relationships and reading methods. Therefore, an engine partitioning method based on two dimensions—data operation relationships and reading methods—is proposed, as shown in

Table 4. Fine-grained clustering engine design statistics.

Engine Category	Data Operation Relationship	Reading Method	Algorithm Operation Steps
Overlapping Block Engine	For pixel matrix operations	Overlap between adjacent matrices	Filtering, Dilation, Erosion
Non-overlapping Block Engine	For pixel matrix operations	No overlap between adjacent matrices	Downsampling, Fine Extraction
Single Pixel Traversal Engine	For single pixel operations	Pixel traversal	Mean, Variance, Logical Operation, Connected Component Labeling, False Alarm Elimination, Padding, Segmentation, and Threshold Calculation

. The data operation relationship targets whether the operation object is a pixel matrix or a single pixel, and the reading method targets whether there is overlap in the operation mode. Finally, three types of processing engines are divided, and 13 detection algorithm operation steps are flexibly implemented through these three processing engines. Among these engines, the Overlapping Block Engine carries out 7 × 7 block processing, specifically implementing algorithm steps including 4 × 4 mean filtering, 7 × 7 Gaussian filtering, 7 × 7 mode filtering, 7 × 7 dilation, and 7 × 7 erosion.

3.2. Reusable Storage Optimization Strategy

Aiming at the problem of limited on-board storage resources, a highly reusable storage optimization strategy is proposed, which optimizes the design of storage buffers on both coarse-grained and fine-grained levels.

At the coarse-grained level, a cache unit sharing mechanism is designed to realize the reuse of the same cache space between the two algorithms. Through this design, the cache space required by the two algorithms can be satisfied in a single cache unit, thereby significantly improving the utilization rate of storage resources.

Furthermore, at the fine-grained level, by studying the data buffering cycle [17], a shared on-chip memory scheme is designed. By optimizing the data caching strategy and scheduling mechanism, it is ensured that the memory is fully utilized without an idle status. This storage optimization strategy, combining coarse and fine granularity, can effectively solve the problem of limited on-board storage resources.

3.3. Multi-Task-Compatible System Design

To meet the requirements of multiple tasks such as water area and oil spill detection, this paper proposes a hardware–software co-programmable efficient processing system. The soft core completes software programming and achieves flexible management by scheduling computing engines; the computing engines implement hardware programming, parse instructions from the soft core, and realize different operation computations through reconstruction. In addition, there are multiple concurrent channels between the shared on-chip buffer and the processing engine to achieve memory reuse. Compared with the traditional pipeline processing mechanism, this system has higher flexibility and reconfigurability, and it can better adapt to the needs of different processing tasks.

As shown in Figure 3, in this processing system, to improve system flexibility, a MicroBlazes (MBS) soft core is instantiated inside the FPGA module as the core control unit. This soft core undertakes the global control of the FPGA module, as well as the configuration of modules such as computing engines and shared on-chip buffers, realizing efficient process scheduling of the water area detection algorithm and the oil spill detection algorithm. To achieve efficient data interaction with the external high-speed memory DDR, the system introduces an xdma storage access module. This module supports flexible modulation of start address, step size, and single burst data volume, thereby endowing the system with extremely high data access flexibility. In terms of bus design, a combination of a data interconnection bus and a control signal bus is adopted. Among them, the data interconnection bus adopts standard AXI4 and AXI4-Stream buses, which ensures the smoothness of data interaction between modules and the convenience of customized functional module development, making data flow between different functional modules more efficient; the control signal bus adopts an APB protocol bus, which realizes comprehensive configuration and scheduling of the control unit, enabling the system to flexibly adjust the working status of modules according to actual needs and ensuring the orderly operation of various functions. In addition, a Serdes interface is adopted for high-speed data input and output transmission. This interface not only supports high-speed data transmission but also has excellent stability and reliability, ensuring the stable operation of the system in various complex environments.

3.4. Detection Algorithm Implementation

• Water Body Detection Algorithm Implementation

As can be seen in Table 1, the water body detection algorithm adopted in this paper is mainly divided into four steps. In the preprocessing step, mean filtering and zero-value filling are implemented through the configurable general-purpose computing engine in the hardware–software co-programmable high-efficiency processing architecture. In the block-level texture feature extraction step, block texture feature extraction, regional gray feature extraction, rough water body segmentation, and correction of rough segmentation results are realized via the configurable general-purpose computing engine. In the refined water body extraction step, refined extraction is achieved through the dedicated computing engine for water body detection algorithms, and post-processing, such as dilation and erosion, is completed by the configurable general-purpose computing engine. In the false alarm elimination step, connected component false alarm elimination is implemented using the configurable general-purpose computing engine, while two-level and three-level false alarm elimination are realized through the dedicated computing engine for water body detection algorithms.

The data flow of the final FPGA implementation is shown in Figure 4. The MBS control unit configures each module according to the algorithm steps. Firstly, it receives the imaged SAR image data through the Serdes interface. Then, the data is written into DDR for buffering via xdma. Subsequently, the data in DDR is read through xdma and transmitted to the configurable general-purpose computing engine and the dedicated computing engine for water body detection algorithms via the data interconnection bus to complete each step of the water body detection algorithm. The shared on-chip buffer caches small amounts of data during the computing process, while DDR handles large-volume data caching. To implement all algorithm steps, the arithmetic processing unit needs to perform multiple rounds of data processing under the scheduling of the MBS control unit, involving repeated reading and writing of DDR. Finally, after all algorithm steps are completed, the output results are sent out through the Serdes interface.

2.

Oil Spill Detection Algorithm Implementation

As can be seen from Table 2, the oil spill detection algorithm adopted in this paper is mainly divided into three steps. In the preprocessing step, Gaussian filtering and ocean region segmentation are implemented through the configurable general-purpose computing engine in the hardware–software co-programmable high-efficiency processing architecture. In the oil spill extraction step, bottom-hat transformation, maximum entropy threshold segmentation, and digital filtering are realized via the configurable general-purpose computing engine. In the false alarm elimination step, gray mean false alarm elimination is achieved through the dedicated computing engine for oil spill detection algorithms, and connected component false alarm elimination is implemented by the configurable general-purpose computing engine. The data flow of the final FPGA implementation is shown in Figure 5, and the processing flow is consistent with that of the water body detection algorithm.

4. Experiment and Result Analysis

The multi-task-compatible processing system proposed in this paper was designed using Verilog Hardware Description Language (Verilog HDL) and then synthesized and implemented using ISE Design Suite 14.6 software. A hardware platform with the radiation-hardened Xilinx XQR5VFX130T FPGA (San Jose, CA, USA) as the core was adopted, and the system operating frequency was 100 MHz.

The experimental data adopted include 10 SAR image data containing oil spill scenes collected by the GF-3 satellite and 10 SAR image data containing water area scenes collected by the GF-3 satellite. Each image has a pixel bit width of 8 bits and a size of 16,384 × 16,384 pixels (16K × 16K pixels).

4.1. Resource Analysis

Table 5. FPGA resource utilization.

Resource	Total Quantity	Used Quantity	Resource Utilization (%)
LUT	81,920	76,073	93
REG	81,920	70,422	86
RAM	298	249	84

presents the resource utilization of the Xilinx XQR5VFX130T FPGA in the multi-task-compatible processing architecture. It can be seen from the table that the most utilized resource in this architecture is the LUT (Look-Up-Table) resource. Although it reaches 93%, it does not exceed the total number of LUTs, so it can be mapped to the FPGA to realize water area and oil spill detection processing.

To further verify the resource overhead of the architecture proposed in this paper, the water area detection algorithm and the oil spill detection algorithm are separately implemented in the Xilinx XQR5VFX130T FPGA. The comparison results are shown in

Table 6. Comparison result of FPGA resource utilization.

Resource	Water Area Detection Usage Quantity	Oil Spill Detection Usage Quantity	Total Usage Quantity of the Two	Usage Quantity of This Method	Savings Rate of This Method
LUT	66,218	55,928	122,146	76,073	37.7%
REG	63,756	60,910	124,666	70,422	43.5%
RAM	237	207	444	249	43.9%

. It can be seen from the Table that by adopting this method, the LUT resources used for logical operations are reduced by 37.7%, and the RAM resources used for storage are reduced by 43.9%. This method can reduce the consumption of computing and storage resources.

4.2. Performance Analysis

• Processing Time

SAR remote sensing image data containing oil spill scenes or water area scenes collected by the GF-3 satellite is used as test data to verify the FPGA processing performance. Some test results are shown in Figure 6 and Figure 7. At a clock frequency of 100 MHz, the processing time for a 16K × 16K water area scene image is 15 s, and for a 16K × 16K oil spill scene image, it is 13 s.

2.

Real-Time Performance Analysis

For the on-board processing of SAR satellites, the original SAR echo data must first undergo imaging processing, and then the SAR image is subjected to detection processing. The imaging processing and detection processing adopt pipeline parallel processing, and the processing flow is shown in Figure 8. When the detection time Td of one scene is ≤the imaging time Ti of one scene, the detection processing is real-time processing; when the detection time Td of one scene is >the imaging time Ti of one scene, after imaging, it is necessary to wait for the detection processing of the previous scene to be completed before executing the detection processing of the current scene, and real-time processing cannot be realized. In this paper, for a 16K × 16K SAR scene image, the maximum detection processing time is 15 s. Therefore, when the imaging time of 16K × 16K original echo data is ≥15 s [18,19,20,21], this scheme has real-time detection performance.

4.3. Comparison with Other Methods

To further verify the timeliness of the architecture proposed in this paper, a comparison is made with other existing hardware schemes, as shown in

Table 7. Comparison of the processing time of different methods.

Reference	Function	Image Size	Processor	Clock Frequency	Processing Time	Per-Pixel Throughput
[5]	Water Area Detection	20,000,000 pixels	Zynq UltraScale + MPSoC ZCU102	500 MHz	400 s	0.048 Mpix/s
This Paper	Water Area Detection	16,384 × 16,384 pixels	XQR5VFX130T	100 MHz	15 s	17.07 Mpix/s
[15]	Oil Spill Detection	1200 × 1200 pixels	Zynq 7020	600 MHz	4.5 s	0.31 Mpix/s
This Paper	Oil Spill Detection	16,384 × 16,384 pixels	XQR5VFX130T	100 MHz	13 s	19.69 Mpix/s

.

Carlos Garcia [5] et al. proposed an FPGA-based water area detection system. For 20,000,000-pixel images, the processing time is about 400 s on Xilinx’s Zynq UltraScale (San Jose, CA, USA) + MPSoC ZCU102 platform (San Jose, CA, USA). In this paper, for 16,384 × 16,384-pixel (268,435,456-pixel) SAR images, the processing time is only 15 s. Therefore, this paper has better timeliness in water area detection.

A SAR image oil spill detection method is proposed in Document [15]. For 1200 × 1200-pixel SAR images, dual-core ARM parallel processing is used on the Zynq 7020 FPGA development board (San Jose, CA, USA), with a processing time of 4.5 s. In contrast, this paper only takes 13 s to process large 16,384 × 16,384-pixel SAR images, so it has better timeliness in oil spill detection.

5. Conclusions

Aiming at the real-time processing requirements under the strict constraints of on-board resources, this paper proposes a hardware–software co-programmable efficient processing system, which can complete the rapid on-board processing of water area and oil spill target detection. To reduce the occupation of computing resources, by analyzing the operation steps of water area and oil spill detection algorithms, an efficient and universal computing engine partitioning method based on coarse and fine granularity is designed. To reduce the consumption of storage resources, a shared on-chip memory is designed. Finally, experimental verification proves the feasibility and real-time performance of the method. This method provides a reference for on-board multi-task processing. In future work, based on this hardware–software co-programmable efficient processing system, it is expected to realize more diverse tasks (such as ship detection and recognition) on FPGA platforms with richer resources.