Multibattery Charger System Based on a Multilevel Dual-Active-Bridge Power Converter

Abstract

This work introduces a novel battery charger implemented with a four-level three-phase neutral-point-clamped converter and a four-level single-phase dual-active-bridge converter, which offers the intrinsic advantages of multilevel conversion, provides galvanic isolation and allows bidirectional power flow. A detailed and extensive modeling of the system is developed, together with the design of appropriate closed-loop control and modulation. The proposed system allows individual charging of each battery pack, ensuring that the full capacity of the battery bank is utilized, even when the battery packs have different state-of-charge levels, differ in nominal capacities, or use different chemistries. Furthermore, the proposed control system manages the overall DC-link voltage and ensures voltage balance across both DC-links in the system. The effectiveness of the proposed system configuration and control has been validated through simulations. The simulation results show good dynamic response in different operating scenarios, confirming the suitability, feasibility, and benefits of the proposed implementation and control approach.

1. Introduction

The role of batteries is becoming more and more important, given the technological evolution in recent years. With regard to the electric vehicle (EV), its rapid expansion [1,2] has intensified the demand for fast, efficient, and smart battery chargers, since the battery is the heart of the EV. Moreover, the use of smart bidirectional battery chargers enables the use of the energy stored in the batteries of the EV as a flexible energy storage unit in diverse applications, a system collectively known as vehicle-to-X [2,3,4,5,6,7,8], employed, for instance, to feed loads (vehicle-to-load, V2L) or to exchange energy with other vehicles (vehicle-to-vehicle, V2V), houses (vehicle-to-home, V2H), or the electric grid (vehicle-to grid, V2G).

Batteries can also be applied to enhance the integration of renewable energy sources into the power network. Since the energy production of renewable energy sources obviously depends on the weather, a battery energy storage system (BESS) [9,10,11] can be used to store the energy surplus when more energy is produced than necessary, to be used at a later time when there is energy consumption but no energy production. To do it, the BESS requires a smart bidirectional battery charger.

In the context described above, battery chargers must deal with increasingly complex requirements, including the management of diverse battery chemistries [9], voltages, and capacities, ensuring optimal performance in terms of efficiency, reliability, and adaptability [12,13], and meeting the corresponding standards [3,14].

Battery chargers have been extensively reported in the literature [2,3,15,16,17,18,19], where the most common approach is based on conventional two-level converters. Isolation is an usual requirement for battery chargers, which can be fulfilled by means of a bulky grid frequency transformer or preferably with a dual-active-bridge (DAB) converter [20], given its advantages of bidirectional power flow capability, soft-switching commutations, low cost, operational flexibility, and high efficiency [21]. DAB converters are particularly well suited for interfacing with EV charging stations and renewable energy storage systems, where operational flexibility and efficiency are critical [20].

Recent works [22,23,24] have demonstrated the feasibility and suitability of three-level DAB converters for battery charger applications. This topology offers the intrinsic advantages of a multilevel structure [25,26], voltage stress reduction on power semiconductors, harmonic distortion improvement, and converter efficiency increase together with improved voltage regulation and enhanced power quality, in comparison to the conventional two-level converters. These features are pivotal as EVs and renewable energy systems demand higher power densities, broader voltage ranges, and stricter efficiency targets.

The present work goes one step further and introduces a four-level battery charger (4L-BC) based on an extended DAB converter topology, which apparently has not been previously described in the literature. This manuscript presents a complete model of the system (switching model, large-signal averaged model, and small-signal linear model), together with the design of the proper modulation and closed-loop control. The proposed approach presents some significant characteristics, which are described below.

The four-level structure provides reduced voltage stress on semiconductor devices, leading to better reliability and longer component lifespans, and smaller harmonic distortion, resulting in improved power quality and reduced electromagnetic interference [26,27].

The closed-loop control and modulation algorithms play a key role in the proposed system. For the grid-side converter, power factor control, a low harmonic distortion of the grid current, and DC-link capacitor voltage balance [28] are achieved. For the DAB converter, the charge/discharge current across each battery pack can be precisely controlled [27].

This last feature is particularly relevant. Since the charge/discharge current can be particularized for each battery pack, this can be extremely useful in the case of heterogeneous batteries with different state-of-charge (SoC), chemistries, or capacities [29,30,31]. The proposed system allows for the efficient and independent regulation for each battery, optimizing the overall charging and discharging process and ensuring a proper SoC balance across the battery packs [27]. The ability to handle batteries with different SoCs is essential for achieving optimal energy utilization and prolonging battery lifespans.

In summary, this work contributes to the ongoing development of multibattery charging systems by offering a comprehensive analysis of the four-level DAB converter capabilities. Through detailed analysis and simulation, this study validates the 4L-BC as a possible solution for next-generation battery charging applications.

This manuscript is structured as follows: Section 2 introduces the proposed charger topology, highlighting its design features. Section 3, Section 4 and Section 5 develop the switching model, large-signal averaging model, and small-signal linear model, respectively. Section 6 describes the control system design and the modulation algorithms and provides the system transfer functions. Section 7 presents the system stability analysis and the time-domain simulation results, offering insights into system behavior under various operating conditions. Finally, Section 8 concludes the manuscript by summarizing the key findings and contributions.

2. Battery Charger Topology

Figure 1 illustrates the topology and circuit model of the proposed 4L-BC in detail. It is worth mentioning that the system described in Figure 1 is bidirectional, that is, power can flow from the grid to the batteries and vice versa. The system is connected to the three-phase AC grid through an inductive filter and an AC-DC conversion stage. This stage employs a four-level neutral-point-clamped (NPC) converter [26], identified as 4L-3P-NPC converter in Figure 1, which performs the AC-DC conversion between the AC grid and the a-side DC-link.

The DC-DC conversion stage between the a-side DC-link and the b-side DC-link is implemented by using a four-level single-phase dual-active-bridge (4L-1P-DAB) converter [25] integrated with a high-frequency transformer (HFT). This converter guarantees efficient power conversion and galvanic isolation between both DC-link sides. Capacitors C_a and C_b on the a-side and b-side, respectively, with parallel resistors R_Ca and R_Cb, ensure voltage stability and dissipate excess energy to prevent overvoltage [23].

The battery bank consists of three battery packs, which are connected between the voltage levels 1_b–2_b, 2_b–3_b, and 3_b–4_b of the b-side DC-link, respectively, as depicted in Figure 1.

3. Battery Charger Switching Model

The development of the switching model for the 4L-BC involves the modeling of the 4L-3P-NPC converter, the 4L-1P-DAB converter, and the battery bank. Each component is analyzed individually to describe their switching dynamics across varying operational states.

The 4L-3P-NPC converter model describes the interaction among the voltages and currents of the AC grid and the a-side DC-link through the switching states of the converter. For the 4L-1P-DAB converter, the model includes the dynamics of the HFT and the b-side DC-link, with an emphasis on switching event timing to regulate power flow between the b-side DC-link and the battery bank [32,33]. The battery bank model reflects the electrical characteristics of each individual battery pack and their combined response to charging currents determined by converter operation.

This component-wise modeling provides a comprehensive switching model for the entire 4L-BC system, facilitating the understanding of component interactions and enabling control strategy optimization for enhanced performance and efficiency.

3.1. 4L-3P-NPC Converter Switching Model

Figure 2 illustrates the switching model of the 4L-3P-NPC converter. AC grid voltages (with respect to N) are denoted as e_a, e_b, and e_c, AC grid currents as i_a, i_b, and i_c, and the voltages at the AC port of the converter (with respect to DC-rail 1_a) as v_a1, v_b1, and v_c1. The capacitor voltages C_a are represented by v_Ca1, v_Ca2, and v_Ca3, with corresponding a-side DC-link currents i₁, i₂, i₃, and i₄. Additionally, i_1a, i_2a, i_3a, and i_4a denote the currents flowing from the 4L-3P-NPC converter into the 4L-1P-DAB converter, as shown in Figure 2. The parameters R_ac and L_ac represent the AC grid filter resistor and inductor values, while R_Ca and C_a indicate the bleeding resistors and capacitors of the a-side DC-link.

The developed model for the 4L-3P-NPC converter provides the equations for the AC grid and the a-side DC-link. These equations, obtained from Figure 2, are presented as follows:

$${\displaystyle \frac{\mathrm{d}{\mathbf{x}}_{\mathbf{1}}}{\mathrm{d}t}}={\mathbf{A}}_{\mathbf{1}}\left(t\right)·{\mathbf{x}}_{\mathbf{1}}+{\mathbf{B}}_{\mathbf{1}}·{\mathbf{u}}_{\mathbf{1}}$$

(1)

where x₁ = [i_a, i_b, i_c, v_Ca1, v_Ca2, v_Ca3]^T and u₁ = [e_a, e_b, e_c, i_2a, i_3a, i_4a]^T. Symbolically,{x₁, u₁} ∈ {ℝ⁶}. The switching functions in (1) are defined by:

$$s_{ij}=\left\{\begin{array}{l}1, i \mathrm{c}\mathrm{o}\mathrm{n}\mathrm{n}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{e}\mathrm{d} \mathrm{to} j\\ 0, \mathrm{e}\mathrm{l}\mathrm{s}\mathrm{e}\end{array}\right.$$

(2)

s_i1a + s_i2a + s_i3a + s_i4a = 1

(3)

for i ∈ {a, b, c} and j ∈ {1_a, 2_a, 3_a, 4_a}. The model in (1) is discrete and nonlinear, due to the inclusion of the switching functions within the state matrix A₁(t), as developed in [20]. The state matrix A₁(t) and the input matrix B₁ are defined in Appendix A.

3.2. 4L-1P-DAB Converter Switching Model

Figure 3 provides a comprehensive switching model of the 4L-1P-DAB converter. In this model, the primary and secondary side input currents of the HFT are denoted as i_aT and i_bT, respectively, and the magnetizing current is represented by i_mT. The input terminal voltages on the HFT’s primary and secondary sides are labeled as v_aT and v_bT, respectively. Parameters R_Lk, L_k, L_m, and a_tr correspond to the resistance and leakage inductance of the HFT windings, the magnetizing inductance, and the turn ratio (a_tr = 1/n) of the HFT, respectively. The relationship between leakage and magnetizing inductance is expressed as L_k||L_m = L_m∙L_k/L_k + L_m, reflecting the parallel combination in the equivalent circuit.

The b-side DC-link voltages across capacitors are denoted by v_Cb1, v_Cb2, and v_Cb3. The currents through the b-side DC-link, i_1b, i_2b, i_3b, and i_4b, correspond to the currents entering the battery bank, while i_1o, i_2o, i_3o, and i_4o are the currents directly flowing through the battery bank.

The model also incorporates the capacitors C_b and the bleeding resistors R_Cb of the b-side DC-link. This switching model describes the dynamic behavior of the 4L-1P-DAB converter, emphasizing its interaction with the battery bank and detailing the complex interplay between converter components and the battery storage system.

Based on the configuration in Figure 3, the switching model of the 4L-1P-DAB converter is presented in the following:

$${\displaystyle \frac{\mathrm{d}{\mathbf{x}}_{\mathbf{2}}}{\mathrm{d}t}}={\mathbf{A}}_{\mathbf{2}}\left(t\right)·{\mathbf{x}}_{\mathbf{2}}+{\mathbf{B}}_{\mathbf{2}}·{\mathbf{u}}_{\mathbf{2}}$$

(4)

where x₂ = [v_Ca1, v_Ca2, v_Ca3, i_aT, i_mT, i_bT, v_Ca1, v_Ca2, v_Ca3]^T and u₂ = [i₂, i₃, i₄, i₂₀, i₃₀, i₄₀]^T. Symbolically, x₂ ∈ {ℝ⁹} and u₂ ∈ {ℝ⁶}. Matrices A₂(t) and B₂ are defined in Appendix A, as in the case of the 4L-3P-NPC converter. In this converter, the state matrix A₂(t) is also time-varying, mainly due to the presence of the switching functions. The corresponding switching functions of the converter are defined as follows:

$$\begin{gathered} s_{vw}=\left\{\begin{array}{c}1, v \mathrm{c}\mathrm{o}\mathrm{n}\mathrm{n}\mathrm{e}\mathrm{c}\mathrm{t}\mathrm{e}\mathrm{d} \mathrm{to} w\hfill \\ 0, \mathrm{else}\hfill \end{array}\right.,\mathrm{where} \\ v\in \{1_{\mathrm{a}}, 2_{\mathrm{a}}, 3_{\mathrm{a}}, 4_{\mathrm{a}}, 1_{\mathrm{b}}, 2_{\mathrm{b}2}, 3_{\mathrm{b}}, 4_{\mathrm{b}}, \}, w\in \{{\mathrm{a}}_{1\mathrm{T}}, {\mathrm{a}}_{2\mathrm{T}}, {\mathrm{b}}_{1\mathrm{T}}, {\mathrm{b}}_{2\mathrm{T}}\} \end{gathered}$$

(5)

s_1aw + s_2aw + s_3aw + s_4aw = 1

(6)

s_1bw + s_2bw + s_3bw + s_4bw = 1

(7)

3.3. Battery Bank Model

The configuration of the battery bank within the 4L-BC system is detailed in Figure 4. The battery bank consists of three battery packs connected to the b-side DC-link, with its mathematical model given by:

$${\displaystyle \frac{\mathrm{d}{\mathbf{i}}_{\mathbf{B}}}{\mathrm{d}t}}=-{\displaystyle \frac{R_{\mathrm{d}\mathrm{c}}}{L_{\mathrm{d}\mathrm{c}}}}·{\mathbf{I}}_{\mathbf{3}}·{\mathbf{i}}_{\mathbf{B}}+{\displaystyle \frac{1}{L_{\mathrm{d}\mathrm{c}}}}·{\mathbf{B}}_{\mathbf{3}}·\mathbf{v}$$

(8)

where i_B = [i_B1, i_B2, i_B3]^T and v = [v_Cb1, v_Cb2, v_Cb3, v_B1, v_B2, v_B3]^T. Symbolically, i_B ∈ {ℝ³} and v ∈ {ℝ⁶}. In addition, I₃ is the 3 × 3 identity matrix and B₃ is defined in Appendix A. Also, i_B1, i_B2, and i_B3 denote the charging currents, while v_B1, v_B2, and v_B3 represent the terminal voltages of the respective battery packs.

The inductance L_dc and resistance R_dc of the wires affect the transient and steady-state behavior of the system during the charging process. Each battery pack in the bank is modeled using a Thévenin equivalent circuit [29,30], which incorporates a voltage source representing the open-circuit voltage of the battery, indicative of its state of charge.

4. Large-Signal Averaged Model

The large-signal averaged models of the three main components of the 4L-BC system are presented in this section: the 4L-3P-NPC converter, the 4L-1P-DAB converter, and the battery bank. These models help to analyze the dynamic behavior of the 4L-BC system under different operating conditions, providing a macroscopic view by smoothing out high-frequency switching effects and aiding in control algorithm design [32,33].

The 4L-3P-NPC converter model describes the interactions between the AC grid and DC-link, while the 4L-1P-DAB converter model details the HFT operation. The battery bank model accounts for electrochemical characteristics and charge/discharge cycles [27]. These averaged models support developing control strategies to improve efficiency, stability, and energy management.

Classical control theory uses continuous-time representations, requiring an averaging operator to convert discrete switching signals into continuous duty ratios. The averaging operator is defined as follows:

$${〈x〉}_{T_{\mathrm{s}}}={\displaystyle \frac{1}{T_{\mathrm{s}}}}·{\int }_{t-T_{\mathrm{s}}}^{t}x\left(\tau \right)\mathrm{d}\tau$$

(9)

To ensure accurate correlation between actual and averaged values, the switching frequency f_s must be significantly higher than the AC grid fundamental frequency f_o. In this work, a 10 kHz frequency is used for both converters, which is higher than the 50 Hz grid frequency.

Applying this averaging process enables developing continuous-time models for effective control system design, bridging the gap between the discrete nature of power electronics and the classical control methodologies.

4.1. 4L-3P-NPC Converter Large-Signal Averaged Model

The averaging operator defined in (9) is applied to the switching model of the converter, as detailed in (1). The Park transformation then provides the large-signal averaged model in the D-Q reference frame. The resulting compact differential equation is given by:

$$\begin{gathered} {\displaystyle \frac{\mathrm{d}{〈{\mathit{v}}_{{\mathbf{C}}_{{\mathbf{a}}_{\mathit{i}}}}〉}_{{\mathit{T}}_{\mathbf{s}}}}{\mathrm{d}t}}=-{\displaystyle \frac{1}{C_{\mathrm{a}}}}·\left[{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{a}}_i}}〉}_{T_{\mathrm{s}}}}{R_{{\mathrm{C}}_{\mathrm{a}}}}}\right.+\sum _{j\ne i}{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{a}}_i}}〉}_{T_{\mathrm{s}}}·{〈i_2〉}_{T_{\mathrm{s}}}}{{\sum }_{k=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{a}}_k}}〉}_{T_{\mathrm{s}}}}}+{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{a}}_m}}〉}_{T_{\mathrm{s}}}·{〈i_3〉}_{T_{\mathrm{s}}}}{{\sum }_{k=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{a}}_k}}〉}_{T_{\mathrm{s}}}}}+\sum _{n=2}^4{〈i_{n_{\mathrm{a}}}〉}_{T_{\mathrm{s}}}+ \\ \left.+{\displaystyle \frac{{〈v_{\mathrm{d}}〉}_{T_{\mathrm{s}}}·{〈i_{\mathrm{d}}〉}_{T_{\mathrm{s}}}+{〈v_{\mathrm{q}}〉}_{T_{\mathrm{s}}}·{〈i_{\mathrm{q}}〉}_{T_{\mathrm{s}}}}{{\sum }_{k=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{a}}_k}}〉}_{T_{\mathrm{s}}}}}\right], \mathrm{h}\mathrm{e}\mathrm{r}\mathrm{e}\left\{i, j, k\right\}\in \left\{1,2,3\right\}, j\ne i, m\ne i\ne j \end{gathered}$$

(10)

The resulting model consists of five state variables, ⟨i_d⟩_Ts, ⟨i_q⟩_Ts, ⟨v_Ca1⟩_Ts, ⟨v_Ca2⟩_Ts, and ⟨v_Ca3⟩_Ts, and six input variables, ⟨i₂⟩_Ts, ⟨i₃⟩_Ts, ⟨i_2a⟩_Ts, ⟨i_3a⟩_Ts, and ⟨i_4a⟩_Ts, plus control variables ⟨v_d⟩_Ts and ⟨v_q⟩_Ts.

Although the model is nonlinear, its variables reach constant values in steady state, making it valuable to analyze the behavior of the 4L-3P-NPC converter and to design proper control strategies.

4.2. 4L-3P-DAB Converter Large-Signal Averaged Model

The derivation of the large-signal averaged model for the 4L-1P-DAB converter begins with establishing a phasor representation as the converter’s fundamental model, based on [20]. Figure 5 presents the sinusoidal steady-state model, focusing solely on the fundamental frequency, equated to the switching frequency f_s for simplicity [20,25]. This model considers two phase-shifted sinusoidal AC voltages with amplitudes determined by modulation angles α_x1, α_x2, and α_x3, where x ∈ {a, b}, as detailed below in Section 6.4.

The key circuit parameters are defined as follows:

$$\left\{\begin{array}{c}{\mathbf{X}}_{{\mathrm{L}}_{\mathrm{k}}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)={\omega }_{\mathrm{s}}·L_{\mathrm{k}}\\ {\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)=R_{{\mathrm{L}}_{\mathrm{k}}}+j·{\mathbf{X}}_{{\mathrm{L}}_{\mathrm{k}}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\\ K_x={\displaystyle \frac{2}{3·\mathsf{\pi }}}·\left(\cos \left({\displaystyle \frac{\mathsf{\pi }}{2}}-{\alpha }_{x1}\right)+\cos \left({\displaystyle \frac{\mathsf{\pi }}{2}}-{\alpha }_{x2}\right)+\cos \left({\displaystyle \frac{\mathsf{\pi }}{2}}-{\alpha }_{x3}\right)\right), x\in \left\{\mathrm{a},\mathrm{b}\right\}\\ {\mathbf{V}}_{\mathrm{a}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)=K_{\mathrm{a}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}⟨{\theta }_{\mathrm{a}}\\ {\mathbf{V}}_{\mathrm{b}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)=a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}⟨{\theta }_{\mathrm{a}}-\varphi \end{array}\right.$$

(11)

The AC voltage amplitudes are expressed as V_a(j⋅ω_s) = K_a⋅v_dca ∠ θ_a and V_b(j⋅ω_s) = a_tr⋅K_b⋅v_dcb ∠ (θ_a − ϕ).

Power transfer at the HFT input P_aHFT and output P_bHFT is obtained and shown as follows:

$$\left\{\begin{array}{c}{P}_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}={\mathcal{R}}_{\mathrm{e}}\left\{{\mathbf{V}}_{\mathrm{a}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)·{\mathbf{I}}^{\mathrm{*}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right\}\\ {\mathbf{I}}^{\mathrm{*}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)=\begin{array}{c}{\displaystyle \frac{1}{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}}·\left(K_{\mathrm{a}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}·\sin \left({\theta }_{\mathrm{a}}+\sigma \right)-a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·\sin \left({\theta }_{\mathrm{a}}-\varphi +\sigma \right)\right)-\end{array}\\ -j·{\displaystyle \frac{1}{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}}·\left(K_{\mathrm{a}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}·\sin \left({\theta }_{\mathrm{a}}-\upsilon \right)-a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·\sin \left({\theta }_{\mathrm{a}}-\varphi -\upsilon \right)\right)\\ \sigma ={\mathit{tan}}^{-1}\left({\displaystyle \frac{R_{L_k}}{{\mathit{X}}_{L_k}\left(j·{\omega }_s\right)}}\right), \upsilon ={\tan }^{-1}\left({\displaystyle \frac{{\mathbf{X}}_{{\mathrm{L}}_{\mathrm{k}}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)}{R_{{\mathrm{L}}_{\mathrm{k}}}}}\right)\\ P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}={\displaystyle \frac{K_{\mathrm{a}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}}·\left(K_{\mathrm{a}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}·\left(\sin \left({\theta }_{\mathrm{a}}+\sigma \right)·\cos {\theta }_{\mathrm{a}}+\sin \left({\theta }_{\mathrm{a}}-\upsilon \right)·\sin {\theta }_{\mathrm{a}}\right)-\right.\\ -\left.a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·v_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·\left(\sin \left({\theta }_{\mathrm{a}}-\varphi +\sigma \right)·\cos {\theta }_{\mathrm{a}}+\sin \left({\theta }_{\mathrm{a}}-\varphi -\upsilon \right)·\sin {\theta }_{\mathrm{a}}\right)\right)\end{array}\right.$$

(12)

$$\left\{\begin{array}{c}{P}_{{\mathrm{b}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}=-\left(P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}+P_{{\mathrm{R}}_{{\mathrm{L}}_{\mathrm{k}}}}\right)\\ P_{{\mathrm{R}}_{{\mathrm{L}}_{\mathrm{k}}}}=R_{{\mathrm{L}}_{\mathrm{k}}}·{\left|\mathbf{I}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}^2\end{array}\right.$$

(13)

Considering θ_a = 0, the maximum input power P_aHFTmax can be defined as follows:

$$P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}={\displaystyle \frac{K_{\mathrm{a}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}{{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}^2}}·\left(K_{\mathrm{a}}·R_{{\mathrm{L}}_{\mathrm{k}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}-a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|·\sin \left(\phi -\sigma \right)\right)$$

(14)

and the achieved phase shift ϕ = π/2 is aligned with the steady-state operation values in [20,25], confirming the validity of the model.

The dynamic large-signal model is obtained by developing the following:

$$\begin{array}{c}{\displaystyle \frac{\mathrm{d}{〈v_{{\mathrm{C}}_{{\mathrm{a}}_k}}〉}_{T_{\mathrm{s}}}}{\mathrm{d}t}}=-{\displaystyle \frac{1}{C_{\mathrm{a}}}}·\left[{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{a}}_k}}〉}_{T_{\mathrm{s}}}}{R_{{\mathrm{C}}_{\mathrm{a}}}}}+{\displaystyle \sum _{j\ne k}}{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{a}}_j}}〉}_{T_{\mathrm{s}}}·\left({〈i_j〉}_{T_{\mathrm{s}}}+{〈i_{j_{\mathrm{a}}}〉}_{T_{\mathrm{s}}}\right)}{{\sum }_{m=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{a}}_m}}〉}_{T_{\mathrm{s}}}}}+{\displaystyle \frac{p_{\mathrm{d}\mathrm{q}}+p_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}}{{\sum }_{m=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{a}}_m}}〉}_{T_{\mathrm{s}}}}}\right]\\ \mathrm{for} \left\{j,k\right\}\in \{\mathrm{1,2},3\}\end{array}$$

(15)

$$\begin{array}{c}{\displaystyle \frac{\mathrm{d}{〈v_{{\mathrm{C}}_{{\mathrm{b}}_k}}〉}_{T_{\mathrm{s}}}}{\mathrm{d}t}}={\displaystyle \frac{1}{C_{\mathrm{b}}}}·\left[-{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{b}}_k}}〉}_{T_{\mathrm{s}}}}{R_{{\mathrm{C}}_{\mathrm{b}}}}}+{\displaystyle \sum _{j\ne k}}{\displaystyle \frac{{〈v_{{\mathrm{C}}_{{\mathrm{b}}_j}}〉}_{T_{\mathrm{s}}}·{〈i_{j_{\mathrm{b}}}〉}_{T_{\mathrm{s}}}}{{\sum }_{m=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{b}}_m}}〉}_{T_{\mathrm{s}}}}}+{\displaystyle \frac{p_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}+p_{{\mathrm{R}}_{{\mathrm{L}}_{\mathrm{k}}}}}{{\sum }_{m=1}^3{〈v_{{\mathrm{C}}_{{\mathrm{b}}_m}}〉}_{T_{\mathrm{s}}}}}-{〈i_{{\mathrm{B}}_k}〉}_{T_{\mathrm{s}}}\right]\\ \mathrm{for} \left\{j,k\right\}\in \{\mathrm{1,2},3\}\end{array}$$

(16)

These equations relate the AC grid in the D-Q frame with the a-side DC-link and also relate the HFT power terms p_aHFT and p_bHFT to the battery charging currents i_B1, i_B2, and i_B3. This development provides an accurate representation of the large-signal behavior of the converter in steady-state and dynamic operation.

5. Small-Signal Model

The large-signal averaged models for the 4L-BC are established for the 4L-3P-NPC converter in (10) and for the 4L-1P-DAB converter in (15) and (16). Both models are continuous but nonlinear. However, linear control techniques are preferred for simplicity and extensive experience.

To utilize linear control techniques, it is essential to linearize the large-signal averaged models by applying the perturbation technique and Taylor series development around the operating point of the system, as described in [32,34]. The operating points are calculated by setting the time derivatives to zero in (10), (15), and (16), and then substituting all variables with their steady-state expressions (denoted in capital letters). The resulting steady-state model of the 4L-BC is given by:

$$\left\{\begin{array}{c}-R_{\mathrm{a}\mathrm{c}}·I_{\mathrm{d}}+\omega ·L_{\mathrm{a}\mathrm{c}}·I_{\mathrm{q}}-E_{\mathrm{l}\mathrm{t}\mathrm{l}}+V_{\mathrm{d}}=0\\ -\omega ·L_{\mathrm{a}\mathrm{c}}·I_{\mathrm{d}}-R_{\mathrm{a}\mathrm{c}}·I_{\mathrm{q}}+V_{\mathrm{q}}=0\\ {\displaystyle \frac{1}{R_{{\mathrm{C}}_{\mathrm{a}}}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}+{\displaystyle \frac{\left(-2·V_{{\mathrm{C}}_{{\mathrm{a}}_1}}+V_{{\mathrm{C}}_{{\mathrm{a}}_2}}+V_{{\mathrm{C}}_{{\mathrm{a}}_3}}\right)}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}}·\left(I_2+I_{2_{\mathrm{a}}}\right)+{\displaystyle \frac{\left(-V_{{\mathrm{C}}_{{\mathrm{a}}_1}}-V_{{\mathrm{C}}_{{\mathrm{a}}_2}}+2·V_{{\mathrm{C}}_{{\mathrm{a}}_3}}\right)}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}}·\left(I_3+I_{3_{\mathrm{a}}}\right)+3·{\displaystyle \frac{P_{\mathrm{d}\mathrm{q}}+P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}}=0\\ -{\displaystyle \frac{1}{R_{{\mathrm{C}}_{\mathrm{b}}}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}+{\displaystyle \frac{\left(-2·V_{{\mathrm{C}}_{{\mathrm{b}}_1}}+V_{{\mathrm{C}}_{{\mathrm{b}}_2}}+V_{{\mathrm{C}}_{{\mathrm{b}}_3}}\right)}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}}}·I_{2_{\mathrm{b}}}+{\displaystyle \frac{\left(-V_{{\mathrm{C}}_{{\mathrm{b}}_1}}-V_{{\mathrm{C}}_{{\mathrm{b}}_2}}+2·V_{{\mathrm{C}}_{{\mathrm{b}}_3}}\right)}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}}}·I_{3_{\mathrm{b}}}+3·{\displaystyle \frac{P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}+P_{{\mathrm{R}}_{{\mathrm{L}}_{\mathrm{k}}}}}{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}}}-\left(I_{{\mathrm{B}}_1}-I_{{\mathrm{B}}_2}-I_{{\mathrm{B}}_3}\right)=0\\ -R_{\mathrm{d}\mathrm{c}}·\left(I_{{\mathrm{B}}_1}+I_{{\mathrm{B}}_2}+I_{{\mathrm{B}}_3}\right)+V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}-\left(V_{{\mathrm{B}}_1}+V_{{\mathrm{B}}_2}+V_{{\mathrm{B}}_3}\right)=0\\ P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}={\displaystyle \frac{K_{\mathrm{a}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}{{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|}^2}}·\left\{K_{\mathrm{a}}·R_{{\mathrm{L}}_{\mathrm{k}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}-a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|·\sin \left(\phi -\sigma \right)\right\}\\ P_{\mathrm{d}\mathrm{q}}=I_{\mathrm{d}}·V_{\mathrm{d}}+I_{\mathrm{q}}·V_{\mathrm{q}}\end{array}\right.$$

(17)

The model captures the dynamics of the voltage differences across capacitors C_a and C_b (denoted as v_Cxy, where x ∈ {a, b} and y ∈ {1, 2, 3}), emphasizing the impact of the currents flowing through the midpoints (neutral points) on the capacitor voltage balance, which will be explored in a later subsection.

To simplify (17), known steady-state variables—including currents I_q, I₂, I_2a, I₃, I_3a, I_2b, I_3b, I_B1, I_B2, and I_B3 and voltages E_ltl, V_Ca1, V_Ca2, V_Ca3, V_Cb1, V_Cb2, V_Cb3, V_B1, V_B2, and V_B3—are considered. Additionally, currents I_q and those flowing through the neutral points (I₂, I_2a, I₃, I_3a, I_2b, and I_3b) are assumed to be zero. This leads to obtaining the unknown variables I_d, V_d, V_q, and ϕ defined by:

$$\left\{\begin{array}{c}{I}_{\mathrm{d}}=\sqrt{{\left({\displaystyle \frac{E_{\mathrm{l}\mathrm{t}\mathrm{l}}}{2·R_{\mathrm{a}\mathrm{c}}}}\right)}^2-{\displaystyle \frac{P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}}{R_{\mathrm{a}\mathrm{c}}}}-{\displaystyle \frac{1}{3}}·{\displaystyle \frac{{V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}^2}{R_{\mathrm{a}\mathrm{c}}·R_{{\mathrm{C}}_{\mathrm{a}}}}}}-{\displaystyle \frac{E_{\mathrm{l}\mathrm{t}\mathrm{l}}}{2·R_{\mathrm{a}\mathrm{c}}}}\\ V_{\mathrm{d}}=E_{\mathrm{l}\mathrm{t}\mathrm{l}}+R_{\mathrm{a}\mathrm{c}}·I_{\mathrm{d}}\\ V_{\mathrm{q}}=\omega ·L_{\mathrm{a}\mathrm{c}}·I_{\mathrm{d}}\\ \phi ={\sin }^{-1}\left\{{\displaystyle \frac{\left|{\mathbf{Z}}_{\mathrm{k}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)\right|·P_{{\mathrm{a}}_{\mathrm{H}\mathrm{F}\mathrm{T}}}}{a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{a}}·K_{\mathrm{b}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·{\mathbf{X}}_{{\mathrm{L}}_{\mathrm{k}}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)}}-{\displaystyle \frac{K_{\mathrm{a}}·R_{{\mathrm{L}}_{\mathrm{k}}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}{a_{\mathrm{t}\mathrm{r}}·K_{\mathrm{b}}·V_{{\mathrm{d}\mathrm{c}}_{\mathrm{b}}}·{\mathbf{X}}_{{\mathrm{L}}_{\mathrm{k}}}\left(\mathrm{j}·{\omega }_{\mathrm{s}}\right)}}\right\}\end{array}\right.$$

(18)

From the steady-state variables defined in (18), the linearization process can be applied to obtain the small-signal model of the 4L-BC. The variables denoted with the symbol “^”, and the capital letters represent disturbances and steady-state operating points, respectively.

As a multivariable system, the linear model of the 4L-BC can be represented in state space form as follows:

$$\left\{\begin{array}{c}\dot{\mathbf{x}}=\mathbf{A}·\mathbf{x}+\mathbf{B}·\mathbf{u}\\ \mathbf{y}=\mathbf{C}·\mathbf{x}+\mathbf{D}·\mathbf{u}\end{array}\right.$$

(19)

where x is the state vector, u is the input vector, and y is the output vector, defined as:

$$\begin{gathered} \left\{\begin{array}{c}\mathbf{x}={\left[{\widehat{i}}_{\mathrm{d}},{\widehat{i}}_{\mathrm{q}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{a}}_1}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{a}}_2}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{a}}_3}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{b}}_1}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{b}}_2}},{\widehat{v}}_{{\mathrm{C}}_{{\mathrm{b}}_3}},{\widehat{i}}_{{\mathrm{B}}_1},{\widehat{i}}_{{\mathrm{B}}_2},{\widehat{i}}_{{\mathrm{B}}_3}\right]}^{\mathrm{T}}\\ \mathbf{u}={\left[{\widehat{E}}_{\mathrm{l}\mathrm{t}\mathrm{l}},{\widehat{v}}_{\mathrm{d}},{\widehat{v}}_{\mathrm{q}},{\widehat{v}}_{{\mathrm{B}}_1},{\widehat{v}}_{{\mathrm{B}}_2},{\widehat{v}}_{{\mathrm{B}}_3},{\widehat{i}}_2,{\widehat{i}}_{2_{\mathrm{a}}},{\widehat{i}}_3,{\widehat{i}}_{3_{\mathrm{a}}},{\widehat{i}}_{2_{\mathrm{b}}},{\widehat{i}}_{3_{\mathrm{b}}},\widehat{\varphi }\right]}^{\mathrm{T}}\end{array}\right. \\ \mathbf{x}=\mathbf{y} \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\mathrm{where} \{\mathbf{x}, \mathbf{y}\}\in \left\{{\mathbb{R}}^{11}\right\} \mathrm{and}\mathbf{u}\in \left\{{\mathbb{R}}^{13}\right\} \end{gathered}$$

(20)

Regarding the assumption x = y, it should be noted that in a state space such (19), x and y are related but not necessarily equivalent. In fact, x represents the state variables of the system, which describe the current state of the system. Instead, the output vector y represents the measurable or observable variables of the system [34,35,36].

The state (A), input (B), output (C), and direct transmission (D) matrices are defined as follows: $\mathbf{A}=\left[\begin{array}{cc}{\mathbf{A}}_{\mathbf{11}}& {\mathbf{A}}_{\mathbf{12}}\\ {\mathbf{A}}_{\mathbf{21}}& {\mathbf{A}}_{\mathbf{22}}\end{array}\right]$, $\mathbf{B}=\left[\begin{array}{cc}{\mathbf{B}}_{\mathbf{11}}& {\mathbf{B}}_{\mathbf{12}}\\ {\mathbf{A}}_{\mathbf{21}}& {\mathbf{A}}_{\mathbf{22}}\end{array}\right]$, C = I, and D = 0. Also, the submatrices A_jk and B_jk, where {j, k} ∈ {1, 2}, are defined in Appendix A. Symbolically, {A, C} ∈ $ℳ$_11×11 and {B, D} ∈ $ℳ$_11×13. Moreover, the submatrices of A can be defined as A₁₁ ∈ $ℳ$_6×6, A₁₂ ∈ $ℳ$_6×5, A₂₁ ∈ $ℳ$_6×6, and A₂₁ ∈ $ℳ$_6×6. The submatrices of B can also be defined as {B₁₁, B₂₁} ∈ $ℳ$_6×6, B₁₂ ∈ $ℳ$_6×7, and B₂₂ ∈ $ℳ$_5×7 (Appendix A). Finally, I and 0 are the identity and zero matrix, respectively.

Since the model presented in (19) is linear, and considering the aim of designing a control system for the 4L-BC using linear design techniques, the Laplace domain representation of the system model is obtained and shown as follows:

$$\left\{\begin{array}{c}{I}_{\mathrm{d}}\left(s\right)={\displaystyle \frac{1}{\left(s+K_1\right)}}·\left[K_2·I_{\mathrm{q}}\left(s\right)-K_3·\left(E_{\mathrm{l}\mathrm{t}\mathrm{l}}\left(s\right)-V_{\mathrm{d}}\left(s\right)\right)\right]\\ I_{\mathrm{q}}\left(s\right)={\displaystyle \frac{1}{\left(s+K_1\right)}}·\left[-K_2·I_{\mathrm{d}}\left(s\right)+K_3·V_{\mathrm{q}}\left(s\right)\right]\\ V_{{{\mathrm{C}}_{\mathrm{a}}}_i}\left(s\right)={\displaystyle \frac{1}{\left(s+K_6\right)}}·\left[-K_4·I_{\mathrm{d}}\left(s\right)-K_5·I_{\mathrm{q}}\left(s\right)+K_7·{\displaystyle \sum _{j\ne i}}{V}_{{{\mathrm{C}}_{\mathrm{a}}}_j}\left(s\right)+K_8·V_{{\mathrm{d}}_{{\mathrm{C}}_{\mathrm{b}}}}\left(s\right)-K_9·V_{\mathrm{d}}\left(s\right)+\right.\\ \left.+{\left(-1\right)}^i·K_{10}·\left(I_2\left(s\right)+I_{2_{\mathrm{a}}}\left(s\right)\right)+{\left(-1\right)}^{i+1}·K_{11}·\left(I_3\left(s\right)+I_{3_{\mathrm{a}}}\left(s\right)\right)-K_{12}·\varphi \left(s\right)\right]\\ \mathrm{for} \left\{i,j\right\}\in \{\mathrm{1,2},3\}\\ V_{{{\mathrm{C}}_{\mathrm{b}}}_i}\left(s\right)={\displaystyle \frac{1}{\left(s+K_{16}\right)}}·\left[K_{15}·V_{{\mathrm{d}}_{{\mathrm{C}}_{\mathrm{a}}}}\left(s\right)-K_{17}·{\displaystyle \sum _{j\ne i}}{V}_{{{\mathrm{C}}_{\mathrm{b}}}_j}\left(s\right)-K_{18}·I_{{\mathrm{B}}_i}\left(s\right)+{\left(-1\right)}^i·K_{19}·I_{2_{\mathrm{b}}}\left(s\right)\right.\\ \left.+{\left(-1\right)}^{i+1}·K_{20}·I_{3_{\mathrm{b}}}\left(s\right)+K_{21}·\varphi \left(s\right)\right]\\ \mathrm{for} \left\{i,j\right\}\in \{\mathrm{1,2},3\}\\ I_{{\mathrm{B}}_i}\left(s\right)={\displaystyle \frac{K_{24}}{\left(s+K_{25}\right)}}·\left\{V_{{{\mathrm{C}}_{\mathrm{b}}}_i}\left(s\right)-V_{{\mathrm{B}}_i}\left(s\right)\right\}\\ \mathrm{for} i\in \{\mathrm{1,2},3\}\end{array}\right.$$

(21)

assuming zero initial conditions, as outlined in [34,37]. This representation in the Laplace domain facilitates the analysis and design of the control system in the frequency domain. The K-constants in (21) are defined in Appendix A.

6. Control System and Modulation Algorithms

The complete control system for the 4L-BC is illustrated in Figure 6, with key control objectives including battery charging current regulation, a-side DC-link voltage regulation (total and individual capacitor balance), and grid power factor control [23,24,38]. The 4L-3P-NPC converter controller is responsible for managing the total a-side DC-link voltage (v_dca), controlling reactive power exchange with the grid (ensuring power factor correction), and balancing the a-side DC-link capacitor voltages (v_Ca1, v_Ca2, and v_Ca3) [27,28]. Meanwhile, the 4L-1P-DAB converter controller regulates the battery charging currents (i_B1, i_B2, and i_B3) and can also contribute to a-side DC-link capacitor voltage balancing [25,27]. This dual capability allows a-side DC-link voltage balancing to be achieved using the 4L-3P-NPC converter, the 4L-1P-DAB converter, or both simultaneously, as demonstrated in the three-level battery charger (3L-BC) [23,24]. This flexibility enables user customization based on specific performance and operational requirements.

The mathematical models describing the dynamic open-loop plants of the system are not covered exhaustively in this article. However, a detailed description of these models can be found in [38].

Modulation algorithms play a pivotal role in the operation of the proposed 4L-BC. For the 4L-3P-NPC converter, a virtual-vector pulsewidth modulation (VVPWM) strategy is employed, which enhances voltage balancing, reduces total harmonic distortion, and optimizes switching losses [28]. For the 4L-1P-DAB converter, a four-level extension of the modulation approach defined in [24] is utilized. This strategy involves dynamically adjusting the switching angles to create an optimized voltage waveform for both the primary and secondary sides of the HFT [25]. This modulation not only improves energy transfer efficiency but also ensures precise control over the charging currents of batteries with varying SoC.

By integrating these advanced modulation algorithms into the control architecture, the 4L-BC achieves superior performance in terms of efficiency, flexibility, and reliability.

6.1. 4L-3P-NPC Converter Control Description

In this 4L-BC, the voltage-oriented control system is similar to the 3L-BC [23,24,38], but with an additional voltage level. The control system scheme is shown in Figure 7a.

The total a-side DC-link voltage (v_dca) is regulated by a PI controller (v_dca-compensator), which provides the reference for the D-component of the grid current (i_d) regulated by another PI controller (i_d-compensator). The Q-component of the grid current (i_q) is regulated by a PI controller (i_q-compensator) to control the reactive power flow and maintain a unity power factor. The current controllers generate the v_d and v_q signals, which are then transformed into α-β variables to obtain the modulation index m = sqrt(v_α + v_β) and the reference angle θ = atan(v_β/v_α) through a calculation function block (calc. function).

For a-side DC-link voltage balancing, the a-side DC-link compensator (VBC_a1) is implemented (Figure 7b). Since the DC-link has three capacitors, there are two voltage unbalances to regulate, v_Caimb2 = v_Ca1 − v_Ca2 and v_Caimb3 = v_Ca2 − v_Ca3. The implementation includes two compensators, a-side DC-link compensators 2 and 3, which generate control signals (k₂ and k₃) to reduce the unbalances to zero.

The control system consists of five compensators, namely the two current compensators (i_d, i_q), the a-side DC-link total voltage compensator (v_dca), and the two voltage unbalance compensators (v_Caimb2 and v_Caimb3).

6.2. 4L-3P-NPC Converter Modulation

VVPWM is based on a set of space vectors in the space-vector diagram, called virtual vectors, which are defined as a linear combination of certain switching states [39]. Each virtual vector involves an average zero neutral-point current in every switching cycle. In this way, if the reference voltage vector is synthesized with these virtual vectors, the balance of the voltages of the DC-link capacitors will be guaranteed in each switching cycle [26,40]. This modulation is suitable for this four-level converter and can be implemented as follows:

$$\left\{\begin{array}{c}{mod}_{\mathrm{a}}\left(\theta \right)=\left({\displaystyle \frac{2}{\sqrt{3}}}\right)·m·\mathrm{c}\mathrm{o}\mathrm{s}\left(\theta \right)\\ {mod}_{\mathrm{b}}\left(\theta \right)=\left({\displaystyle \frac{2}{\sqrt{3}}}\right)·m·\mathrm{c}\mathrm{o}\mathrm{s}\left(\theta -{\displaystyle \frac{2·\mathsf{\pi }}{3}}\right)\\ {mod}_{\mathrm{c}}\left(\theta \right)=\left({\displaystyle \frac{2}{\sqrt{3}}}\right)·m·\mathrm{c}\mathrm{o}\mathrm{s}\left(\theta +{\displaystyle \frac{2·\mathsf{\pi }}{3}}\right)\end{array}\right.$$

(22)

$$\left\{\begin{array}{c}{mod}_{\mathrm{m}\mathrm{a}\mathrm{x}} \left(\theta \right)=\max \left[{mod}_{\mathrm{a}},{mod}_{\mathrm{b}},{mod}_{\mathrm{c}}\right]\\ {mod}_{\mathrm{m}\mathrm{i}\mathrm{n}} \left(\theta \right)=\min \left[{mod}_{\mathrm{a}},{mod}_{\mathrm{b}},{mod}_{\mathrm{c}}\right]\end{array}\right.$$

(23)

$$\left\{\begin{array}{c}{d}_{x_1}\left(\theta \right)={\displaystyle \frac{1}{2}}·\left({mod}_{\mathrm{m}\mathrm{a}\mathrm{x}}-{mod}_x\right)\\ d_{x_2}\left(\theta \right)=d_{x_3}\left(\theta \right)\\ d_{x_3}\left(\theta \right)={\displaystyle \frac{1}{2}}·\left(1-d_{x_1}\left(\theta \right)-d_{x_4}\left(\theta \right)\right)\\ d_{x_4}\left(\theta \right)= {\displaystyle \frac{1}{2}}·\left(d_{x_1}\left(\theta \right)-{mod}_{\mathrm{m}\mathrm{i}\mathrm{n}}\right)\end{array}\right.$$

(24)

$$\begin{gathered} m^{\prime }={\displaystyle \frac{m}{1+k_2·\frac{v_{{\mathrm{C}\mathrm{a}}_3}+v_{{\mathrm{C}\mathrm{a}}_2}-v_{{\mathrm{C}\mathrm{a}}_1}}{v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}+k_3·\frac{v_{{\mathrm{C}\mathrm{a}}_3}-v_{{\mathrm{C}\mathrm{a}}_2}-v_{{\mathrm{C}\mathrm{a}}_1}}{v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}}} \\ \Rightarrow r={\displaystyle \frac{m^{\prime }}{m}}={\displaystyle \frac{1}{1+k_2·\frac{v_{{\mathrm{C}\mathrm{a}}_3}+v_{{\mathrm{C}\mathrm{a}}_2}-v_{{\mathrm{C}\mathrm{a}}_1}}{v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}+k_3·\frac{v_{{\mathrm{C}\mathrm{a}}_3}-v_{{\mathrm{C}\mathrm{a}}_2}-v_{{\mathrm{C}\mathrm{a}}_1}}{v_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}}} \end{gathered}$$

(25)

$$\left\{\begin{array}{c}{d^{\prime }}_{x_1}\left(\theta \right)=d_{x_1}·\left(1-k_2-k_3\right)·r\\ {d^{\prime }}_{x_2}\left(\theta \right)=d_{x_2}·+k_2·\left(d_{x1}-d_{x_4}\right)\\ {d^{\prime }}_{x_3}\left(\theta \right)=d_{x_3}·+k_3·\left(d_{x1}-d_{x_4}\right)\\ {d^{\prime }}_{x_4}\left(\theta \right)=d_{x_4}·\left(1+k_2+k_3\right)·r\end{array}\right.$$

(26)

where x ∈ {a, b, c} [28].

In (24), the basic form of the leg duty ratios is calculated, without considering the control action determined by the closed-loop capacitor voltage balancing control. While the modulation strategy aims to achieve capacitor voltage balance in all operating conditions, non-idealities in the converter can still cause slight capacitor voltage unbalance.

Therefore, the closed-loop capacitor voltage balance control shown in Figure 7b becomes necessary. The closed-loop control in Figure 7b generates control parameters k₂ and k₃, which modify the values of the open-loop leg duty cycles given in (26). This modification is required to ensure proper capacitor voltage balancing in the presence of converter non-idealities.

The correction factor r defined in (25) is necessary to prevent the capacitor voltage balancing action from perturbing the intended m value when the DC-link capacitor voltages are different. It ensures that the voltage balancing control does not affect the desired m, maintaining converter performance and stability.

6.3. 4L-1P-DAB Converter Control Description

The control schemes for the 4L-1P-DAB are shown in Figure 7c–e [25,27]. The 4L-1P-DAB converter has the capability to regulate the imbalance of the voltages v_Ca1, v_Ca2, and v_Ca3 (VBC_a2) similar to the 3L-3P-NPC converter (VBC_a1) [23,24,38]. The control efforts u_a2 and u_a3 are produced to achieve a zero imbalance, i.e., v_Caimb2 = v_Ca1 − v_Ca2 and v_Caimb3 = v_Ca2 − v_Ca3, controlling the necessary switching angles α_axy where x ∈ {o, i} and y ∈ {1, 2, 3} [25].

In addition, the 4L-1P-DAB converter regulates the battery pack charging currents i_B1, i_B2, and i_B3 by controlling the differential-mode (DM) and common-mode (CM) components, i.e., i_DM2 = i_B1 − i_B2, i_DM3 = i_B2 − i_B3, and i_CM = (i_B1 + i_B2 + i_B3)/3 [27]. The control efforts u_b2 and u_b3 produce the necessary switching angles α_bxy, where x ∈ {o, i} and y ∈ {1, 2, 3}, for the proper operation of the modulator of the 4L-1P-DAB converter (Figure 7d).

Figure 7e shows the control diagram for i_CM control, where the power transfer of the 4L-1P-DAB converter is regulated by controlling the phase angle ϕ [27].

The control system associated with the 4L-1P-DAB converter is constituted by five PI compensators, the detailed development of which can be found in [38].

6.4. 4L-1P-DAB Converter Modulation

The switching strategy for this four-level converter, as shown in Figure 8, is based on modifying the switching angles to achieve a specific shape of the voltages on the primary and secondary sides of the HFT [25]. Figure 8 illustrates the waveforms of the voltages on the primary (v_aT) and secondary (v_bT) sides of the HFT, the voltage across inductance L_k (v_Lk), and the current flowing through the a-side of the HFT (i_aT). Moreover, this modulation strategy aims to build seven levels in the voltages v_aT and v_bT. The power transfer between the a- and b-side of the converter is regulated through the phase-shift angle ϕ and the switching angles α_zjk, where z ∈ {a, b}, j ∈ {i, o}, and k ∈ {1, 2, 3}.

It is worth mentioning that for z ∈ {a, b}, v_zT exhibits a predetermined switching state sequence as depicted in the top Figure 8.

The six switching angles per side (α_zi1, α_zi2, α_zi3, α_zo1, α_zo2, and α_zo3) plus the ϕ sum up 13 degrees-of-freedom available to control capacitor voltage balancing, converter performance, and power flow. If α_z1 = α_zo1 = α_zi1z, α_z2 = α_zo2 = α_zi2z, and α_z3 = α_zo3 = α_zi3z, and the DC-link capacitor voltages are balanced, then quarter-wave symmetry is guaranteed and even order harmonics are eliminated in v_aT, v_bT, v_Lk, and i_aT waveforms [25].

The operating principle of this modulation involves drawing or injecting current from the two neutral points of the a- and b-side DC-link (i_2z and i_3z, where z ∈ {a, b}) to balance the voltages v_Cax and v_Cbx, where x ∈ {1, 2, 3}. That is, v_Ca1 = v_Ca2 = v_Ca3 and v_Cb1 = v_Cb2 = v_Cb3 [25]. The currents i_2z and i_3z are defined as follows:

$$\left\{\begin{array}{c}{i}_{2_z}=-\left(s_{2_z{z}_{1\mathrm{T}}}-s_{2_z{z}_{2\mathrm{T}}}\right)·i_{z\mathrm{T}}\\ i_{3_z}=-\left(s_{3_z{z}_{1\mathrm{T}}}-s_{3_z{z}_{2\mathrm{T}}}\right)·i_{z_{\mathrm{T}}}\end{array}\right.$$

(27)

based on the switching model of the 4L-1P-DAB converter, i.e., Equation (4).

To maintain the balance of the a- and b-side DC-link voltages, the total charge injected into the neutral points in a switching cycle must be zero [25]. To simplify the analysis, it is convenient to consider only the fundamental component of i_zT, i.e., i_zT,1, as its amplitude is larger than the harmonic amplitudes and is the main contributor to i_2z and i_3z. Moreover, as shown in Figure 9, i_zT,1 can be decomposed into the in-phase and in-quadrature components with respect to v_zT,1 (the fundamental component of v_zT, where z ∈ {a, b}).

To study the dynamics of the charge injection at the neutral points, the effects of the fundamental component of i_zT, denoted as i_zT,1, are explored. As its amplitude is larger than the harmonic amplitudes, the effect of the harmonics on the capacitor voltages can be neglected. According to [22,25] and Figure 6 and Figure 7, i_zT,1 can be decoupled into a component in phase and a component in quadrature with v_zT,1 (fundamental component of v_zT), as mentioned before, denoted as i^p_zT,1 and i^q_zT,1, respectively. The voltage and current v_zT,1 and i_zT,1 are defined by [22,25]:

$$\left\{\begin{array}{c}{v}_{z\mathrm{T},1}=V_{z\mathrm{T},1}·\sin \left(\theta \right)\\ i_{\mathrm{z}\mathrm{T},1}=i_{z\mathrm{T},1}^{\mathrm{p}}+i_{z\mathrm{T},1}^{\mathrm{q}}=I_{z\mathrm{T},1}^{\mathrm{p}}·\sin \left(\theta \right)+I_{z\mathrm{T},1}^{\mathrm{q}}·\cos \left(\theta \right)\end{array}\right.$$

(28)

Also, Figure 9 plots the voltage v_zT and the currents i^p_zT,1 and i^q_zT,1 as a function of θ_z (the phase angle of v_zT,1). The green- and yellow-shaded areas represent the electric charges injected toward (positive sign) and drawn from (negative sign) the DC-link neutral points 2_z and 3_z, respectively. These charges are provided by the currents i^p_zT,1 and i^q_zT,1. To keep a preexisting capacitor voltage balance, the sum of the yellow areas must be zero and the sum of the green areas must also be zero. This is accomplished if the following is satisfied:

sin(α_z1) + sin(α_z3) − 2·sin(α_z2) = 0

(29)

However, even when (29) is satisfied, converter non-idealities may lead to non-zero average neutral-point currents causing capacitor voltage unbalances. Any voltage imbalance in v_Cax and v_Cbx, where x ∈ {1, 2, 3}, can be corrected by modifying switching angles α_zjk (where z ∈ {a, b}, j ∈ {i, o}, and k ∈ {1, 2, 3}) in order to inject or draw charge within a switching period. Note that this electric charge is only supplied by i^p_{z_HFT,1}, since the total charge injected by i^q_{z_HFT,1} is zero due to the odd symmetry of v_zT [25,40].

6.5. Control System Transfer Function

The system modeling is described in Section 3, Section 4 and Section 5. This modeling procedure resulted in the linear Equation (21) that describes the behavior of the system. Considering model (21) and the control system schemes described in the previous subsections, the control system transfer functions (TFs) that characterize the dynamics of the closed-loop system can be obtained. This section provides a theoretical analysis of these TFs.

As previously introduced, the 4L-BC is composed of a cascaded configuration integrating a 4L-3P-NPC and a 4L-1P-DAB. Each converter operates under a dedicated multiloop control framework designed to meet specific objectives such as DC-link voltage regulation, grid current tracking, voltage balancing, and controlled power flow. It is worth noting that the averaged and linearized models of the system obtained from the modeling procedure were used to tune the controllers. The explicit mathematical expressions of the TFs are detailed in Appendix A, and the controller design methodology used in this work is described in [38].

6.5.1. Voltage Regulation Loop—4L-3P-NPC

The outer voltage regulation loop of the 4L-3P-NPC converter governs the total a-side DC-link voltage, denoted as v_dca. The associated transfer function, representing the plant to be controlled, is given by:

$$G_{{\mathrm{v}}_{{\mathrm{d}\mathrm{c}}_{\mathrm{a}}}}\left(s\right)={\left.{\displaystyle \frac{V_{{\mathrm{d}}_{{\mathrm{C}}_{\mathrm{a}}}}\left(s\right)}{I_{\mathrm{d}}\left(s\right)}}\right|}_{Y\left(s\right)=0}$$

(30)

This TF (see Appendix A) describes the interactions between the AC-side grid current I_d, the DC-link capacitors C_a, resistive losses R_Ca, and the interconnection impedance ∣Z_k(j∙ω_s)∣ influenced by the DAB stage. It results in a high-order coupled system that includes both fast-switching and low-frequency dynamics. The pole-zero distribution of this TF is nontrivial, featuring multiple dominant poles associated with energy storage elements and parasitic resistances. This complexity requires careful controller design to achieve stability and bandwidth objectives.

6.5.2. DQ-Frame Current Regulation Loops

The inner loops of the 4L-3P-NPC converter regulate the d- and q-axis components of the grid current. These currents are crucial for enforcing grid-side power factor correction and establishing reference-tracking behavior. Both axes are governed by a shared second-order plant model, expressed as:

$$G_{\mathrm{d}}\left(s\right)=G_{\mathrm{q}}\left(s\right)=G_{\mathrm{d}\mathrm{q}}\left(s\right)={\displaystyle \frac{I_{\mathrm{d}}\left(s\right)}{V_{\mathrm{d}}\left(s\right)}}={\displaystyle \frac{I_{\mathrm{q}}\left(s\right)}{V_{\mathrm{q}}\left(s\right)}}$$

(31)

(refer to Appendix A). This TF encapsulates the behavior of the LC filter and its interaction with the grid impedance. The zero at s = −ξ∙ω_n enhances phase response, allowing for higher control bandwidth while maintaining a sufficiently large phase margin. The pole placement is linked to the natural frequency ω_n and damping ratio ξ, both of which are functions of R_ac and L_ac. These loops serve as the backbone for the voltage control loop, providing a fast dynamic response necessary to maintain tight regulation under transient disturbances.

6.5.3. A-Side DC-Link Voltage Balancing

The three a-side DC-link capacitors may exhibit voltage imbalances due to asymmetries in load or converter operation. Two dedicated loops are implemented to actively balance the voltages by controlling the imbalance terms:

$$\left\{\begin{array}{c}{v}_{{\mathrm{C}}_{{\mathrm{a}}_{{\mathrm{i}\mathrm{m}\mathrm{b}}_2}}}=v_{{\mathrm{C}}_{{\mathrm{a}}_1}}-0.5·\left(v_{{\mathrm{C}}_{{\mathrm{a}}_2}}+v_{{\mathrm{C}}_{{\mathrm{a}}_3}}\right)\\ v_{{\mathrm{C}}_{{\mathrm{a}}_{{\mathrm{i}\mathrm{m}\mathrm{b}}_3}}}=0.5·\left(v_{{\mathrm{C}}_{{\mathrm{a}}_1}}+v_{{\mathrm{C}}_{{\mathrm{a}}_2}}\right)-v_{{\mathrm{C}}_{{\mathrm{a}}_3}}\end{array}\right.$$

(32)

The corresponding plant dynamics are governed by first-order TFs:

$$G_{{\mathrm{C}}_{{\mathrm{a}}_{{\mathrm{i}\mathrm{m}\mathrm{b}}_k}}}\left(s\right)={\displaystyle \frac{V_{{\mathrm{C}}_{{\mathrm{a}}_{{\mathrm{i}\mathrm{m}\mathrm{b}}_k}}}\left(s\right)}{I_k\left(s\right)}}$$

(33)

where k ∈ {2, 3} (see Appendix A). These functions reflect the RC-like dynamics of charge balancing among the capacitor banks. Dominant poles are determined by the product R_Ca∙C_a, and the system is inherently stable. However, due to their low-pass nature, these loops must be carefully compensated to prevent slow behavior or excessive control action during large transients [41].

6.5.4. Differential-Mode Current Control—4L-1P-DAB

The DM current control loops are designed to regulate the charging current imbalance across the individual battery packs. These loops act on the differential currents:

$$\left\{\begin{array}{c}{i}_{{\mathrm{D}\mathrm{M}}_2}=i_{{\mathrm{B}}_1}-i_{{\mathrm{B}}_2}\\ i_{{\mathrm{D}\mathrm{M}}_3}=i_{{\mathrm{B}}_2}-i_{{\mathrm{B}}_3}\end{array}\right.$$

(34)

The associated plant TFs are modeled as second-order systems:

$$G_{{\mathrm{C}}_{{\mathrm{i}\mathrm{m}\mathrm{b}}_k}}\left(s\right)={\displaystyle \frac{I_{{\mathrm{D}\mathrm{M}}_k}\left(s\right)}{I_{k_{\mathrm{b}}}\left(s\right)}}$$

(35)

where k ∈ {2, 3} (see Appendix A). These TFs include poles determined by the coupled dynamics of the DAB converter modulation index, interlink inductance L_k, and battery pack voltages. Resonant behavior may arise depending on pole locations, and loop gain compensation must account for potential peaking in frequency response.

6.5.5. Common-Mode Current Control and Power Transfer

The net power transfer from the AC-side grid to the battery bank is controlled through the regulation of the common-mode current component defined by:

$$i_{\mathrm{C}\mathrm{M}}={\displaystyle \frac{1}{3}}·{\sum }_{j=1}^3{i}_{{\mathrm{B}}_j}$$

(36)

The plant TF associated with this loop is modeled as shown as follows:

$$G_{\mathsf{\varphi }}\left(s\right)={\displaystyle \frac{I_{\mathrm{C}\mathrm{M}}\left(s\right)}{\varphi \left(s\right)}}$$

(37)

which is defined in Appendix A.

The presence of a right-half-plane zero at s = −ω_z introduces a non-minimum phase characteristic, imposing a theoretical upper limit on control bandwidth. The cubic denominator includes dominant low-frequency poles resulting from interactions between converter inductance, DC-link dynamics, and modulation phase angle ϕ. The sensitivity of this loop to parameter variations and input disturbances requires conservative tuning strategies, especially in systems where rapid power fluctuations may occur.

7. Simulation Results

7.1. Specifications, Scenarios, and Cases Definition

Simulations were carried out with the model shown in Figure 1, using MATLAB/Simulink, version R2019b. The 4L-BC was connected to a three-phase AC grid with E_{ltl_ss} = 400 Vrms line-to-line and f = 50 Hz. Both converters in the 4L-BC operated with a switching frequency f_s = 10 kHz.

The converter parameter values are listed in

Table 1. Converter parameters values [24].

Parameters	Values
Rac	10 [mΩ]
Lac	1 [mH]
RCa = RCb	10 [kΩ]
Cb	800 [μF]
Lk	25 [μH]
Lm	10 [H]
RLk	50 [mΩ]
atr	1
Rdc	20 [mΩ]
Ldc	1 [mH]
f	50 [Hz]
fs	10 [kHz]

. The initial a-side DC-link capacitor voltages are v_Ca10 = 280 V, v_Ca20 = 420 V, and v_Ca30 = 700 V; i.e., the system starts with the a-side DC-link with its voltages imbalanced. The a-side DC-link voltage reference is set at v^*_dca = 1.4 kV. The initial voltages of the b-side DC-link capacitors v_Cb10, v_Cb20, and v_Cb30 are imposed by the voltages of each battery pack v_B1, v_B2, and v_B3. Charging current references i^*_B1, i^*_B2, and i^*_B3 are set to 100 A. The switching angles are initially defined as follows: α_z1 = 10°, α_z2 = 35.4°, and α_z3 = 80°, where z ∈ {a, b}, which are consistent with (29) and thus force i^p_zT,1 to deliver a zero charge to the inner DC-link points [22,25].

Four different scenarios are generated for this 4L-BC according to four different capacitance ratings of the a-side DC-link capacitors, as shown in

Table 2. Definition of studied scenarios depending on the a-side DC-link capacitor value C_a.

Parameter	Scenario 1	Scenario 2	Scenario 3	Scenario 4
Ca	300 [μF]	600 [μF]	800 [μF]	1100 [μF]

.

Similarly to the analysis for the 3L-BC case performed in [24], the characteristics and performance under each scenario are studied in the same three cases that were defined in the 3L-BC. As shown in

Table 3. Definition of studied cases depending on the converter in charge of balancing the a-side DC-link.

Case	Converter
1	only 4L-3P-NPC
2	only 4L-1P-DAB
3	both 4L-3P-NPC and 4L-1P-DAB

, these cases are defined depending on the converters in charge of balancing the a-side DC-link, that is, to keep v_Ca1, v_Ca2, and v_Ca3 balanced.

7.2. System Stability Analysis

As detailed in previous sections, the linear model of the system was used to tune the controllers described in Section 6, as documented in [38]. A detailed frequency-domain stability analysis was carried out for all closed-loop systems in the 4L-BC architecture. Each control loop—covering DC-link voltage, DQ-frame current, voltage balancing, DM, and CM components—was subjected to classical loop-gain analysis using Bode plot evaluation and root locus inspection. As described in [38], the crossover frequency of each compensated open-loop transfer function was tuned to match the converter switching frequency f_s = 10 kHz, ensuring minimal phase lag, high disturbance rejection, and fast transient response.

Figure 10a shows that the uncompensated open-loop gain T_vdcau(s) of the 4L-3P-NPC converter outer voltage loop lacks a crossover near f_s. However, after compensator insertion, the resulting loop gain T_vdca(s) exhibits a crossover precisely at f_s with a substantial phase margin of 270°, confirming stability and responsiveness. The corresponding root locus diagram in Figure 10b reveals all poles confined to the left-half complex plane, further validating system stability.

Similarly, the DQ-frame current controllers—governing G_dq(s)—show uncompensated crossover points at 30 Hz and 102 Hz (Figure 11a, blue). After compensation, the gain crossover shifts toward f_s, with a phase margin of 86° (Figure 11a, red). The root locus plot in Figure 11b confirms left-half-plane pole placement, affirming robust current control.

The voltage balancing loops C_VBCa12(s) and C_VBCa13(s), governing imbalances v_Caimb2 and v_Caimb3, also exhibit crossover frequencies at f_s with phase margins exceeding 270°, as seen in Figure 12a,b. This implies the excellent dynamic suppression of capacitor voltage

On the 4L-1P-DAB side, Figure 13 and Figure 14 reveal that the DM current controllers, T_iDM2(s) and T_iDM3(s), are very stable, exceeding 360° of phase margin. This high phase margin is attributed to the inherent second-order plant dynamics and well-tuned compensators.

Finally, the most demanding control loop—the common-mode current controller regulating i_CM through phase angle ϕ—is analyzed in Figure 15. Despite the non-minimum phase behavior of G_ϕ(s), the compensated loop T_ϕ(s) achieves a robust phase margin of 258°, with root locus analysis verifying strict left-half-plane pole locations.

In conclusion, all control loops within the 4L-BC system—whether linear or nonlinear, single-input or multiple-input multiple-output—are well compensated, phase-stable, and dynamically resilient. These results validate the theoretical modeling presented in Section 6.5 and demonstrate the practical effectiveness of the control architecture under both steady-state and dynamic operating conditions.

7.3. Time-Domain Simulation Results

In this subsection, the time-domain simulation results are presented for the proposed simulation scenarios and cases.

Figure 16, Figure 17, Figure 18 and Figure 19 depict the value of voltages v_Ca1, v_Ca2, and v_Ca3, leg “a” duty ratios d_a1, d_a2, d_a3, and d_a4, and switching angles corresponding to side a, i.e., α_ajk where j ∈ {i, o} and k ∈ {1, 2, 3}, with the system in steady-state operation, for scenarios 1 to 4, respectively. Figure 16a–c, Figure 17a–c, Figure 18a–c, 19a–c correspond to cases 1 to 3, respectively. Additionally, Figure 16d, Figure 17d, Figure 18d, Figure 19d shows the dynamics of the voltages v_Ca1, v_Ca2, and v_Ca3 in the absence of balance control of these voltages.

It is worth highlighting that the a-side DC-link voltage balance is essential for proper system operation. The first row in Figure 16, Figure 17, Figure 18 and Figure 19 shows balanced a-side DC-link voltages in all conditions. To demonstrate the effectiveness of the balance control loop, the simulations in Figure 16d, Figure 17d, Figure 18d, Figure 19d were carried out with this control deactivated. Without balance control, the a-side DC-link voltages become unbalanced and reach unsafe values, which necessarily leads to a system shutdown to avoid system damage. It should be noted that the negative DC-link voltages shown in the simulation results would not be possible in a real system, since they will be clamped at zero by the converter diodes. Overall, it is obvious that the voltage balancing control loop is essential.

Under proper balanced operation, the high-frequency ripple observed in v_Ca1, v_Ca2, and v_Ca3 (first row in Figure 16, Figure 17, Figure 18 and Figure 19) decreases with increasing capacitance from scenario 1 to 4, reflecting the filtering characteristics of the DC-link. In high-performance charging systems, a ripple threshold of 1.5% is typically enforced, guiding the DC-link capacitor design for both energy storage and dynamic filtering.

A figure of merit (FoM) related to the values of the percentage of ripple in the DC-link voltages (rr_vca1, rr_vca2, and rr_vca3) are calculated and summarized in

Table 4. Percentage of ripple in the a-side DC-link voltages (rr_vCa1, rr_vCa2, and rr_vCa3).

Scenarios	rrvCa1, rrvCa2, and rrvCa3 in [%]	Cases
		1	2	3
1	rrvCa1	3.77	1.90	3.89
	rrvCa2	0.75	0.65	0.83
	rrvCa3	3.36	1.97	3.30
2	rrvCa1	1.87	1.65	1.65
	rrvCa2	0.47	0.24	0.30
	rrvCa3	1.70	1.58	1.67
3	rrvCa1	1.43	1.37	1.28
	rrvCa2	0.26	0.23	0.26
	rrvCa3	1.28	1.45	1.48
4	rrvCa1	1.00	0.86	1.03
	rrvCa2	0.21	0.21	0.21
	rrvCa3	0.88	0.90	0.90

. Figure 16, Figure 17, Figure 18 and Figure 19 confirm that this requirement is not satisfied in scenario 1 except for v_Ca2 in case 2, as detailed in Table 4. The ripple performance improves substantially in scenarios 3 and 4, meeting specifications across all cases. The peak ripple is observed in rr_vCa1 for scenario 1, case 3, whereas the lowest ripple appears in rr_vCa2 for scenario 4.

The duty ratios of the AC-DC converter legs do not reach saturation under any scenario or case, preserving control margin and suggesting that DC-link capacitance could potentially be reduced without compromising dynamic controllability.

From Figure 16a, Figure 17a, Figure 18a, Figure 19a (case 1 in all scenarios), it is observed that the switching angles are kept constant around their reference values, i.e., α_a1 = 10°, α_a2 = 35.4°, and α_a3 = 80°, which is consistent, since in this case, the 4L-1P-DAB controllers are not responsible for regulating the balance of the a-side DC-link voltages, and therefore, these controllers are not generating any control effort. Additionally, it should be noted that the angles values were calculated in accordance with [25] to guarantee that the currents flowing through the internal points of the a-side DC-link as seen from the 4L-1P-DAB converter, i.e., i_2a and i_3a, provide a null electrical charge. However, in cases 2 and 3 of all scenarios (see Figure 16b,c, Figure 17b,c, Figure 18b,c, Figure 19b,c), one can see the control efforts produced by the controllers, which is convincing since, in these cases, the 4L-1P-DAB converter is in charge of regulating the balance of the a-side DC-link voltages. It is evident from Figure 16b, Figure 17b, Figure 18b, Figure 19b that the angles α_amn, where m ∈ {i, o} and n ∈ {1, 2, 3}, approach their α_an reference values. Thus, the 4L-1P-DAB converter can operate with the balanced voltages of the a-side DC-link capacitors. Moreover, it can be seen that the α_amn dynamics present variations with respect to their reference values, with the largest one seen in α_am1 and α_am3. Also, the angle α_a3 saturates at 90°. The 4L-1P-DAB converter has the same control margin and can eventually enable a reduction in the capacity of the a-side DC-link. Finally, the control efforts generated by the 4L-1P-DAB converter when the system operates in cases 2 and 3 are greater as the capacity of the a-side DC-link decreases.

It should be noted that during the execution of the 4L-BC case studies, the tuning parameters of the compensators related to the balancing of the a-side DC-link voltages, as well as those related to the regulation of the CM and DM components, were not modified, which means that the developed tuning process was performed satisfactorily.

Figure 20 shows the dynamics under step changes in the charging currents (i_Bx, x ∈ {1, 2, 3}) in case 3, for all scenarios. Figure 20a–d relate to scenarios 1–4, respectively.

At start-up, the reference currents (i^*_B1, i^*_B2, and i^*_B3) are set to 100 A. At 160 ms, i^*_B1 takes the value of 110 A and the other currents remain at their initial reference values. Subsequently, at 300 ms, i^*_B2 takes the value of 95 A whereas i_B1 and i_B3 are maintained at 110 A and 100 A, respectively. Then, at 400 ms, i^*_B3 is set to 90 A and i_B1 and i_B2 are maintained at 110 A and 95 A, respectively. Finally, at 500 ms, 600 ms, and 700 ms, the currents i^*_B1, i^*_B2, and i^*_B3 return to their initial reference values, i.e., 100 A, respectively. From Figure 20, it can be seen that the maximum start-up overshoot for each scenario is approximately equal to 7.5%, which represents a relatively low value. In addition, two other FoMs are defined, i.e., the overshoot and settling time. On the other hand, a second constraint was imposed on the system and it is related to the maximum percentage overshoot allowed, which is set to 10%, a typical value in the literature [34,35,37].

The FoMs related to i_Bx are summarized in

Table 5. Summary of overshoots and settling times in step changes in charging currents.

Step Change Time [ms]	Step Change Current	FoM	Scenarios
			1	2	3
160	i*B1	Overshoot [%]	3.46	3.33	3.02
		Settling time [ms]	91.50	97.74	97.82
300	i*B2	Overshoot [%]	0.77	0.76	0.78
		Settling time [ms]	85.12	85.25	85.32
400	i*B3	Overshoot [%]	1.28	1.11	0.95
		Settling time [ms]	81.35	81.32	81.57
500	i*B1	Overshoot [%]	0.69	0.72	0.76
		Settling time [ms]	52.71	52.63	55.66
600	i*B2	Overshoot [%]	1.75	1.65	1.23
		Settling time [ms]	60.75	60.83	60.81
700	i*B3	Overshoot [%]	1.69	1.61	1.17

according to Figure 20. Table 5, derived from Figure 20, succinctly presents the FoMs pertaining to i_Bx (where x ∈ {1, 2, 3}).

A comprehensive analysis of the results in Table 5 reveals patterns in the maximum and minimum values of overshoots and settling times. With respect to the step change time and i_Bx reference, the maximum values are as follows: 3.46% (scenario 1), 0.79% (scenario 4), 1.28% (scenario 1), 0.77% (scenario 4), 1.75% (scenario 1), and 1.92% (scenario 4), and 97.82 ms (scenario 3), 85.32 ms (scenario 3), 81.68 ms (scenario 4), 55.66 ms (scenario 3), 60.83 ms (scenario 2), and 72.27 ms (scenario 4) for step change times of 160 ms, 300 ms, 400 ms, 400 ms, 500 ms, 600 ms, and 700 ms, respectively.

Conversely, the minimum values for overshoots and settling times, also in relation to the step change time and i_Bx reference, are 2.84% (scenario 4), 0.76% (scenario 2), 0.94% (scenario 4), 0.69% (scenario 1), 1.01% (scenario 4), and 1.17% (scenario 3), and 91.50 ms (scenario 1), 85.12 ms (scenario 1), 81.32 ms (scenario 2), 52.63 ms (scenario 2), 60.58 ms (scenario 4), and 72.13 ms (scenario 1) for step change times of 160 ms, 300 ms, 400 ms, 400 ms, 500 ms, 600 ms, and 700 ms, respectively.

Upon careful examination of the maximum and minimum results, organized by step change time and i_Bx, it is evident that the highest values for overshoots and settling times across all scenarios are 3.46% (scenario 1, step change @ 160 ms) and 97.82 ms (scenario 3, step change @ 160 ms), respectively. Conversely, the lowest values are 0.69% (scenario 1, step change @ 500 ms) and 52.63 ms (scenario 2, step change @ 500 ms). In summary, the 4L-BC demonstrates effective controllability of i_Bx in all scenarios, characterized by favorable FoMs and negligible steady-state errors.

8. Conclusions

This work constitutes proof-of-concept of a novel four-level battery charger based on an extended dual-active-bridge converter topology, which has not been previously studied in the literature. This multibattery charging system is based on a hybrid multilevel topology by combining a four-level three-phase neutral-point-clamped (4L-3P-NPC) AC-DC converter and a four-level single-phase dual-active-bridge (4L-1P-DAB) DC-DC converter.

A comprehensive analytical model was developed, including the switching-level representation, large-signal averaged models in time and D–Q domains, and a small-signal linear state-space model. These models accurately describe the system dynamics—including DC-link voltage regulation, multibattery current control, power transfer, and capacitor voltage balancing—and enable classical control design and frequency-domain stability analysis using gain/phase margin criteria.

The proposed multiloop control system fulfills three primary objectives: (i) the regulation of the total a-side DC-link voltage and reactive power control via the 4L-3P-NPC stage, (ii) the precise control of individual battery pack charging/discharging currents via the 4L-1P-DAB stage, and (iii) active voltage balancing across the a-side and b-side DC-link capacitors. Modulation strategies include virtual-vector PWM (VVPWM) for the NPC stage and a multilevel angle-based strategy for the DAB stage, both contributing to enhanced harmonic performance and DC-link capacitor voltage balancing.

The proposed system was successfully validated by simulation with MATLAB/Simulink. The stability analysis of the compensated control loops confirms gain and phase margins well above design thresholds across all control domains. Time-domain simulations validate the proposed system under a wide range of capacitance scenarios and dynamic loading conditions. The results confirm fast transient response (settling times < 100 ms), low overshoot (<3.5%), high disturbance rejection, negligible steady-state error, and efficient ripple suppression, with ripple percentages below 1.5% in most cases. Furthermore, tuning parameters remained fixed across all tested conditions, evidencing the robustness and generalizability of the control strategy.

A key advantage of the proposed architecture lies in its modularity and scalability. The system is naturally extendable to more battery packs or higher DC-link voltage levels configurations without requiring significant structural changes.

The advantages of multilevel converters in comparison to conventional two-level converters are well known and will not be detailed here. However, they require DC-link capacitor voltage balance to guarantee correct operation. In the proposed system, DC-link capacitor voltage balance is achieved by means of a dual control strategy, in which both the 4L-3P-NPC and 4L-1P-DAB converters are responsible for balancing the a-side DC-link.

From the point of view of the battery, the four-level converter enables the use of a battery bank consisting of three battery packs connected in series. The simulation results show that the proposed control approach allows the current of each battery pack to be controlled. This feature is very interesting, as it allows the state-of-charge of the battery packs to be balanced and enables the use of battery packs with different charge levels. Moreover, it is feasible to work with battery packs that have different loading or varying degrees of aging, are built with different chemistries, and even combine new and second-life battery packs, thus maximizing the available capacity of the battery bank.

Future work will focus on the experimental validation of the proposed 4L-BC system, including hardware-in-the-loop testing and full-scale prototype development. Further experimental analyses, for instance, the analysis of the power losses, system overall efficiency, power loss distribution, or power quality, among others, will be useful to quantify the benefits of the proposed battery charger compared to current chargers.

Finally, it should be noted that the proposed battery charger combines the advantages provided by multilevel converters, the flexible and compact behavior of the dual-active-bridge converter, and customized battery pack charging. These advantages make the proposed system a suitable, feasible, and promising option for implementing battery chargers, in applications such as heavy-duty electric vehicles, second-life battery repurposing, stationary storage, and vehicle-to-everything (V2X) scenarios.