An Innovative Digital Pulse Width Modulator and Its Field-Programmable Gate Array Implementation
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe overall quality of the paper is acceptable.
My recommendation is to add the points at the end of section I, the main contribution of your work, and the significance of the proposed method in the present scenario.
My recommendation is to improve the impact and novelty of the research, add results of the methods that are considered in the literature [14–16, 21, 22], and compare them with the proposed model experimentally on FPGA.
The manuscript may not be considered for publication in its present form as it requires revision.
The paper is acceptable enough and technically sound. I provided some comments. The current form might not meet the acceptance criteria.
Comments on the Quality of English LanguageThe English language looks good; however, I am not the person to judge its nuances and complexities.
Author Response
Dear Reviewer,
Thanks for the in-depth reading and your valuable feedback.
In the following, I address your comments point-by-point.
(In blue I reported your feedback, in black my response.)
General Comments
The overall quality of the paper is acceptable.
Thanks, once again for your valuable feedback.
Comment 1
My recommendation is to add the points at the end of section I, the main contribution of your work, and the significance of the proposed method in the present scenario.
Thanks for this suggestion. The revised manuscript contains a list of the main contributions and the significance of this work in the considered scenario at the end of section 1.
Comment 2
My recommendation is to improve the impact and novelty of the research, add results of the methods that are considered in the literature [14–16, 21, 22], and compare them with the proposed model experimentally on FPGA.
Thanks to point it out. The work in [21] and [22] relate to analog PWM. For this reason a comparison with an FPGA implementation is not feasible. The work in [15] refers to a multi-sampling ADE-DPWM when the number of samples per period, N, is greater than 2. In the case of double-sampling (N = 2) the work proposed in [15] collapse to the model proposed in [16]. Since the double-sampling models in [16] only recovers the phase delay introduced by the modulator itself and no derivative actions are possible, a fair comparison with the proposed eDPWM is not possible.
The only possible comparison is therefore with the double-sampling ADE-DPWM proposed in [14].
Please note that in the revised manuscript four papers are added in the introduction. Thus the references are update as follows [14 ->18], [15 ->19] etc.
The author proved that the analytical model of the architecture in [14] and the one of the eDPWM are exactly the same (see section 4). Therefore, if both architectures are implemented properly on FPGAs, there is no reason why they should give different results. Especially, the system clock of the FPGA is 400Mhz (this value is derived with the system PLL from the fundamental clock at 50MHz) and that of the modulator is only 20kHz. Given the large frequency separation, the latencies of additional products cannot be captured with the experimental procedure adopted. In other words, if you have enough resources, the two architectures, which are equivalent on paper will also be equivalent experimentally.
To show this, an experimental test was done with a few points to show the total equivalence between the two architectures even experimentally. This test is attached in this letter but will not be added to the final manuscript since it does not add anything to what is reported. Instead, the discussion of this response, it is included in the paper to prevent the same legitimate doubts from arising in the reader (see the discussion section at the end of section 5). I believe that this feedback has been very helpful in prompting me to look more closely to an issue that from my point of view, having worked on this architecture for years, is trivial but actually deserves to be investigated properly.
Comment 3
The manuscript may not be considered for publication in its present form as it requires revision.
The paper is acceptable enough and technically sound. I provided some comments. The current form might not meet the acceptance criteria.
The paper is revised taking into account feedback from reviewers. My responses to the due comments went in the direction of always implementing the requested changes, including reworking the text to avoid ambiguous expressions or parts. I trust that the new form can meet the reviewers' criteria.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for AuthorsThis work has depth and proves their proposed research idea with valid and exhaustive theoretical derivations which are interesting and impressive. I therefore proposed minor revision and could be accepted if authors can provide satisfactory replies to my comments in attached pdf.
Comments for author File: Comments.pdf
Author Response
Warning. The file provided did not allow me copying and pasting the text. I am only responding by quoting the various parts.
I thank the reviewer for the thorough and detailed reading and his valuable feedback. In the following my answers to the reviewer's comment.
Res. to the General comment
Thank you for reading and the encouragement given. The feedback received will allow me to improve the readability of the article.
Res to Comment 1
A detailed discussion section was provided at the end of the section on experimental results. This is in line with other suggestions from other reviewers. Thank you once again for helping me to improve the quality of the article.
Res to Comment 2
Mathematically, the modulator delay is recovered by eliminating the presence of the "synch function" that cause a drop around the Nyquist frequency. The phase gain for $a=b>1$, on the other hand, is obtained by an additional derivative action. In practice, the phase delay is recovered by the fact that the operating frequency during transients is no longer fs but the inverse of the period obtained as the lowest common multiple between Ts = 1/fs and Tk = 1/fk. Where fs and fk are the PWM modulation frequency and the perturbation frequency, respectively.
This is proved rigorously for modulators with the same time response as in [18,19,20]. Given the equivalence of the model in the time domain, the frequency model must be the same. This is clearly stated in the submitted manuscript. The only analysis technique that can formally prove this is based on the use of descriptive functions approach. Details have already been published and can be found in [18].
Res to Comment 3
The discussion section addresses this issue. Thanks again for the advice.
Res to Comment 4
The paper proves that the time domain model of the proposed eDPWM architecture is the same as that of the ADE-DPWM architecture. When deriving the small-signal model with the use of descriptive functions, only the time domain model is used. In other words, if the time domain returns the same equations, the small-signal model must be the same. Since the mathematical model does not consider how the equations were obtained in the time domain but only their form.
The transition from the time domain model to the frequency domain model was rigorously reported in [18] and will not be reported again here. The paper [18] is attached. Instead, the link between a and b and the derivative action can also be easily understood logically, without looking at the small-signal model. In fact, in the eDPWM model, see Figure 5(a), the part in light blue is exactly a discrete derivative without any manipulation. In the ADE-DPWM architectures this action is hidden in the architecture, in the eDPWM version this action is explicitly present. The coefficient a and b are simply the weights of the discrete derivative
Res to Comment 5
Figure 7 explains how the trigger signal generated through the intersection of the two carriers allows the average current in a buck to be sampled. This signal is not present in ADE architectures and therefore must be generated, further increasing the complexity of the system. Section 3.2 has been revised to better highlight this aspect.
Res to Comment 6
This aspect is analyzed in the revised manuscript in the "Discussion" section before the conclusions. Thank you again for suggesting to include this part and for helping me in writing its content.
Res to Comment 7
The number of references is increased. The one suggested by the reviewer is also added.
Res to Comment 8
The purpose of this work is proving the equivalence between the simpler eDPWM and the complex ADE-DPWM in [18].
The overall description is provided near to the block diagram of the ADE-DPWM. In the Discussion section one critical aspect is detailed. The scope of the paper is not a deep comparison between FPGA implementations (that can be always improved and modified) but to prove the equivalence between two different architectures, regardless the specific implementation. The provided architecture is much more simpler that the ADE-DPWM in [18]. This can be easily observed from the comparison in Figure 5. The metrics of evaluation can be chosen by the author. Numbers can be interpreted, the basic implementation on the block diagram cannot be interpreted as per convenience.
Res to Comment 9
Section 4 proves that the time domain description of the proposed eDPWM is the same as the one proposed in [18]. To calculate the small signal model you only use the time description. Regardless if this require hundred of complex block in an eventually FPGA implementation. Thus the equivalence of the time domain description proves itself the equivalence in the frequency domain.
Res to Comment 10
Once again (see Res to Comment 5) the figure 7 and the relative Section 3.2 detail how the mechanism is implemented and why this is important. The text of the section is partially rewritten to avoid ambiguity and improving understanding on this issue.
Thank you once again for your suggestions and careful reading. I am sure the feedback provided helped me to improve the quality of the paper.
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsI have thoroughly read the manuscript, procedures, and all the details provided. The author has stated:
"Data Availability Statement: I will share the entire MATLAB code and the Simulink implementation of the final eDPWM V2.0 architecture when/if the paper is accepted."
While this is a positive statement, I suggest that, given the limited availability of public data for training FPGA/ASIC designs, the author consider publishing all VHDL code and FPGA implementation details as well.
Doing so would significantly enhance the manuscript’s impact and contribute to increased citations.
Some minor comments:
1-If possible, discuss real-world FPGA resource utilization or compare with commercial implementations (Kind of Comparative benchmark)
2-If feasible, include a table summarizing FPGA resource usage (For example, DSPs, LUTs, FFs, etc)
3-ADC Latency is a little bit more elaborated.
Author Response
Dear Reviewer,
Thanks for the careful reading and your valuable feedback.
In the following, I'll try to examine and respond to your comments point-by-point.
(In blue I reported your feedback, in black my response.)
General Considerations
I have thoroughly read the manuscript, procedures, and all the details provided. The author has stated:
"Data Availability Statement: I will share the entire MATLAB code and the Simulink implementation of the final eDPWM V2.0 architecture when/if the paper is accepted."
While this is a positive statement, I suggest that, given the limited availability of public data for training FPGA/ASIC designs, the author consider publishing all VHDL code and FPGA implementation details as well.
I deeply think about that aspect. The problem is the following. I am the person who elaborate on the first digital pulse-width modulator (DPWM) based on the asymmetric dual-edge carrier capable of recovering the phase delay intrinsically introduced in conventional DPWM. There, I was involved with a company (I do not want to mention its name here, but you can check the affiliation of the authors). So I started to work on this topic because of this project.
Although the architecture proposed in this article is totally original and entirely developed by me, I do not want to explicitly share the VHDL code because it may be seen as the result of much later elaboration than that developed for the initial project. Also if the architecture is completely different.
Comment 1-If possible, discuss real-world FPGA resource utilization or compare with commercial implementations (Kind of Comparative benchmark).
Currently, there are no commercial products, available on the market, that offer modulators like the ones I developed. A comparison would also have been useful to show the strength of the developed model. But at the moment I am pioneering this technology.
Comment 2 -If feasible, include a table summarizing FPGA resource usage (For example, DSPs, LUTs, FFs, etc).
No DSPs and LUTs are used and required for this architecture.
You need just two counters and some shift registers. The story is slightly different if you want to implement the synchronization mechanism. At that point, it depends on the speed you need to reach the synchronism. Please consider that increasing the synch speed will reduce the derivative action. For this reason, I avoided to include such a list.
Since I do not have specific targets, I struggle to give general indications of the complexity of synchronism. This topic is also covered in publications done on the ADE modulator in the multi-sampling version.
Comment 3 -ADC Latency is a little bit more elaborated.
Regarding these three points, I have changed some parts of the text from the original version to share as much information as possible. I hope that the incremental changes find feedback and are in line with the reviewer's directions.
Thank you again for the valuable feedback, it will also help me to direct further work.
