High-Reliability Wireless Pressure Measurement System Based on FEC Algorithm

Abstract

As the core of an aircraft’s power system, the stability and reliability of an aero-engine’s performance are crucial to flight safety. Addressing the issues of complex wiring and poor flexibility in traditional wired testing systems, this paper designs and implements a wireless transmission aero-engine pressure measurement system based on FPGA. By integrating front-end memory and a back-end test bench and utilizing LoRa wireless communication technology and the Reed–Solomon (RS) forward error correction (FEC) algorithm, the system significantly enhances the reliability and anti-interference capability of data transmission. Test results demonstrate that the system can monitor and record engine pressure parameters in real time in complex environments, with a notable reduction in bit error rate and packet loss rate, especially under strong interference conditions. This system resolves wiring challenges, enhances the real-time performance of monitoring links and the stability of data storage, and is characterized by high precision, high reliability, and automation. It is suitable for complex and harsh working environments and has broad application prospects in the aviation and military sectors.

1. Introduction

Aero-engines have extremely high requirements in terms of structural design, materials, manufacturing processes, and testing. They play a crucial role in aircraft flight. Whether an aero-engine can operate properly directly affects the stability, reliability, and safety of the aircraft. The research, development, and maintenance of high-quality aero-engines are one of the important symbols of the improvement in the level of the national defense industry [1,2].

In both the research and development and maintenance of engines, a large number of dynamic tests of mechanical parameters are required. These tests provide real-time monitoring and data that can be stored and retrieved after the experiment. By using a computer for further restoration and analysis of this data, it is possible to determine the working status, performance, and faults of relevant engine components. This provides sufficient and accurate data support for the next-step improvement and testing of the engine [3]. Data testing and storage technology is a key technology for the dynamic testing of aero-engine mechanical parameters. It connects the aero-engine and the sensors to be tested, forming an overall parameter testing system [4].

At present, foreign countries have basically achieved standardized and large-scale production of aero-engine testing equipment. At the forefront of the development of aero-engine testing technology around the world, military testing equipment in particular stands out. The United States, for example, has significant advantages in the precision manufacturing of aero-engine testing equipment and the innovative research into and development of testing technologies and is in a world-leading position [5]. Although China has also achieved phased achievements in related technologies, high-performance testing technologies are still in the development stage. Compared with developed countries, China started relatively late in testing equipment for aero-engine mechanical parameters, and there is also a shortage of ground-based mechanical testing equipment, resulting in insufficient fault exclusion capabilities for engines [6]. Despite the phased achievements, there are still disadvantages. For example, problems such as relatively single-function testing systems, inconvenient human–machine interaction, and low reliability still remain unsolved [7].

When an aircraft is in flight, due to the complex external environment and continuous high-load operation, the aero-engine may encounter uneven pressure distribution. This situation may cause components like fans and compressors to experience uneven stress and vibration, thus affecting their performance and structural integrity. Extensive research has confirmed that irregular pressure changes are a key factor influencing the stability of aero-engines and a common cause of their instability [8,9]. With the advancement of aerospace electronic technology and the continuous improvement of aero-engine performance, the field of engine testing is also confronted with new challenges [10]. Firstly, as the internal structure of engines is optimized and test signals become more complex, signal processing has become increasingly difficult [11,12]. Secondly, the diversity and instability of the testing environment make it challenging to collect key parameters, such as pressure, under specific conditions [13]. Existing testing systems often face severe signal interference and complex wiring problems in these environments [14]. Therefore, there is an urgent need to update engine testing technologies and equipment. The new-generation testing systems are required to have features such as real-time response, high-precision measurement, high sensitivity, high reliability, and miniaturization [15,16].

In view of the numerous problems currently faced in aero-engine testing, such as complex wiring, severe signal interference, and insufficient real-time performance, this paper innovatively proposes a system that integrates testing storage and wireless communication technologies. The development of this system has profound practical significance. It can address the drawbacks of traditional testing systems and meet the current testing requirements of aero-engines [17]. On the one hand, the storage system is easy to deploy and highly reliable, ensuring the stable acquisition and storage of data [18]. On the other hand, the flexibility of wireless communication technology effectively solves the wiring problem and improves the real-time performance of the monitoring link [2]. Complementing each other’s advantages, these two aspects can not only meet the testing requirements for key parameters, such as pressure signals, but also significantly reduce the system construction cost and effectively enhance the adaptability and reliability of the system in harsh and complex working environments [19]. Verified by practice, this system is easy to operate, highly automated, and has excellent characteristics, such as high-precision testing and high reliability, which is of great scientific value and practical significance.

2. Overall System Design

Figure 1 shows a schematic diagram of the specific scheme design of the test system. The test system consists of a front-end memory and a back-end test bench. The front-end memory has a built-in complete power supply system, ensuring that the device can independently perform test tasks at the front end. The DC/DC converter and power module provide the required voltage for each component of the control board and sensors. During system operation, the memory is located at the front-end test site and is independently responsible for data recording. The test bench is at a safe distance and remotely debugs, configures parameters, monitors the status, and sends instructions to the storage unit wirelessly. After the system starts, it begins to perform monitoring and data storage tasks, waiting to receive the trigger signal to determine the time reference. The physical quantity signals captured by the pressure sensor are converted into electrical signals. After being processed by the conditioning circuit, they are collected by the analog-to-digital converter module and converted into digital quantities. These digital signals are sent back to the back-end test bench through the established wireless communication link and simultaneously stored in the flash storage module. Under the control of the FPGA on the test bench, data are exchanged with the upper computer via Gigabit Ethernet [20]. After receiving the data, the upper computer uses the corresponding supporting software to process, configure, display, and store the data. The overall system architecture is shown in Figure 2.

3. Key Hardware Circuit Design

3.1. Trigger Circuit Design

After ignition, the front-end memory of the testing system can receive a signal synchronized with that of the control center. This signal is used to ensure the real-time performance and time consistency of data acquisition. Before the test starts, although the system is powered on and already recording data, it will only use the received signal as the starting mark. Once the signal is received, the system will accurately timestamp the subsequent data, enabling the data at different time points to have an accurate correspondence on the time axis. The externally connected cable contains two channels, which receive +5 V and −5 V level signals, respectively, when triggered. Once the system receives the trigger signal from the main control module through the optocoupler, it will timestamp the data, and the frame structure timing of the data will change from “0000” to “FFFF”, marking the starting point of the test. The hardware parameters of the standby trigger channel are symmetric to those of the main channel. When the signal level of the main channel is abnormal and the abnormality persists for longer than the preset time, the FPGA automatically switches to the standby channel.

The optocoupler circuit, due to the absence of electrical connection between the input and output, offers strong anti-interference capabilities and protective functions for the circuit, thereby enhancing reliability and preventing test accidents caused by misoperations [21,22]. In the testing system, the timing trigger signal is isolated and received using the optocoupler OLH6000, which has a conduction voltage of 1.9 V and an operating current of 12 mA. According to Ohm’s law, the resistance values of R8 and R9 in the circuit can be calculated. When the acquisition command is initiated, ST1_P and ST1_N conduct, outputting a low-level signal. Under the control of the FPGA, the system determines the start and end of acquisition by detecting changes in the ST1 level. Figure 3 illustrates the circuit design principle of the trigger receiving module.

3.2. Analog-to-Digital Conversion Acquisition Circuit Design

The signal collected from the sensor is passed through a voltage follower circuit and then filtered to remove interference signals and kept within the analog input range before being transmitted to the analog-to-digital conversion chip AD9220 for analog-to-digital conversion. The circuit schematic is shown in Figure 4. It features 12-bit analog-to-digital conversion accuracy [23], with the byte output order following a high-to-low transmission method, and has an adjustable sampling rate below 10 MHz to accommodate different application needs. It operates on a single 5 V power supply, with small errors, and can adapt to various input ranges and interface options, including single-ended and differential inputs [24]. An internal clock is used, with an 80 MHz clock generated internally by the FPGA providing the clock for the analog-to-digital chip, eliminating the need for an external crystal oscillator. The CAPT and CAPB pins are connected to an external coupling capacitor circuit to reduce reference voltage noise. The FPGA is connected to the AD9220’s interface, reset, control, status indicator, and other pins to complete the control of the analog-to-digital conversion chip and the configuration of the registers.

3.3. Wireless Communication Module

This system uses a wireless serial port based on LoRa spread spectrum modulation technology to support data transmission between the front-end and back-end devices. This module is based on the SX1278 chip, adopting half -duplex communication and SPI communication control. It uses hardware verification and hardware spread spectrum coding, and the frequency modulation mechanism can be customized [25]. Different working modes can be configured to meet the application requirements in various scenarios. Moreover, it has low power consumption, which is sufficient for the real-time transmission of data from the front-end sensors to be measured during an engine ignition test. An interface circuit is designed for this module, which is directly connected to the main-control FPGA through a 3.3 V IO port. The electrical connection of the interface is shown in Figure 5. The pin definitions of the chip are shown in

Table 1. Pin definitions of the wireless module.

Pin Name	Pin Type	Pin Description
GND	reference ground	ground wire
VCC	power input	power supply input
MISO	output	data output
MOSI	input	data input
DIO0-DIO5	input	configuration mode
SCK	—	clock
ANT	—	antenna

.

To enhance the reliability of wireless communication, this system employs Reed–Solomon (RS) coding to implement the FEC algorithm. RS codes are widely used in the field of wireless communication due to their strong error correction capabilities and mature hardware implementation solutions. The system opts for the RS(255,223) coding scheme, where each data block contains 223 bytes of valid data and 32 bytes of check code, capable of correcting up to 16 bytes of errors. This coding scheme ensures high error correction capability while balancing the rational utilization of FPGA resources.

Table 2. FPGA resource allocation.

Module	LUT Occupancy	DSP Occupancy	BRAM (Block)
Galois field multiplier	320	0	1
register check bit generation	450	8	0
data packet formatting	120	0	0

shows the FPGA resource occupancy and allocation, with LUT mainly used for lookup table methods and state machine control, DSP for accelerating polynomial operations, and BRAM for storing generator polynomials and intermediate calculation results.

3.4. Ethernet Communication Module

In this system, the upper computer exchanges data with the outside world through a Gigabit Ethernet interface, taking advantage of its characteristics of large-capacity and high-speed transmission [26,27]. In this system, the connection between the MAC of the FPGA and the PHY chip 88E1111 uses the GMII interface [28], with a transmission rate of up to 1000 Mbps. The chip interface design is shown in Figure 6. The model of the isolation transformer is HX5008NL. During the data transmission process, the FPGA of the back-end test bench first receives the wireless data. After decoding and verification, if there are no errors, the MAC controller sends the data to the 88E1111 through the GMII bus. Then, the data are sent to the network port through the isolation transformer HX5008NL to exchange data with the upper computer, thus completing the data transmission.

4. Key Control Logic Design

4.1. Overall Logic Design

The overall logic design process is illustrated in Figure 7. The monitoring and acquisition module includes optocoupler trigger control and analog-to-digital conversion acquisition, primarily completing the collection of analog signals through the control of analog-to-digital conversion sampling logic, while also receiving digital signals as trigger commands; the readback storage module mainly functions to store the collected data and FPGA logic code; the data transmission module is composed of wireless communication control and gigabit Ethernet control, realizing various data communication functions.

4.2. Analog-to-Digital Conversion Logic Design

The analog-to-digital conversion acquisition process is shown in Figure 8. After the chip is initialized, the system enters a standby state, waiting for an external trigger signal to initiate the data acquisition process. Upon receiving the trigger command, the FPGA starts reading the preset channel addresses from the ROM. The system checks the validity of the channel addresses read from the ROM to ensure the correct target channel for data acquisition. Once the address is confirmed to be valid, the system prepares the signal channel for analog-to-digital conversion. Following the predetermined timing control, the analog-to-digital conversion begins converting the analog signal to a digital signal. The converted data are temporarily stored in the FIFO, and upon receiving a read signal, the system transfers the data from the FIFO to the flash storage module.

4.3. Wireless Module Logic Design

The wireless part of the front-end memory is responsible for receiving and identifying the instructions from the back-end, modulating the real-time monitoring or read-back data into LoRa RF signals and transmitting them into the air; the wireless part of the back-end test bench is responsible for sending the instructions issued by the host computer, completing the reception and demodulation of the LoRa RF signals returned by the front-end memory, and transmitting them to the main control chip and the host computer for information display. Taking the wireless front-end memory module as an example, Figure 9 shows the logic flow chart of the wireless module. First, start the wireless module and complete its initialization process. After initialization, the system needs to wait for the wireless module to complete the internal reset process. Using different level combinations of the DIO pins, configure the module to enter the required configuration mode through the MODE_CTL signal. In the configuration mode, the baud rate of the serial communication is set to 9600 bps, with a data format of 8 data bits, no parity bit, and 1 stop bit. After the parameters are written, the system switches the wireless module from the configuration mode to the transmission mode to start the data sending and receiving tasks. For the wireless receiving module, its operation logic is similar to that of the sending module, also requiring steps such as initialization, reset, mode configuration, and parameter setting.

After inserting the FEC encoding logic into the FPGA, the data transmission timing of the SPI interface is controlled through a state machine to ensure the stable transmission of encoded data packets. The encoding and decoding logic is controlled by a finite state machine, and the implementation of the encoding and decoding logic is shown in Figure 10.

In the encoding logic, the lookup table method is used to implement multiplication operations. The coefficients of the generator polynomial are calculated and stored in the BRAM of the FPGA. The lookup table method transforms complex real-time multiplication operations into address index lookups, significantly reducing the complexity of real-time calculations and being suitable for the parallel processing characteristics of FPGA. The generation of parity bits is achieved through a linear feedback shift register. The input data enter the shift register in byte streams and undergoes iterative operations using the following polynomial:

$$G\left(X\right)={\prod }_{i=0}^{31}(x-{\alpha }^i)$$

(1)

Finally, a 32-byte check code is generated. The original data and the check code are combined into an FEC-encoded data packet. The maximum transmission unit of the LoRa module is adjusted to ensure the complete transmission of the encoded data packet.

The decoding state machine is responsible for receiving FEC encoded data packets and detecting and correcting errors. It waits for data reception in the IDLE state and initializes decoding parameters. When the data_received signal is high, it enters the RECEIVE state to receive 255 bytes of encoded data and then calculates the syndrome of the data through a shift register and determines whether there are any errors. If syndrome_zero = 1, it enters the CORRECT state; otherwise, it enters the SOLVE_ERROR state, using the Berlekamp–Massey algorithm to calculate the error location polynomial. In the CORRECT state, it calculates the error values, corrects the received data, and finally sends the corrected data to the flash storage module.

4.4. Ethernet Communication Logic Design

The wireless communication module has successfully transmitted the data to the back-end test bench. In order to achieve further data processing, storage, and interaction with external devices, the system integrates the Ethernet communication module to fulfill this function. The logic block diagram of the UDP top-level module is shown in Figure 11, which includes a UDP data processing module, a clock CLK module, and a data buffer FIFO module. The data processing module is mainly responsible for handling upper-layer network protocols, including data segmentation and recombination. The clock module is used to synchronize data processing operations. By adjusting the phase of the clock signal, it ensures clock synchronization during high-speed data transmission. The data buffer module temporarily stores the data packets received by the UDP module. The data processing module consists of several key sub-modules. The UDP sending module manages the data sending process. It uses the state–machine transition method to package the valid data in the Ethernet frame format and send it back. The UDP receiving module handles data reception. It extracts data packets from the Ethernet and checks whether the MAC address and IP address are consistent with those of the target board. The CRC data verification module performs a cyclic redundancy check to ensure the integrity and accuracy of the data [29].

5. Test Results and Analysis

5.1. Reliability Testing

The overall physical system is shown in Figure 12.

To test the reliability and anti-interference ability of the FEC algorithm in the wireless communication of this system [30,31], a series of system performance verification experiments were conducted in a site simulating real test conditions. The experiments simulated wireless communication environments under different interference intensities and recorded and analyzed the changes in the bit-error rate (BER) and packet loss rate, respectively [32]. The specific test method is as follows: First, a series of interference intensity levels were set, ranging from −95 dBm to −75 dBm. These values reflect the interference intensities from low to high. Under each interference intensity level, the BER and packet loss rate were measured both without FEC and with FEC. Subsequently, the same test method was applied in a high-temperature laboratory environment. By adjusting the attenuator in the signal transmission path, the change in interference intensity could be precisely controlled.

The experimental results are shown in Figure 13 and Figure 14. As the interference intensity increased, the BER and packet loss rate without FEC increased significantly, indicating that interference has a negative impact on the signal transmission quality. However, after introducing the FEC algorithm, both the BER and packet loss rate were significantly reduced. Although high temperature can affect the system performance, it was found through comparison that in a high-temperature environment, the system with the FEC algorithm had lower BER and packet loss rate than the system without the FEC algorithm, showing greater stability. This indicates that through redundant coding and error correction mechanisms, FEC can effectively correct transmission errors, significantly enhance the anti-interference ability of the signal, optimize the integrity and stability of data transmission, and greatly improve the reliability of the system.

5.2. Upper Computer Testing

To verify the reliability of the overall functions of the designed system, it was applied to a pressure parameter testing experiment of a certain type of aircraft engine. First, the engine was installed on the test bench. Then, the sensors to be tested were installed on the outer wall of the engine through threads according to the set direction and position. A professional aviation cable was used to connect the front-end memory with the main part of the testing system. A digital trigger cable was introduced to the memory to receive the trigger signal for the start of the test. The front-end memory was placed on a special shock-absorbing pad near the test bench, and the back-end testing station was arranged at a certain safe distance from the test bench. The entire testing system was powered on, and the back-end testing station was connected to the upper computer via an Ethernet cable. The upper computer sent commands to start monitoring and storage to initiate the experiment. After the experiment, the data in the flash storage module was read back. After being processed by the upper computer software, the curve was plotted as shown in Figure 15. The y-axis represents the pressure in MPa, and the x-axis represents time. From 0 to 13 s, the aero-engine is in the startup phase. After the engine ignites, the pressure in the combustion chamber gradually builds up, and the fan and compressor start to operate. From 13 to 26 s, the engine enters a stable idle state, and the pressure in the combustion chamber rises slightly. Subsequently, the engine thrust gradually increases, and the engine is in the medium-load stage, with a significant increase in the combustion chamber pressure. From 67 to 93 s, the engine is in the full-load stage, gradually reaching the maximum thrust state, and the combustion chamber pressure reaches its peak. Finally, the engine is shut down for cooling, and the pressure in the combustion chamber is gradually released.

6. Conclusions

In response to the problems of complex wiring and poor flexibility in traditional wired testing systems for aero-engines, a wireless transmission aero-engine pressure testing system based on FPGA was designed and implemented. The system integrates a front-end memory and a back-end testing station and combines LoRa wireless communication technology with the FEC algorithm. Through testing in complex environments, this system can monitor and record the pressure parameters measured in aero-engine tests, completely store valid data, and significantly improve the reliability and anti-interference ability of data transmission. In addition, the system solves problems such as wiring difficulties, management complexity, and insufficient scalability. The system features simple operation, a high level of automation, as well as high-precision testing and high reliability. It can adapt to complex and harsh working environments and has high scientific value and practicality in the aviation and military industries.