A 64 dB-DR, 4.5 GHz-BW Logarithmic Amplifier for RSSI Measurement in 180 nm SiGe Process

Abstract

For RSSI measurement of RF systems, a wide band, large dynamic range (DR), parallel-summation logarithmic amplifier is presented in this paper. The circuit adopts an 8-stage DC-coupled cascaded limiting amplifier structure. The output voltage of the limiting amplifier is converted into current through a rectifier to realize parallel summation. In order to reduce offset, this paper introduces offset reduction circuits in the gain and output stage, respectively. In addition, a log slope adjuster is proposed, which can achieve log slope control of different frequency inputs. The post-simulation results show that at a power supply voltage of 5 V, the 3 dB gain bandwidth is 4.5 GHz, the dynamic range reaches 64 dB, and the log error is less than ±1 dB. The overall circuit consumes 21 mA of current.

1. Introduction

In wireless communication systems, receivers need to process weak radio frequency (RF) signals that requires a dynamic range of 80–120 dB. Such a large dynamic range can lead to design complexity and even impracticality. Therefore, a circuit is needed to compress the wide dynamic range signal dynamically, making it easier for subsequent circuit processing. In practical applications, typical circuits for compressing wide dynamic range signals mainly include automatic gain control (AGC) systems and logarithmic amplifiers; AGC systems belong to linear compression technology. The AGC is essentially a negative feedback system that linearly processes signals, consisting of a variable gain amplifier, a detector, a low-pass filter, and a comparator. When the input signal is small, the AGC is equivalent to a linear amplifier, linearly amplifying the small signal. When the signal reaches a certain value, the amplified output signal reaches a threshold, triggering the AGC system. The gain of the variable gain amplifier will be reduced to a certain extent, ensuring that the amplitude of the signal output is always controlled within a small range. So this linear processing scheme limits the dynamic range of the input signal [1]. Additionally, logarithmic amplifiers belong to nonlinear compression technology. When the input signal is small, the logarithmic amplifier will perform linear amplification. When the input signal is large, the logarithmic amplifier will perform nonlinear compression, and the logarithmic characteristic will always be maintained between the input and the output signal. The logarithmic amplification of signals is an instantaneous transformation, which means that logarithmic amplifiers can instantly compress large dynamic range input signals into small dynamic range output signals. Therefore, logarithmic amplifiers can be used to measure signals with wide dynamic range and high frequency and are widely used for signal amplitude control in RF systems.

Since the birth of logarithmic amplifiers, after more than half a century of research and development, they have now become the preferred circuit for processing wide dynamic range signals. A broadband logarithmic amplifier was designed using CMOS 130 nm technology [2]. This logarithmic amplifier adopts a structure combining a 3-stage amplifier and a rectifier, with a dynamic range of 43 dB and bandwidth of 14 GHz. Simultaneously, it has a smaller log error. Due to the use of CMOS technology, in order to avoid the complexity of circuit design caused by differential circuits, only a single-ended structure can be adopted, which limits the overall noise and anti-interference performance. A current-input current-output CMOS logarithmic amplifier was proposed for biological signal processing applications [3]. This circuit uses a floating voltage source and a linear resistive element within a translinear loop to achieve variable gain. Simultaneously, it utilizes a translinear-based resistive cancellation technique for temperature compensation. This structure is only suitable for detecting low bandwidth biological current signals. A digitally calibratable logarithmic amplifier was presented to be applied as a predistortion power amplifier [4]. By using a digital tuning interface, the log error is only 0.15 dB. Due to its dynamic range of only 20 dB, the application of this structure in wide dynamic range circuits is limited. A logarithmic amplifier with an operating frequency of 3–17 GHz based on a 0.25 µm GaN process was proposed [5]. Its dynamic range reaches 55 dB and the minimum log error is 0.9 dB. All performances are relatively balanced. Zhang, D et al. presented a detector logarithmic video amplifier that consists of a MMIC chip detector and broadband millimeter-wave amplifier [6]. The operating frequency range is 18–44 GHz, with a dynamic range of 60 dB. But the log amplifier belongs to a discrete millimeter-wave circuit and cannot be integrated on a single chip. Ravi, G et al. designed a logarithmic amplifier with HFET as an RF switch to achieve dual-channel input. HFET switches have low insertion loss and good isolation. This circuit mainly uses AD8309 to build a logarithmic amplification system. Although the dynamic range reaches 60 dB, the system is large and cannot be embedded into RF systems, with a bandwidth of only 32 MHz.

This paper focuses on the application of received signal strength indicator (RSSI) measurement and a wideband logarithmic amplifier is presented. The logarithmic amplifier is implemented based on a parallel-summation structure of 8-stage limiting amplifiers, with each stage providing 8 dB gain. The voltage output of each limiting amplifier is converted into current through a rectifier and achieves signal summation. Finally the I–V converter outputs the voltage signal. In response to the low-distortion requirements, the offset reduction circuits in both the cascade stage and the I–V converter are added. To meet the detection applications of signals with different frequencies and amplitudes, this paper proposes a log slope adjuster. By configuring different off-chip resistors, precise control of the log slope can be achieved.

2. Circuit Design

Logarithmic amplifiers are commonly used in RF receivers to process intermediate frequency signals. After the intermediate frequency signal enters the RSSI circuit, if the signal amplitude is very small and cannot be limited by each amplifier stage, the signal will be amplified by N-stage limiting amplifiers. If the signal amplitude is large and is limited by a certain amplifier stage, all amplifiers after that stage will be limited, and the amplifiers in the limiting state will output a fixed limiting value [7,8,9]. In order to facilitate signal summation, a rectifier is connected to the subsequent stage of each limiting amplifier to convert voltage into current. At this time, the output current can be directly added. Finally the summed current is converted into voltage, which is the final output of the circuit [10]. The parallel-summation logarithmic amplifier is shown in Figure 1, which mainly includes a differential limiting amplifier, rectifier, two bandgaps, log slope adjuster, and I–V converter. The 8-stage limiting amplifier is divided into three structures. The first stage is a differential amplifier (LA1), and the second to seventh stages (LA2) are differential amplifiers with emitter followers. The eighth-stage limiting amplifier (LA3) has a similar structure to the first stage, but it includes an offset amplifier to reduce the offset between stages. Each limiting amplifier provides 8 dB gain, which ensures an overall dynamic range greater than 60 dB. The 9-stage rectifier converts the input and output voltage of the 8-stage limiting amplifier into current and sums them up at nodes A and B. The current is input to the I–V converter. Finally, the amplified signal is output by the I–V converter. The integrator, consisting of the I–V converter, resistors R1/R2, and capacitors C1/C2/C3, has a low-pass filtering function in the frequency domain, which removes the ripple of rectifiers. The input port of the log slope adjuster is connected to an external adjustable resistor, Radj. Radj is connected in series with the internal resistor to adjust the base voltage of the BJT transistor, thereby changing the current at nodes A and B and achieving control over the log slope. The offset amplifier in the 8th-stage amplifier samples the offset. Capacitors Cos1 and Cos2, along with resistors Ros1 and Ros2, form a low-pass filter to filter out high-frequency components in the feedback signal. The DC component in the offset is fed back to the 1st-stage limiting amplifier, thereby reducing the inter-stage offset caused by DC coupling. Two bandgaps provide bias voltages to the limiting amplifier and rectifier, respectively, to avoid their crosstalk.

The first limiting amplifier, as shown in Figure 2, consists of three parts: the main limiting amplifier, the output stage, and the common-mode voltage extraction circuit (Vcm extractor) [11]. The main limiting amplifier is a single-stage common-emitter amplifier, and the tail-current transistor Q3 is biased by Vbias_LA output from the bandgap Bandgap_LA. Capacitor C1 serves to stabilize the bias DC voltage. Resistors R3, R4, and Rbe3 together determine the collector current Ice of Q3, as well as the transconductance of Q1 and Q2, which plays a decisive role in the bandwidth of the limiting amplifier. Q4 and Q5 form a cross-coupled negative resistor structure to increase output impedance and gain. Qbias, Rb1, and Rb2 form a circuit to set the input common-mode voltage to 3.8 V. When the input amplitude is small, the limiting amplifier can be approximated as a linear amplifier. When the input signal reaches the threshold, the output amplitude no longer increases with the input but is limited to a certain amplitude [12]. At this point, the relationship between the differential output voltage and the differential input voltage can be expressed as follows:

$$V_{od}=I_{ce,Q3}·R_1·\tanh ({\displaystyle \frac{-V_{id}}{2V_T}})$$

(1)

where $V_{od}$ is the output differential-mode voltage of limiting amplifier, $I_{ce,Q3}$ is the collector current for Q3, $V_{id}$ is the input differential-mode voltage, and $V_T$ is thermal voltage. The common-mode voltage extractor is an emitter follower that extracts the output common-mode voltage and inputs it into the rectifier, so that the rectifier current output is logarithmic to the input voltage. The limiting amplifier is a single-pole system, with the main pole located at the output nodes (A1, B1). Therefore, the relationship between the bandwidth of a single-stage limiting amplifier and the overall logarithmic amplifier bandwidth can be expressed as follows:

$$f_{\mathrm{Limiting} \mathrm{Amplifier}}={\displaystyle \frac{1}{\sqrt{2^{\frac{1}{N}}-1}}}·f_{\mathrm{Logarithmic} \mathrm{amplifier}}$$

(2)

Therefore, in order to meet the requirement of a logarithmic amplifier bandwidth greater than 4.5 GHz, the bandwidth of the single-stage limiting amplifier must be greater than 14.96 GHz.

The function of a rectifier is to detect the voltage of the signal to be tested and output a differential current with which it has a logarithmic relationship. The rectifier, as shown in Figure 3, is a three-port input common-emitter differential structure. The two differential output voltages of the limiting amplifier and the output of the common-mode voltage extractor are simultaneously input into the differential pair.

The output common-mode voltage of the limiting amplifier is V_cm, the output differential-mode voltage is V_id, and I_c1, I_c2, and I_c3 are the collector currents of Q1, Q2, and Q3, respectively.

$$V_{cm}+{\displaystyle \frac{V_{id}}{2}}-V_{be1}=V_{cm}-V_{be3}$$

(3)

$$V_{cm}-{\displaystyle \frac{V_{id}}{2}}-V_{be2}=V_{cm}-V_{be3}$$

(4)

And $I_c=I_s·e^{{\displaystyle \frac{V_{be}}{V_T}}}$, so

$$V_T\ln {\displaystyle \frac{I_{c1}}{I_{s1}}}-V_T\ln {\displaystyle \frac{I_{c3}}{I_{s3}}}={\displaystyle \frac{V_{id}}{2}}$$

(5)

$$V_T\ln {\displaystyle \frac{I_{c3}}{I_{s3}}}-V_T\ln {\displaystyle \frac{I_{c2}}{I_{s2}}}={\displaystyle \frac{V_{id}}{2}}$$

(6)

The Q3 emitter area is chosen to be twice the emitter areas of Q1 and Q2, that is:

$$I_{s3}=2I_{s2}=2I_{s1}$$

(7)

Meanwhile,

$$I_{c1}+I_{c2}+I_{c3}=I_{c4}$$

(8)

Combining (5), (7) and (6), (7), respectively, gives:

$${\displaystyle \frac{I_{c1}}{I_{c3}}}={\displaystyle \frac{1}{2}}{e}^{{\displaystyle \frac{V_{id}}{2V_T}}}$$

(9)

$${\displaystyle \frac{I_{c3}}{I_{c2}}}=2e^{{\displaystyle \frac{V_{id}}{2V_T}}}$$

(10)

Combining (8)–(10) gives:

$$I_{c1}={\displaystyle \frac{1}{2}}·{\displaystyle \frac{I_{c4}·e^{\frac{V_{id}}{2V_T}}}{1+\frac{1}{2}(e^{\frac{V_{id}}{2V_T}}+e^{-\frac{V_{id}}{2V_T}})}}$$

(11)

$$I_{c2}={\displaystyle \frac{1}{2}}·{\displaystyle \frac{I_{c4}·e^{-\frac{V_{id}}{2V_T}}}{1+\frac{1}{2}(e^{\frac{V_{id}}{2V_T}}+e^{-\frac{V_{id}}{2V_T}})}}$$

(12)

$$I_{c3}={\displaystyle \frac{I_{c4}}{1+\frac{1}{2}(e^{\frac{V_{id}}{2V_T}}+e^{-\frac{V_{id}}{2V_T}})}}$$

(13)

At this time, the output differential current is $\Delta I$ is given by:

$$\Delta I=I_{c1}+I_{c2}-I_{c3}=I_{c4}·{\tanh }^2({\displaystyle \frac{V_{id}}{4V_T}})$$

(14)

From (14), it can be seen that the output current of each rectifier stage is approximately exponentially related to the input voltage.

LA2, as shown in Figure 4, mainly consists of three parts: the main limiting amplifier, emitter follower, and common-mode voltage extractor [13]. The main limiting amplifier is the same as LA1 and is a single-stage common-emitter amplifier. The emitter follower also uses Q8 and Q9 to form a cross-coupling structure, forming a negative resistance of −2/gm. On the other hand, Q8 (Q9) is connected in series between Q6 (Q4) and Q5 (Q7). By adjusting the Vce of Q4 and Q6, it is relatively easy to ensure that the common-mode voltage output by the emitter follower is consistent with the common-mode voltage output by the main limiting amplifier. Because the rectifier needs to extract the common-mode voltage VCM-OUT of each limiting amplifier stage, which works together with the output voltages VOUTN and VOUTP to form a logarithmic function relationship between the output current and the input voltage, it is necessary to ensure that the common-mode component in VOUTN and VOUTP is the same as that in the output nodes A1 and B1 of the main limiting amplifier.

In multi-stage limiting amplifiers, DC coupling is usually used for cascading [14,15,16]. The reasons are that, firstly, it can avoid the use of capacitors between stages, which can effectively reduce layout area; and secondly, the capacitor determines the minimum operating frequency of the logarithmic amplifier, which to some extent limits the amplifier bandwidth. However, the DC coupling method can cause the offset to be amplified, reducing the dynamic range of the overall logarithmic amplifier. Therefore, it is necessary to add a global feedback offset amplifier in the logarithmic amplifier and use DC negative feedback to reduce the offset. At this point, the feedback pathway has a low-pass characteristic. Therefore, it is necessary to control the cutoff frequency of the feedback path and filter out high-frequency components in the feedback signal to prevent the input signal from directly coupling to the output stage [17,18,19]. The eighth-stage limiting amplifier is shown in Figure 5, and it is similar to LA1. It just adds a offset amplifier, which extracts the output offset of the 8-stage limiting amplifier and feeds it back to LA1 in the form of current to reduce inter-stage offset.

The I–V converter is shown in Figure 6, which converts the differential input voltage into a single-ended signal. C3 and R8 are the compensating capacitor and resistor, respectively, to stabilize its frequency characteristics. The circuit also includes an offset reduction circuit. When the limiting amplifier experiences offset, assuming that the voltage at node B2 is greater than that at node A2, the voltage at node B3 is less than the voltage at node A3. The base voltage of Q16 decreases, and similarly, the base voltages of Q15 and Q14 decrease, resulting in a decrease in the current drawn from Q11 by Q15. Then, there is an increase in Ic11, causing a decrease in the voltage of node B2. At the same time, the voltage at node B3 increases and the voltage at the lower plate of capacitor C1 rises. Due to the conservation of charge on C1, the voltage at the upper plate (node A2) of C1 increases, ultimately making the voltages at nodes A2 and B2 equal and eliminating the output offset.

The log slope adjuster is a buffer consisting of a 2-stage amplifier, as shown in Figure 7. The input port VI is connected in series with an external adjustable resistor, Radj, forming a feedback path with the I–V converter. Its function is similar to an offset compensation amplifier. There is a constant difference in the sum of the output currents of the 9-stage limiting amplifier. If it is directly input into the I–V converter, it will cause the output to approach the power supply or ground. Therefore, a log slope adjuster is needed to compensate for the input current of the I–V converter. The logarithmic amplifier output adjusts the Q10 base voltage, then the output currents Iout0 and Iout1 change accordingly, with a fixed difference between them. So they ultimately change the sum current of the I–V converter input.

3. Post-Simulation Results

The proposed design was implemented by an 180 nm 1P6M SiGe process. The layout is shown in Figure 8 with an area of 0.907 mm². And the active area is 0.3268 mm².

The AC characteristics of the logarithmic amplifier were simulated, and the results are shown in Figure 9. The DC open-loop gain is 64.5 dB, and the 3 dB-bandwidth reaches 4.5 GHz.

The input signal frequencies were set to 100 MHz, 2 GHz, and 4.5 GHz, and the input–output characteristic curves of the logarithmic amplifier are shown in Figure 10. Good logarithmic linearity can be achieved within the input signal range of −40 dBm to 24 dBm, with a dynamic range of approximately 64 dB and logarithmic slope of 13.43 mV/dB. Figure 11 shows the fitting results of the log error, which is less than ±2 dB within the dynamic range.

When a sudden −20 dBm sine wave signal of 100 MHz is input, the response time of the logarithmic amplifier is shown in Figure 12. The response time for the output waveform to rise from 10% to 90% amplitude is 52 ns. When the input signal amplitude is the same and the frequency is 4.5 GHz, the response time is approximately 56 ns.

The log slope of different input frequencies was simulated. When the input frequencies are 100 MHz and 4.5 GHz, respectively, the results are shown in Figure 13. The log slope ranges from 13.5 to 14.5 mV/dB. When the input frequency is fixed to 4.5 GHz, under different temperatures, the log slope vs. input frequency curves are presented in Figure 14, which is within the range of 10.5–15 mV/dB.

Because only through testing can the reduction of offset voltage be better characterized, we used Monte Carlo simulations to represent the impact of the offset reduction circuit, as shown in Figure 15. The results show that the offset is approximately 97.3 µV. It is overall at a relatively low level.

In a cascaded system, the noise performance is mainly determined by the first stage. We performed noise simulations on the overall logarithmic amplifier. When there is no input signal, the noise floor is shown in Figure 16. The noise PSD is approximately 4.2 μV/$\sqrt{Hz}$. It can be seen in the low frequency domain that the flick and thermal noise affect the log amplifier together. And with the increase in frequency, the thermal noise dominates.

The comparison of the results this work with others are shown in

Table 1. Performance comparison.

Parameter	[2]	[4]	[20]	[21]	[22]	This Work
Process	130 nm CMOS	350 nm SiGe BiCMOS	180 nm CMOS	180 nm CMOS	180 nm CMOS	180 nm SiGe BiCMOS
Bandwidth (GHz)	16	2.7	1.8	10.6	8	4.5
Dynamic range (dB)	43	24	29	20	40	64
Log error (dB)	±1.5	±0.15	±1	±2.4	±1	±1
Response Time (ns)	N/A	2.2	N/A	N/A	N/A	52
Log slope adjustment	No	No	No	No	No	Yes
Pdc (mW)	35.2	85.8	16	10.8	70	103

. Due to the use of an 8-stage parallel limiting amplifier structure, and each stage with 8 dB gain, a larger dynamic range has been achieved. At the same time, a 9-stage rectifier is used to convert the output voltage of the limiting amplifier into current, and only a one-stage I–V converter is used, which to some extent improves the response time. Finally the logarithmic amplifier designed in this paper has the maximum dynamic range. Compared with previous achievements in performance parameters such as bandwidth, log error, and response time, it has achieved a good compromise. At the same time, our design also has an offset reduction circuit and log slope adjuster, with relatively complete functions. Because the work in Ref. [3] was designed for biomedical applications in which the dynamic range is only 24 dB, it has a better response time, less power consumption, and lower log error. And the input dynamic range of their work is only 20 dB, which means the logarithmic amplifier only has a response small signal and it has fewer limiting amplifiers in parallel.

4. Conclusions

A wideband logarithmic amplifier based on a parallel summation structure is presented in this paper. The circuit is realized by a HHGRACE 0.18 µm 1p6m SiGe process. The power supply voltage is 5 V. In order to meet the requirements of low distortion applications, this paper adopts a DC-coupling cascade structure and global/local offset reduction circuits in the 8th-stage limiting amplifier and output stage, respectively. This paper proposes a log slope adjustment circuit. By configuring different off-chip resistors, precise control of the log slope can be achieved. The post-simulation results show that the logarithmic amplifier has a bandwidth of 4.5 GHz, dynamic range of 64 dB, log error of only ±1 dB, with a power consumption of 103 mW, which can be applied to RF PA, RSSI measurement, and radar systems.