Optimization of Cross-Bridge Kelvin Resistor (CBKR) Layout for the Precise Contact Resistance Measurement of TiSi₂/n⁺ Si

Abstract

This study investigates the impact of cross-bridge Kelvin resistor (CBKR) layout designs on specific contact resistivity (ρ_c) measurements between TiSi₂ and n⁺ Si. The theoretical ρ_c is calculated as a function of silicon doping concentration (N_Si) and Schottky barrier height (ϕ_b) to evaluate the measurement value. Various CBKR patterns are fabricated and measured with different contact hole areas (A_c) and aligned margins (δ) to evaluate measurement accuracy. The results show that CBKR with a narrow active width (W) can more accurately measure the ρ_c compared to the conventional layout mainly attributed to the current path confinement. In addition, if the contact hole length (L) is smaller than the transfer length (L_T), the entire A_c contributes to the voltage drop of contact resistance (R_c), resulting in improved measurement accuracy. In contrast, if δ is increased, the measurement error decreases due to current dispersion near the recessed TiSi₂ region, which is different from conventional CBKR layouts. Consequently, the measured ρ_c with an optimized layout shows a close value to the theoretical ρ_c.

1. Introduction

The metal–oxide–semiconductor field-effect transistors (MOSFETs) have evolved over the past several decades through miniaturization for better performance and higher integration density [1,2,3,4,5,6,7]. Conventionally, the current drivability of MOSFET is mainly determined by the channel resistance (R_ch), and the other parasitic resistance (R_para) such as a source/drain (R_sd), a contact (R_c), and a metal interconnect (R_m) can be ignorable. However, in the case of state-of-the-art short-channel MOSFET, the portion of R_para in the total resistance (R_tot) is significantly increased because an aggressive scaling of channel length decreases the R_ch, while the decrease in source/drain junction depth and contact area increases the R_sd and R_c (i.e., R_para), respectively. Consequently, the proportion of R_para in the total resistance has started to exceed R_ch, with the R_c accounting for more than 50% of the R_para [8,9,10,11]. Therefore, reducing the R_c has become increasingly important for improving MOSFET performance. Several strategies, such as a metal–insulator–semiconductor (MIS) contact [12], a silicidation [13], and doping engineering [14], have been suggested to reduce the R_c by decreasing a specific contact resistance (ρ_c). Among them, Ti silicidation is a promising technique since it can simultaneously achieve a high doping concentration [i.e., a low sheet resistance (R_sh)] with the help of dopant segregation and a low Schottky barrier height (SBH) [15,16,17,18].

In addition to the importance of reducing ρ_c, the significance of test patterns that can precisely evaluate the ρ_c increases, too. When the measurement range of ρ_c is below 10⁻⁷ Ω∙cm², parasitic metal resistance and/or a current crowding effect cannot be ignored, leading to significant measurement errors. Therefore, the parasitic components of the test pattern should be minimized and eliminated. There are two representative test patterns for measuring R_c: the cross-bridge Kelvin resistor (CBKR) [19,20,21,22,23] and the transmission line model (TLM) [24,25,26]. The CBKR directly measures the ρ_c using its four-terminal structure, implying higher accuracy and simplicity [Figure 1a]. The TLM pattern determines the ρ_c by extrapolating the resistance and length. However, TLM requires complex modeling to extract ρ_c from total resistance measurements due to its high sensitivity to design and process parameters, which can introduce additional measurement errors during extrapolation.

In the CBKR, current is applied through the two terminals (I₂₄) while voltage is measured across the other two terminals (V₁₃). R_c is extracted using Ohm’s law; V₁₃/I₂₄ and ρ_c are calculated by multiplying the R_c by A_c (i.e., ρ_c = R_c · A_c). Although R_c can be calculated by using this one-dimensional (1-D) model, in practice, the additional voltage drops caused by current crowding near the contact hole can introduce measurement errors [19,20,21,22,23]. These errors become more pronounced when extracting a low ρ_c. There are several reports that the current crowding in CBKR can be suppressed by reducing the space between the contact hole and the active layer [19,20]. However, when the Ti silicidation is applied, it reduces the R_sh and changes the current distribution adjacent to the contact hole since it consumes the silicon and forms a recessed TiSi₂ [Figure 1b,c]. Therefore, the current flows from the n⁺ Si region to the TiSi₂ via the contact hole, resulting in a different layout dependency compared to the non-Ti silicidation case. Recently, Ti silicidation has emerged as a promising alternative to CoSi2 and Ni(Pt)Si in advanced CMOS technologies due to its low ρ_c [16,17,18]. Although various silicides have been studied using TLM patterns [25], to the best of our knowledge, there is no research on CBKR layouts considering the effects of Ti silicidation. Therefore, in this work, the various CBKR layouts are fabricated and analyzed to extract a precise ρ_c between TiSi₂ and n⁺ Si.

2. Fabrication Process

The CBKR test pattern is fabricated using a (100) low-doped p-type substrate. A 3 × 10²⁰ cm⁻³-doped n-type region is formed by using an arsenic ion implantation (1 × 10¹⁵ cm⁻²-dose and 10 keV-acceleration energy), followed by a dopant activation at 1050 °C in an N₂ atmosphere for 30 s with a rapid thermal annealing (RTA). It is patterned by photolithography and a Si reactive ion etching (RIE) for 1 µm depth to create a mesa pattern [Figure 2a]. A 400 nm-thick SiO₂ is deposited using a plasma-enhanced chemical vapor deposition (PECVD), and a contact hole is patterned by the dry and wet etching process [Figure 2b,c]. After depositing a 30 nm-thick Ti with the help of a sputtering system [Figure 2d], two-step annealing processes are performed for a TiSi₂ at the contact hole region. The first annealing is conducted at 750 °C for 30 s. Subsequently, an unreacted Ti is selectively removed using a sulfuric acid and hydrogen peroxide mixture (SPM, H₂SO₄:H₂O₂ = 4:1) at 120 °C for 20 min [Figure 2e]. The conditions for the second annealing are 850 °C and 30 s to convert the C-49 phase to the C-54 phase [27]. Figure 3a shows the R_sh of non-patterned arsenic-doped Si at each Ti silicidation step measured by a four-point probe. It is clear that the R_sh decreases as the processes proceed. As a back-end process, a 400 nm-thick Al and a 30 nm-thick TiN are sputtered on the substrate in sequence, followed by the patterning [Figure 2f]. Finally, a thermal annealing is performed at 400 °C for 30 s.

The CBKRs are fabricated in two different layouts. In the case of layout #1, an active width (W) is larger than the length of one side of a square-shaped contact hole (L) by a double align margin (δ) (i.e., W = L + 2δ) [Figure 3b]. On the other hand, layout #2 features the same W and L [Figure 3c]. Both layouts define the contact hole area (A_c) as a square of L (i.e., A_c = L²). The δ is identical along both the X and Y axes in layout #1 and layout #2. Figure 3d,e shows the plan-view scanning electron microscope (SEM) images for layouts #1 and #2 samples, respectively. In order to analyze the influence of pattern design, the various samples with the different L and δ are fabricated. The detailed information about design parameters is summarized in

Table 1. Design parameters of CBKR layout.

Parameters	Layout #1	Layout #2
Contact hole length (L)	0.5/1/2/3/4/5 μm
Contact hole area (Ac)	0.25/1/4/9/16/25 μm2
Align margin (δ)	0.2/0.5/1/2/3 μm
Active (W)	2δ + L	L

.

3. Simulation Structures and Extraction Condition

To analyze the measurement error related to the layout design, the technology computer-aided design (TCAD, Sentaurus™) simulations are performed. To account for omnidirectional current crowding, the three-dimensional (3D) structures are considered. Figure 4a,b shows the schematic view of 3D CBKR structures for layout #1 and layout #2, corresponding to the fabricated structures. Figure 4c shows the cross-sectional view (Y–Z plane) between nodes 2 and 4 at the center of the contact hole. Considering the ion implantation process conditions, the n⁺ Si junction exhibits a Gaussian doping profile with a peak doping concentration of 3 × 10²⁰ cm⁻³ at the surface. A TiSi₂ thickness is 69 nm, as shown in Figure 4d, which is 2.3 times thick at 30 nm; deposited Ti thickness. Last of all, the Al is used as the metal layer for nodes 3 and 4. The TiN on top of Al shown in Figure 2f is ignored for the simulation due to its negligible impact on contact resistance. To extract R_c in CBKR structures, I₂₄ is swept from −40 μA to 40 μA in both simulation and measurement. In measurement, I₂₄ is applied using the source measurement unit (SMU), while V₁₃ is measured using the voltage measurement unit (VMU) of Keithley 4200A-SCS. R_c is extracted at current saturation points; I₂₄ = ±40 μA.

4. Theoretical ρ_c Calculation

The ρ_c between TiSi₂ and n⁺ Si is theoretically calculated based on the doping concentration and Schottky barrier height (SBH, ϕ_b) to evaluate the measurement accuracy of the test patterns. If the doping concentrations exceed 5 × 10¹⁹ cm⁻³, a field emission dominates the tunneling process, and ρ_c is expressed as Equation (1) [28].

$${\rho }_c={\displaystyle \frac{k_B\sin \left(\pi c_{1}kT\right)}{A^{*}\pi qT}}\exp \left({\displaystyle \frac{q{\varphi }_b}{E_{00}}}\right)$$

(1)

Here, q, k_B, T, ε_Si, and A^* represent electron charge, Boltzmann constant, temperature, silicon permittivity, and the effective Richardson constant, respectively. The A^* is 120 A∙cm⁻²∙K⁻², where the effective mass (m*) is equal to the free electron mass (m₀) [28]. The functions E₀₀ and c₁ describe the dependence of tunneling current on the temperature and doping concentration, which are expressed as Equations (2) and (3), respectively.

$$E_{00}={\displaystyle \frac{qh}{4\pi }}\sqrt{{\displaystyle \frac{N_{\mathrm{S}\mathrm{i}}}{{\epsilon }_{\mathrm{S}\mathrm{i}}{m}_t}}}$$

(2)

$$c_1={\displaystyle \frac{\mathrm{l}\mathrm{n}\left(\frac{4q{\varphi }_b}{E_f}\right)}{2·E_{00}}}$$

(3)

The h, N_Si, m_t, and E_f represent the Plank constant, doping concentration of silicon, effective tunneling mass, and Fermi level of silicon, respectively. Here, m_t is set to 0.19∙m₀ [28]. Although an ideal SBH between TiSi₂ and n-Si is 0.6 eV [29], it decreases due to a barrier lowering (Δϕ_b) caused by image force expressed as Equations (4) and (5) [30].

$$∆{\varphi }_b=\sqrt{{\displaystyle \frac{q{E}_{\mathrm{m}\mathrm{a}\mathrm{x}}}{4\pi {\epsilon }_{\mathrm{S}\mathrm{i}}}}}$$

(4)

$$E_{\mathrm{m}\mathrm{a}\mathrm{x}}=\sqrt{{\displaystyle \frac{2q{N}_{\mathrm{S}\mathrm{i}}{\psi }_{\mathrm{S}\mathrm{i}}}{{\epsilon }_{\mathrm{S}\mathrm{i}}}}}$$

(5)

The E_max and ψ_Si represent the maximum electric field and surface potential at the silicon region, respectively. Based on Equations (1) to (5), Figure 5a,b shows the calculated Δϕ_b and ρ_c as a function of N_Si, respectively. Considering N_Si of the fabricated sample is ~3 × 10²⁰ cm⁻³ (Figure 2), it corresponds to the 0.29 eV-Δϕ_b, resulting in a 0.31 eV effective ϕ_b in Equations (1) and (3) at the TiSi₂/n⁺ Si interface. Consequently, the theoretical ρ_c is ~1.05 × 10⁻⁸ Ω∙cm², which is used as a reference value for the evaluation of measurement results [Figure 5b].

5. Results and Discussion

5.1. Layout Comparison

Figure 6a,b shows the measured R_c and ρ_c for layout #1 and #2 as a function of A_c with 1 μm- δ. The R_c of layout #2 is lower than that of layout #1 across all A_c, resulting in approximately an order of magnitude lower ρ_c compared to layout #1. The design parameters of layout #1 and #2 are identical, as shown in Table 1, except for the size of W. It indicates that a narrower W in layout #2 effectively constrains the current path, suppressing current crowding and decreasing the parasitic voltage drop in V₁₃. Figure 6c shows the simulated plan-view current density distribution of both layouts, providing direct evidence of this improvement. Compared to layout #1, layout #2 confines the current path toward the contact hole, which leads to an accurate contact resistance measurement.

5.2. Contact Hole Area (A_c) Variation

Despite the improvement of measurement accuracy in layout #2, the measured ρ_c is much higher than the theoretical ρ_c at A_c above 1 μm². On the other hand, the measured ρ_c is almost the same as the theoretical ρ_c when the A_c is less than 0.25 μm² [Figure 6b]. In other words, the measurement errors significantly decrease with the smaller A_c. This result indicates that the actual area contributing to the R_c is smaller than the A_c for the large A_c, causing significant measurement errors during the ρ_c extraction. The current from n⁺ Si to TiSi₂ does not flow uniformly across the A_c but flows toward the contact edge where the path resistance is lowest. The current density reduces away from the edge since the resistance consisting of R_sh and ρ_c along the contact hole increases. Therefore, the voltage drop V₁₃ peaks at the edge and then exponentially decreases [Figure 7a]. This decay length, at which the voltage drop decreases to 1/e of its peak value, is defined as transfer length (L_T) and determined by the ρ_c and R_sh (i.e., $L_T=\sqrt{{\rho }_c/R_{sh}}$) [26]. Therefore, the effective contact hole area (A_{c, eff}), where the voltage drop V₁₃ occurs, is expressed as the multiplication of L_T and L (i.e., A_{c, eff} = L_T ∙ L). Using the theoretical ρ_c and measured R_sh of TiSi₂ [Figure 3a], L_T is calculated to be 0.55 μm. For A_c-0.25 μm², where L is smaller than L_T, the voltage drop V₁₃ occurs across the entire A_c. However, when L becomes larger than L_T, the voltage drop V₁₃ is confined within L_T, causing measurement errors during ρ_c extraction [Figure 7b]. Therefore, L should be designed smaller than the L_T to minimize the measurement errors caused by the mismatch between A_c and A_{c, eff}.

5.3. Align Margin (δ) Variation

Figure 8a shows the measured ρ_c as a function of δ for layouts #1 and #2 with A_c of 0.25 μm². Layout #1 shows the measured ρ_c an order of magnitude higher than the theoretical ρ_c across all δ values due to the large W, which fails to constrain the current path, as discussed in Section 5.1. Layout #2 shows the measured ρ_c close to the theoretical ρ_c for δ from 3 μm to 1 μm. However, the measured ρ_c increases by an order of magnitude when δ decreases below 0.5 μm. This phenomenon is due to the recessed TiSi₂ formation at the contact hole region. Figure 8b shows the simulated current density distribution for δ of 0.2 μm and 1 μm in layout #2. At δ of 0.2 μm, current concentrates within the narrow δ region, resulting in high current density near the recessed TiSi₂ region. In contrast, at δ of 1 μm, current disperses over a wide δ region, exhibiting low current density near the recessed TiSi₂ region. Although V₁₃ should measure only the voltage drop at the contact interface, this high current density at the semiconductor region for small δ introduces additional parasitic voltage to V₁₃, causing significant measurement errors. In contrast to the prior research showing that narrowing δ suppresses the current crowding and reduces measurement error [19], our results demonstrate that with Ti silicidation, narrowing δ increases the current crowding and measurement errors. While improved measurement accuracy is achieved at δ of 2 μm and 3 μm, the average value of measured ρ_c is most close to the theoretical ρ_c at δ of 1 μm. Also, considering layout area efficiency, a δ of 1 μm is optimal.

6. Conclusions

In this study, contact resistance measurements between TiSi₂ and n⁺ Si are performed using various CBKR test pattern layout designs with evaluation of layout-dependent errors. The theoretical ρ_c is calculated to be ~1.05 × 10⁻⁸ Ω∙cm² as a function of N_si and Δϕ_b. A modified CBKR design with narrow W (layout #2) shows improvement in measurement accuracy compared to the conventional layout (layout #1) by confined current path. Investigation of A_c variations shows that accurate ρ_c extraction can be achieved when L is designed smaller than L_T, as demonstrated with A_c-0.25 μm² since the entire A_c contributes to the voltage drop of R_c. Also, investigation of δ variations shows that recessed TiSi₂ formation affects current distribution near the contact region. At δ of 1 μm, current disperses over a wide area, while at smaller δ, current concentrates near the recessed TiSi₂ region, introducing parasitic voltage in V₁₃ measurement. The optimized layout #2 with δ-1 μm and A_c-0.25 μm² achieves ρ_c measurements closely aligned with theoretical ρ_c, demonstrating the elimination of layout-dependent measurement errors between TiSi₂ and n⁺ Si contact resistance characterization.