A 5-Transistor CMOS Voltage Reference with Double Supply-Regulation

Abstract

This paper presents an ultra-low-power CMOS voltage reference designed and verified in an 180 nm standard CMOS technology. To achieve DC and AC supply sensitivity under 0.01%/V and −100 dB, it employs a single transistor and two 2-T cores to improve supply immunity with minimal overhead, adding only one drain-to-source voltage for the total supply voltage. The proposed design achieves a line sensitivity of 0.0027%/V in a supply voltage range of 0.5 V to 2 V and consumes 630 pW with a supply voltage of 0.5 V. The simulated temperature coefficient is 12 ppm/°C in a temperature range of −40 °C to 150 °C, and the simulated power supply rejection ratio is −100.5 dB at 100 Hz without requiring any output decoupling capacitor.

1. Introduction

The rapid advancement of sensor technology has enabled various applications, including the Internet of Things (IoT) nodes and portable electronics. However, these applications often operate in energy-constrained environments where power availability is limited, requiring ultra-low-power operation. Voltage references, as essential building blocks for generating internal biases, must maintain accurate and stable outputs while consuming minimal power to extend system longevity. In addition to low power, such systems require voltage sources with low supply voltage dependency, as the supply voltage can fluctuate significantly due to power/data transfer activities, energy harvesting variations, or external interferences.

Voltage reference can be categorized into three types: bandgap reference (BGR) [1,2], hybrid reference (HR) [3,4], and CMOS reference (CR) [5,6,7,8,9,10,11,12]. In BGR and HR circuits, the reference voltage is generated by adding a proportional-to-absolute-temperature (PTAT) voltage to a complementary-to-absolute-temperature (CTAT) voltage of a BJT, effectively canceling out temperature variation. While BGR and HR topologies offer strong immunity to process, voltage, and temperature (PVT) variations, their reliance on BJTs limits their adoption in supply voltage-constrained environments.

As an alternative, CRs address this limitation by operating the transistor in the subthreshold region and exploiting the threshold voltages as a reference instead of the silicon bandgap voltage. Ref. [5] presents a 2-transistor (2-T)-based voltage reference that generates a reference voltage based on the threshold difference of two different transistor types. This approach achieves power consumption under nanowatt-level while maintaining the conventional requirement such as temperature coefficient (TC) and minimum supply voltage.

However, dc and ac supply stability, determined by the intrinsic gain of the transistors, may deteriorate when the reference voltage is scaled up [6] or when the circuit is implemented in recent technology nodes [7].

Various methods have been proposed to suppress the supply dependency [8,9,10,11]. Ref. [8] employed a low-impedance diode-connected transistor to mitigate the impact of the supply voltage on the reference core, albeit at the cost of significantly higher power consumption compared to 2-T reference. Refs. [9,10] proposed a current subtraction path to compensate for supply dependency, requiring trimming or output decoupling capacitor. Ref. [11] duplicated three 2-T cores to regulate the effective supply voltage, though its power supply rejection ratio (PSRR) remains unverified. Ref. [12] proposed a gate-leakage-based TC compensation and a diode-connected voltage divider to alleviate the temperature dependence, but this approach introduces increased costs for trimming options.

This paper presents an ultra-low-power CMOS voltage reference that utilizes a single transistor and two 2-T cores to enhance the supply immunity with minimal overhead, requiring only the additional drain-to-source voltage for the overall supply voltage. The overall circuit, implemented using a total of five transistors (5-T), is designed and verified in a 180 nm standard CMOS technology. The proposed circuit consumes 630 pW at a supply voltage of 0.5 V, achieving a line sensitivity (LS) of 0.0027%/V across a supply voltage range of 0.5 V to 2 V and a PSRR of −100.5 dB at 100 Hz without requiring any decoupling capacitor. The TC of the proposed circuit is 12 ppm/°C over a temperature range of −40 °C to 150 °C.

The remainder of this paper is organized as follows: Section 2 describes the proposed double regulation method and compares it with the conventional 2-T CR. Section 3 presents the simulation results, demonstrating the performance improvements. Finally, Section 4 concludes the paper.

2. Proposed CR with Double Supply Regulation and Post-Layout Simulation Results on Supply Variations

Figure 1 illustrates the overall circuit diagrams of the conventional 2-T CR [5] and the proposed 5-T CR. By equating the subthreshold current equations of two transistors in Figure 1a, the reference voltage of the conventional 2-T CR, V_REF,CONV, can be expressed as

$$V_{REF,CONV}=\left(V_{TH,B}-V_{TH,A}\right)+m_B{V}_T\mathit{ln}\left({\displaystyle \frac{W_A{L}_B}{W_B{L}_A}}\right),$$

(1)

where the subscripts A and B represent the parameters of M_A and M_B, respectively, and V_TH, V_T, and m denote the threshold voltage, thermal voltage, and subthreshold slope factor. In Equation (1), parameters such as mobility, oxide capacitance, and subthreshold slope factor are assumed to be identical for both transistors to simplify the equation. The optimum dimension ratio between M_A and M_B can be derived using the following equation [5]:

$${\displaystyle \frac{W_B{L}_A}{W_A{L}_B}}\cong e^{\left(C_{TH,B}-C_{TH,A}\right){\displaystyle \frac{T}{m_B{V}_T}}},$$

(2)

where C represents the first-order temperature dependency of the threshold voltage.

The proposed 5-T CR is depicted in Figure 1b. Based on the conventional 2-T core (M₁ and M₂), the first-regulated output, V₁, is used to provide an effective supply voltage for the second-2T core, V_DD,EFF, via a single transistor (M₃) operating as a source follower. This output is then further regulated by another 2-T core (M₄ and M₅) to generate the final reference voltage, V_REF,PROP. It is worth noting that the core operation of the proposed 5-T CR remains identical to that of the conventional 2-T CR, except for the double regulation process. Consequently, Equations (1) and (2) from the conventional 2-T CR can also be applied to the proposed design. In the proposed circuit, nominal transistors are used for M₂ and M₅, while native transistors are used for M₁, M_3, and M₄. Each body of the transistors is connected to the ground. The dimensions of all transistors are listed in

Table 1. Transistor dimensions of the proposed circuit.

Transistor	Width(μm)	Length(μm)	Current(pA)
M1 = MA	1.1	18	628
M2 = MB	15	18	628
M3	0.42	14	633
M4	1.13	18	633
M5	15	18	633

.

Figure 2 shows the small-signal models of the conventional 2-T CR (Figure 2a) and the proposed 5-T CR (Figure 2b), where g_m and r_o are the transconductance and output resistance of the transistors, respectively, with subscripts corresponding to individual transistors. Using Kirchhoff’s Law in Figure 2a, the supply sensitivity of the 2-T CR can be derived as follows:

$${\displaystyle \frac{V_{REF,CONV}}{V_{DD}}}\cong {\displaystyle \frac{1}{\left(g_{m,A}+g_{m,B}\right)r_{o,A}+1}}.$$

(3)

A similar approach can be applied to derive the equations for the proposed 5-T CR. The regulated voltage, V_DD,EFF, can be expressed as

$$V_{DD,EFF}\cong {\displaystyle \frac{\left(g_{m,3}{V}_{REF,CONV}+\frac{V_{DD}}{r_{o,3}}+g_{m,4}{V}_{REF,PROP}+\frac{V_{REF,PROP}}{r_{o,4}}\right)}{\left(\frac{g_{m,3}{r}_{o,3}{r}_{o,4}+r_{o,4}+r_{o,3}}{r_{o,3}{r}_{o,4}}\right)}}.$$

(4)

By substituting $V_{REF,CONV}$ from Equation (3) into Equation (4) and changing the subscripts A and B to 1 and 2, V_DD,EFF can be rearranged as

$$V_{DD,EFF}=\left(g_{m,3}{\displaystyle \frac{V_{DD}}{g_{m,1}{r}_{o,1}+g_{m,2}{r}_{o,1}+1}}+{\displaystyle \frac{V_{DD}}{r_{o,3}}}+g_{m,4}{V}_{REF,PROP}+{\displaystyle \frac{V_{REF,PROP}}{r_{o,4}}}\right)\times {\displaystyle \frac{r_{o,3}{r}_{o,4}}{g_{m,3}{r}_{o,3}{r}_{o,4}+r_{o,4}+r_{o,3}}}.$$

(5)

Additionally, the relationship between M₄ and M₅ can be written as

$$V_{REF,PROP}={\displaystyle \frac{\frac{1}{r_{o,4}}{V}_{DD,EFF}}{g_{m,4}+g_{m,5}+\frac{1}{r_{o,4}}}}.$$

(6)

Substituting $V_{DD,EFF}$ from Equation (5) into Equation (6), the final reference voltage, V_REF,PROP, can be derived as

$${\displaystyle \frac{V_{REF,PROP}}{V_{DD}}}={\displaystyle \frac{\left(g_{m,1}+g_{m,2}\right)r_{o,1}+g_{m,3}{r}_{o,3}}{g_{m,3}(g_{m,1}+g_{m,2}{\left)\right(g}_{m,4}+g_{m,5})r_{o,1}{r}_{o,3}{r}_{o,4}}}.$$

(7)

Assuming g_m,1 = g_m,a, g_{m,2 =} g_m,b, and r_o,1 = r_o,a, the supply stability ratio between the conventional 2-T and the proposed 5-T can be derived from Equations (3) and (7) as follows:

$${\displaystyle \frac{V_{REF,CONV}/V_{DD}}{V_{REF,PROP}/V_{DD}}}={\displaystyle \frac{1}{{(g}_{m,1}+g_{m,2})r_{o,1}}}/{\displaystyle \frac{\left(g_{m,1}+g_{m,2}\right)r_{o,1}+g_{m,3}{r}_{o,3}}{g_{m,3}\left(g_{m,1+}{g}_{m,2}\left)\right(g_{m,4+}{g}_{m,5}\right)r_{o,1}{r}_{o,3}{r}_{o,4}}}={\displaystyle \frac{g_{m,3}\left(g_{m,4+}{g}_{m,5}\right)r_{o,1}{r}_{o,3}{r}_{o,4}}{\left(g_{m,1}+g_{m,2}\right)r_{o,1}+g_{m,3}{r}_{o,3}}}.$$

(8)

Consequently, the supply sensitivity of the proposed 5-T CR is improved by approximately one order of magnitude, proportional to the intrinsic gain of a transistor (g_mr_o). In our design, the value calculated from Equation (8) is 85.8, which may vary depending on the transistor dimensions or level of flowing currents. The device parameters for each transistor in the proposed 5-T CR are listed in

Table 2. Device parameters of the transistors in the proposed 5-T CR.

Transistor	gm (nS)	ro (GΩ)
M1 = MA	20.98	27.9
M2 = MB	17.35	25.2
M3	20.51	18.9
M4	21.18	8.34
M5	17.51	25.1

. Since M₃ functions as a source follower and does not affect the core regulation process, its dimension is designed to be minimum to reduce the area cost.

Figure 3 compares the original supply voltage, V_DD, with the effective supply voltage, V_DD,EFF, after passing through the first 2-T core and M₃. Since the regulated supply is applied to the 2-T core, the proposed 5-T CR demonstrates superior LS compared to the conventional 2-T core. This improvement is quantified as g_mr_o, as shown in Figure 4. The simulated LS of the proposed 5-T CR is 0.0027%/V across a supply voltage range of 0.5 V to 2 V, greatly outperforming the conventional 2-T CR, which exhibits a LS of 0.304%/V over the same range.

The minimum supply voltage condition for the 2-T CR in Figure 1a can be written as

$$V_{DD,min,CONV}=V_{REF}+V_{DS,A},$$

(9)

whereas the minimum supply voltage for the proposed 5-T CR in Figure 1b is derived as

$$V_{DD,min,PROP}=V_{REF}+V_{DS,3}+V_{DS,4}=V_{DD,min,CONV}+V_{DS}.$$

(10)

For fair comparison, both designs were configured to dissipate the same amount of current per each branch. While the proposed 5-T CR consumes twice the current and requires a supply headroom of V_DS, LS achieves about 50 times better and PSRR achieves about 30 times better supply characteristics.

3. Post-Layout Simulation Results on Process and Temperature Variations

Figure 5 shows the simulated PSRR for each node voltage over a frequency range from 1 Hz to 100 MHz. By applying the pre-regulated voltage, V_DD,EFF, instead of the overall supply voltage, V_DD, to the 2-T core, the proposed 5-T CR achieves double regulation. The final reference voltage, V_REF,PROP, shows a PSRR of −100.5 dB at 100 Hz, which is an improvement of approximately −40 dB compared to the conventional 2-T CR. The dominant pole remains at the same frequency as that of the conventional 2-T CR.

Figure 6 illustrates temperature dependency of each node voltage. Through the modulated threshold voltage of the native transistor, M₃, the supply voltage, V_DD,EFF, for the 2-T core is successfully generated from the first regulated voltage, V₁. The TC of V_REF,PROP is 12 ppm/$°\mathrm{C}$ over a temperature range from −40 °C to 150 °C. Despite the significant suppression of the achieved supply variation, there is no penalty in temperature characteristics. Figure 7 shows the simulated temperature dependency of V_REF,PROP at different supply voltage levels. Thanks to the superior supply immunity, the overall shape and TC remain regardless of the supply voltage level.

To verify the inaccuracy of V_REF,PROP across multiple samples, a Monte Carlo simulation with 500 samples is performed, accounting for process, mismatch, and both (process and mismatch) variations, respectively. Figure 8a shows the distribution of V_REF,PROP, revealing an average of 184.9 mV and a standard deviation of 11.6 mV. Since V_REF,PROP is a function of threshold difference of two types of transistors, the main source for variation is the process variation. Figure 8b presents the statistical spread for TC, showing an average of 14.4 ppm/°C and a standard deviation of 6.1 ppm/°C. The worst-case and the best-case TCs are 30.9 ppm/°C and 4.33 ppm/°C, respectively. Figure 8c depicts the LS distribution at room temperature, showing an average of 0.00382%/V and a standard deviation of 0.0011%/mV. The worst-case and the best-case LS values are 0.0022%/V and 0.0075%/V, respectively. Figure 9 demonstrates an exemplary layout of the proposed 5-T CR, with an active area of 787.3 µm² (18.7 µm × 42.1 µm).

Table 3. Comparison table with previously reported CRs.

	This Work	[5]	[6]	[7]	[8]	[9]	[10]	[11]	[12]
Technology (nm)	180	180	180	180	130	40	180	65	65
VDD (V)	0.5–2	0.5–3	1.4–3.6	0.4–1.8	0.5–1.8	0.9–1.5	0.5–2.1	0.5–1.8	0.4–2.5
VREF (V)	0.17	0.18	1.25	0.15	0.18	0.58	0.19	0.26	0.28
Temp. Range (°C)	−40~150	−20~80	0~100	−40~150	−20~80	−40~150	0~100	0~100	−10~155
TC (ppm/°C)	12	16.9	23	89.8	29*	18*	26.7	78.4	15.9 *
LS (%/V)	0.0027	0.033	0.31	0.163	0.036	0.23	17.1	0.02	0.08
PSRR (dB) Freq. (Hz)	−100.5 @100	−53 @100	−41 @100	−55 @100	−50.5 @10	−72 @1M	−72 @10	N/A N/A	−76.7 @100
Power (pW)	630	2.22	35	1000	2.2	4200	28.8	14.3	53.8

* Trimmed.

summarizes and compares the performance of the proposed 5-T CR with recently reported voltage references. Figure 10 compares the performances of the previously reported CRs and the proposed CR by visualizing the TC against the maximum operating temperature and the LS against the minimum supply voltage.

4. Conclusions

This paper presented a CR optimized for ultra-low-power applications, with improvements in LS and PSRR achieved using only five transistors, without any penalty in TC. The circuit was designed and verified in an 180 nm standard CMOS technology, generating a reference voltage of 169 mV and consuming only 630 pW under nominal conditions. It achieves an average TC of 12 ppm/°C over a temperature range of −40 °C to 150 °C and an average LS of 0.0027%/V across a supply voltage range of 0.5 V to 2 V at room temperature. The simulated PSRR is −100.5 dB at the 100 Hz and at a minimum operating supply voltage of 0.5 V. The proposed CR is suitable for energy-constrained electronics such as IoT systems, where accuracy against PVT variations and ultra-low power operation is critical.