Overcoming Printed Circuit Board Limitations in an Energy Harvester with Amplitude Shift Keying and Pulse Width Modulation Communication Decoder Using Practical Design Solutions

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

Author needs to modify the abstract with numerical analysis of the proposed work, the abstract seems to be a description of the advantages of the proposed work, which can be simply described in the introduction.

A reduction in development time has been described by the author. Is there any analysis of the time complexity involved?

There is too much lengthy discussion in reference paper 7. In the literature review, it is important to describe the existing work and its limitations.

Author should reduce reference paper 7's description and add other relevant references.

Communication schemes can be categorized in a shared-channel SWIPT system as single modulation or double modulation [7]. There is no consistency between this sentence and the description. The sentence should begin at the beginning of the second graph.

Same reference paper repeated so many times, such as [2], [7]. It is not required.

How could inductive ripples be reduced by using smaller capacitors instead of one large capacitor?

What are the limitations of this approach regarding response time?

What is the specific purpose of the potentiometer in the inverter when decoding PWM?

As a result of the addition of a series resistor in the communication path's rectifier, signal attenuation could be introduced. How is that avoided so that reliable decoding of data can be ensured?

 

PCBs are made from FR-4 substrates. Why was this chosen? A range of alternative materials was considered, especially those with lower losses at 924 MHz.

Author Response

Comment 1: Author needs to modify the abstract with numerical analysis of the proposed work, the abstract seems to be a description of the advantages of the proposed work, which can be simply described in the introduction.

Response 1: Dear reviewer, thank you greatly for the comment provided regarding the abstract. Indeed, the abstract was missing a great deal of numerical analysis regarding PCE, separation distance, and power consumption. We have added such information in the abstract.

 

Comment 2: A reduction in development time has been described by the author. Is there any analysis of the time complexity involved?

Response 2: Thank you for your insightful and critical comment, dear reviewer. We greatly appreciate your input, which has allowed us to refine the paper further. Since development time primarily relies on the difference between implementing the system on ICs versus PCBs, we have emphasized the timing advantages of PCB implementation for this specific system in comparison to IC realization. Our system, based on the provided design methodology, can be designed within one week, manufactured in another week, and requires only one day for soldering and one day for testing, resulting in a total implementation period of 16 days. In contrast, IC realization demands significantly more time due to the complexity of the layout and the need to meet complex design rules. IC design typically requires 2 to 6 months, with the tape out process alone taking approximately 10 weeks. Additionally, packaging the IC involves specialized wire bonding equipment and often requires sending the die to a packaging company. Based on these factors, the IC implementation process can take anywhere from 6 months to 1 year. While we agree that IC realization is more suitable for mass production, PCB implementation offers a clear advantage for rapid prototyping due to its significantly shorter development cycle. We have incorporated a summary of this discussion into the manuscript, highlighted for your convenience in ²yellow (page 3). Thank you once again for your valuable feedback.

 

Comment 3: There is too much lengthy discussion in reference paper 7. In the literature review, it is important to describe the existing work and its limitations.

Response 3: Thank you for the comment dear reviewer, we have reduced the usage of reference 7 in the manuscript and added several other references. As for the limitations of existing work, it is described in the paragraph of ³yellow (page 3). The main limitation is the slow prototyping phase of the IC compared to PCB solution. In addition to the costs of IC manufacturing compared to PCB production.

 

Comment 4: Author should reduce reference paper 7's description and add other relevant references.

Response 4: Thank you for bringing this issue to our attention, dear reviewer. Indeed, we have relied significantly on reference 7 in our study. To strengthen our discussion, we have conducted additional research on papers addressing the operation and performance metrics of the different modulation techniques, which led us to identify and add three relevant references [8][9][10]. These additions are highlighted in ⁴yellow (page 2).

 

Comment 5: Communication schemes can be categorized in a shared-channel SWIPT system as single modulation or double modulation [7]. There is no consistency between this sentence and the description. The sentence should begin at the beginning of the second graph.

Response 5: Thank you for identifying this issue, dear reviewer. We have restructured the end of the first paragraph and integrated it into the second paragraph to improve coherence. The adjusted sections are highlighted in ⁵yellow (page 1).

 

Comment 6: Same reference paper repeated so many times, such as [2], [7]. It is not required.

Response 6: Thank you, dear reviewer, for pointing out the redundancy in the cited references. We have addressed this by removing the repeated references to enhance the quality of the paper.

 

Comment 7: How could inductive ripples be reduced by using smaller capacitors instead of one large capacitor?

Response 7: Thank you for your question, dear reviewer. Using a single capacitor creates a highly inductive path from the capacitor through the via to the ground plane, leading to significant RF voltage at the output. Since the issue arises from the inductive path, increasing the size of the capacitor does not reduce such leakage. However, adding multiple capacitors in parallel mitigates the inductive impact by shunting multiple inductive paths in parallel, thereby reducing voltage variations at the output of the harvester. The reduction in the sizes of the parallel capacitors is done to match the equivalent loading capacitance of a single large capacitor, ensuring consistency in the analysis. To clarify this mechanism further, we have expanded the discussion in the manuscript and included a plot showing the relationship between the number of capacitors and the resulting voltage ripples at the output (Figure 5), highlighted in ^7&13yellow (pages 6,7,8,9). We sincerely appreciate your valuable feedback, which has helped us enhance the clarity and depth of our explanation.

 

Comment 8: What are the limitations of this approach regarding response time?

Response 8: Thank you for the comment dear reviewer. The response time in our system is determined by two main factors: the start-up time and the transition time from idle mode to to transmission mode. For the start-up phase: The harvester requires approximately 5 µs to reach its steady-state value due to the small time constant at its output. The communication rectifier, with a significantly higher time constant, requires around 0.2 ms to reach the appropriate operating conditions for ASK demodulation, as shown in Figure 10(b) and 10(c). Lastly, the regulator’s time constant contributes a 0.2 ms in our design. For the transition from idle state to data transmission state, at least two consecutive “0” bits are needed as a preamble to enable the VCM to reach correct voltage level and decode incoming data. At a bitrate of 15 kbps, this corresponds to a duration of approximately 0.13 ms. We have included additional discussion on response time in the revised manuscript, with updates highlighted in ⁸yellow (page 12). 

Comment 9: What is the specific purpose of the potentiometer in the inverter when decoding PWM?

Response 9:  Dear reviewer, thank you for this crucial comment. The potentiometer serves an important role in PWM decoding by allowing adjustments to the charging time at the output of the skewing inverter. This adjustment is needed when reconfiguring the bit rate, as it ensures the skewing inverter's charging time is modified appropriately for successful decoding. We have expanded the discussion in the manuscript to provide more details on the importance of the potentiometer in this context, highlighted in ⁹yellow (page 14). Thank you for bringing attention to this critical part.

Comment 10: As a result of the addition of a series resistor in the communication path's rectifier, signal attenuation could be introduced. How is that avoided so that reliable decoding of data can be ensured?

Response 10: Thank you for this important comment, dear reviewer. Although signal attenuation complicates receiver demodulation, it is highly necessary to include this series resistance to provide this signal attenuation. The series resistor serves a critical role in signal attenuation for two key reasons. First, it ensures that RF power is primarily directed toward the harvester path, minimizing power leakage into the communication path. This helps maintain a high PCE in the harvester path, especially when adjusting the time constant at the output of the communication’s path rectifier. Second, the series resistor reduces the voltage to within the ICMR range of the comparator (0 to 2V in this work). In this design, the comparator operates in an open-loop configuration to provide significant voltage amplification for successful ASK signal demodulation. Additionally, we incorporated an auxiliary comparator to ensure the output produces a smooth clock (CLK) signal. We have expanded the discussion in the manuscript to clarify the impact of the series resistor, its necessity for signal attenuation, and the approach used to ensure effective signal amplification and demodulation. The expanded information is provided in ¹⁰yellow (pages 3,10,11). Thank you again for your valuable feedback.

Comment 11: PCBs are made from FR-4 substrates. Why was this chosen? A range of alternative materials was considered, especially those with lower losses at 924 MHz.

Response 11: Thank you, dear reviewer, for your question regarding our choice of using the FR4 substrate. While FR4 substrates have a higher loss factor compared to other materials at the designed frequency, our decision was driven by the need to balance rapid implementation and cost efficiency without significantly compromising performance. FR4 substrates are highly economical, with costs ranging from $4–$8 for approximately 10 copies, making them a practical choice for prototyping. In contrast, Rogers substrates, which offer a lower loss factor, are considerably more expensive, costing between $100 and $1,000 for the same quantity. This substantial cost difference, aligned with our objectives of this research, motivated the use of FR4 substrates for this work. We have added a detailed explanation in the manuscript (¹¹yellow ) (page 14) to clarify our reasoning for choosing the FR4 substrate.

Reviewer 2 Report

Comments and Suggestions for Authors

The manuscript presents "Overcoming PCB Limitations of an Energy Harvester with ASK-PWM Communication Decoder using Novel Design Solutions." Following are my comments and suggestions.

[1] In the title, it is recommended to remove the word 'novel' as it is purely subjective and does not provide meaningful information.

[2] It is necessary to include a relevant theory about ripple reduction using parallel smaller capacitors.

[3] Using a series resistor negatively impact the circuit performance in terms of noise response and signal loss. What is the guideline for a balanced resistance?

[4] What is the measured impedance matching for different modes (harvesting vs receiver)?

[5] What is the measured PCE of the harvesting path only with and without the power consumption of the regulator? Please include PCE numbers in Table 1.

Author Response

Comment 1: In the title, it is recommended to remove the word 'novel' as it is purely subjective and does not provide meaningful information.

Response 1: Dear Reviewer, thank you for the comment. We have removed the word “novel” and replaced it with “Practical” since it adds an objective tone to the title.

 

Comment 2: It is necessary to include a relevant theory about ripple reduction using parallel smaller capacitors.

Response 2: Thank you for your critical and constructive comment dear reviewer. In response, we have expanded the theoretical analysis and discussion to strengthen the simulations and enhance the overall quality of the paper. Specifically, we have derived and included the transfer function of the output filter, demonstrating the impact of the parasitic inductor on RF voltage leakage into the output. This analysis highlights the necessity of adding parallel capacitances at the filter’s output to mitigate the inductive effect, thereby improving RF rejection at the harvester output. These adjustments have been incorporated into the revised manuscript, with the relevant sections highlighted in ^7&13yellow (pages 6, 7, 8).

 

Comment 3: Using a series resistor negatively impact the circuit performance in terms of noise response and signal loss. What is the guideline for a balanced resistance?

Response 3: Thank you for your insightful comment, dear reviewer, which allowed us to clarify how to select an appropriate value for the series resistance. The chosen resistance must maintain isolation to maximize power conversion efficiency (PCE) at the harvester side, while ensuring the voltage is reduced suitably for Comp1. We have elaborated on the method for determining the optimal series resistance in the revised manuscript, with the relevant text highlighted in ¹⁴yellow (page 11).

 

Comment 4: What is the measured impedance matching for different modes (harvesting vs receiver)?

Response 4: Thank you for the question dear reviewer. Due to the large-signal operation of the harvester, we only resided to simulating the matching conditions and then refining the matching conditions experimentally via adjust the matching capacitor and inductor to maximize PCE. By adding the series resistance in the communication path’s rectifier, we have guaranteed minimal power to be received by the communication path while the harvesting path receives all if not most of the power. As a result, the matching network values in Figure 3 (a) are very similar to those in Figure 6. We added a brief discussion highlighting this in ¹⁵yellow (page 9).

 

Comment 5: What is the measured PCE of the harvesting path only with and without the power consumption of the regulator? Please include PCE numbers in Table 1.

Response 5: Thank you for the critical comment dear reviewer. In order to ensure consistency between PCE measurements with and without the regulator, we have used a reference output power of 2 mW. As for the case without regulator. Co-simulations efficiency of providing 2 mW to the load was given by 51%, while the measured one was 42.12 %. As for the case with regulator, the efficiency was 12.8 % which is expected to be low due to the voltage drop between the harvested voltage and the regulated one. To maintain correct envelope range, the harvested voltage needs to be higher than the regulated one. We included these numbers into the manuscript, highlighted in ¹⁶yellow (page 11). Additionally, we added the measured PCE to table 1 compared with literature PCEs.

 

Reviewer 3 Report

Comments and Suggestions for Authors

1. The authors claim - As of this date, no work has been done to achieve such an option. 101 The state-of-the-art did not present a detailed design approach for the energy harvester 102 with an ASK-PWM decoder. - However, there are a few studies reported on ASK-PWM WPT technology. For example, https://ieeexplore.ieee.org/abstract/document/10215978 reports this idea. Please perform a thorough literature survey and explain the findings, drawbacks, and challenges from previous studies. 

2. Three challenges were faced when attempting to realize this system in a discrete fashion - Were these challenges observed in your work or previous work by other authors? Please clarify the challenges in the state-of-the-art studies and how your design aims to resolve those challenges. 

3. Figure 3a does not show the 1.3 nH inductor. Please update the figure accordingly. 

4. After this identification, we split the 600 pF capacitor into 6x100 pF capacitors in parallel, as shown in Figure 4 (b).- Why was this capacitance split by 6? Would a factor of 4 or 2 suffice? Please show the simulation results for various splitting factors to prove the optimized results. 

5. Please add a plot that shows the amount of power harvested vs distance to demonstrate that 12 cm was the separation distance.

Author Response

Comment 1: The authors claim - As of this date, no work has been done to achieve such an option. 101 The state-of-the-art did not present a detailed design approach for the energy harvester 102 with an ASK-PWM decoder. - However, there are a few studies reported on ASK-PWM WPT technology. For example, https://ieeexplore.ieee.org/abstract/document/10215978 reports this idea. Please perform a thorough literature survey and explain the findings, drawbacks, and challenges from previous studies. 

Response 1: Thank you for the comment dear reviewer. It is true that ASK-PWM has been discussed to large extent in the literature. However, the contribution of this work is highlighted in capabilities of prototyping an energy harvesting with ASK-PWM communication decoding on FR4 PCB using commercial components. In the literature, all of the work was done using an IC prototype which can be costly, complex and require a long development time.  The drawbacks are highlighted in ³yellow (page 3). In the mentioned literature, detailed analysis was not presented. In the current text, we have presented details analysis and simulations of interfacing ASK-PWM with a harvester and how to design the several time constants in the system.

 

Comment 2: Three challenges were faced when attempting to realize this system in a discrete fashion - Were these challenges observed in your work or previous work by other authors? Please clarify the challenges in the state-of-the-art studies and how your design aims to resolve those challenges. 

Response 2: Thank you for the comment dear reviewer. Since this is a first-time attempt to prototype a harvesting ASK-PWM PCB with commercial components, the challenges were faced in our work. The large inductive traces, the inability to adjust the current flowing through the communication path by adjusting the transistor’s sizing, and the inability to adjust the length of the transistor to perform skewing operation; are all issues that exhibit themselves in PCB design, not in an IC realization. The addressed problems and solutions are highlighted in ¹⁸yellow (page 3).

 

Comment 3: Figure 3a does not show the 1.3 nH inductor. Please update the figure accordingly.

Response 3: Thank you dear reviewer for highlighting the missing inductor, we have updated the figure and added the component within the text, highlighted in ¹⁹yellow (pages 6, 7).

 

Comment 4: After this identification, we split the 600 pF capacitor into 6x100 pF capacitors in parallel, as shown in Figure 4 (b).- Why was this capacitance split by 6? Would a factor of 4 or 2 suffice? Please show the simulation results for various splitting factors to prove the optimized results. 

Response 4: Thank you for your valuable comment, which has helped us further enhance the quality of the paper. In response, we have included a plot illustrating the relationship between the number of capacitive paths and the RF voltage present at the output (Figure 5). Additionally, we have provided a detailed explanation of our choice to use six shunt capacitive branches. This configuration achieves a balance between a compact implementation and minimal voltage ripple. Beyond this point, adding additional branches yields diminishing improvements. The added discussion has been incorporated into the revised manuscript and is highlighted in ²⁰yellow (pages 8, 9).

 

Comment 5: Please add a plot that shows the amount of power harvested vs distance to demonstrate that 12 cm was the separation distance.

Response 5: Thank you, dear reviewer, for highlighting the need for further discussion on separation distance. We have provided a plot of harvested power and minimum peak harvested voltage vs. distance in Figure 13 (f). We provided a more detailed discussion on the separation distances and their limits in the manuscript. We have taken the word “up to 12 cm” and replaced with the range the system was validated on which is “6 cm to 12 cm”. 6 cm was the minimum distance we were able to do the measurements on due to the thickness of the antenna panels themselves, while beyond 12 cm, the system the regulator’s voltage drops below 2V due to the minimum peak harvested voltage dropping below 2 V. We have not clarified the distance at which the measurements were taken from which is 8 cm, a distance which the minimum peak envelope is maximized. The adjusted parts are highlighted in ²¹yellow (pages 15, 16).

Reviewer 4 Report

Comments and Suggestions for Authors

• 1.It is recommended to carefully examine the phase relationship between VCM and VENV. Additionally, the potential impact of multiple capacitors on signal accuracy should be thoroughly assessed, as this could have significant implications for the reliability of the results.

• 2.The paper would benefit from a broader evaluation of the system's linearity by testing multiple sets of symbols. Currently, the data provided is limited to the case of "100." Including analyses of other cases, such as "101," "110," and additional combinations, would provide a more comprehensive understanding of the system's behavior. The sensitivity of the system under these conditions is not clearly addressed and should be explored further.

• 3.The input signal strength is not explicitly discussed in the paper. Clarification is needed regarding whether the system can successfully demodulate weak signals, as this is critical for understanding the overall robustness of the system.

Author Response

Comment 1: It is recommended to carefully examine the phase relationship between VCM and VENV. Additionally, the potential impact of multiple capacitors on signal accuracy should be thoroughly assessed, as this could have significant implications for the reliability of the results.

Response 1: Dear reviewer, thank you for the comments provided which allowed us to improve the paper and its structure. Regarding the phase shift between VENV and VCM, we acknowledge that there can indeed be a phase difference of up to 90 degrees. However, this does not affect the reliability of CLK extraction. Since VCM is synthesized directly from VENV, they remain synchronized, making sure that the CLK signal is demodulated at the frequency of both VENV/VCM. For the use of multiple capacitors, we have made sure that the combined values of the smaller capacitors closely approximate the value of the larger capacitor. To minimize variations, we have selected capacitors with a low tolerance of 1%. Additionally, the different sections of multiple capacitors were designed to establish a good separation between specific time constants, allowing for reliable data decoding across a broad frequency range. In terms of energy harvesting reliability, the parallel capacitances help produce a smoother DC output voltage, thereby enhancing harvesting performance. To address these points more clearly in the paper, we have added further explanations, which are highlighted in ²²yellow (page 12) in the revised manuscript.

 

Comment 2: The paper would benefit from a broader evaluation of the system's linearity by testing multiple sets of symbols. Currently, the data provided is limited to the case of "100." Including analyses of other cases, such as "101," "110," and additional combinations, would provide a more comprehensive understanding of the system's behavior. The sensitivity of the system under these conditions is not clearly addressed and should be explored further.

Response 2: Thank you for your valuable comment. The choice of using “100” was made to simplify the presentation of the results in the paper. However, we conducted extensive testing with various symbols, and the system demonstrated correct operation regardless of the symbols used. This is attributed to the asynchronous nature of the data and clock recovery mechanism. We have attached here a screenshot of the oscilloscope showing the recovered DATA and CLK signals illustrating correct DATA and CLK bits successful extraction for different transmitted bit sequences. Additionally, we have added a statement in the revised manuscript to address this point, highlighted in ²³yellow (page 15).

Comment 3: The input signal strength is not explicitly discussed in the paper. Clarification is needed regarding whether the system can successfully demodulate weak signals, as this is critical for understanding the overall robustness of the system.

Response 3: Thank you for the comment dear reviewer. We have added more details about the amount of power transmitted, highlighted in ²⁴yellow (pages 15, 16). Additionally, to help define the limitations of our system in terms of signal strength, we have added Figure 13 (f), which highlights the maximum distance the system can decode signals correctly and its limiting factors. 

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The author has addressed all comments well in the revised manuscript.

Reviewer 2 Report

Comments and Suggestions for Authors

I have no more technical comments on the manuscript.

Reviewer 4 Report

Comments and Suggestions for Authors

No more questions.