Overcoming Printed Circuit Board Limitations in an Energy Harvester with Amplitude Shift Keying and Pulse Width Modulation Communication Decoder Using Practical Design Solutions

Abstract

This paper presents PCB design solutions for implementing a radiative-field RF energy harvester with an ASK-PWM decoding communication scheme using available commercial components. The paper provides the design approach and tackles key challenges such as the impact of inductive parasitic effects at the output of the harvester, how to maintain the $PCE$ at a constant value regardless of the time constant at the output of the communication path’s rectifier, and the difficulty of changing the aspect ratio of the discrete inverter used for PWM decoding. These challenges are addressed by using multiple capacitors connected in parallel at the output of the rectifier to reduce inductive parasitic effects, adding a series resistor in the communication path’s rectifier to isolate its loading from impacting the $PCE$, and utilizing a potentiometer in the inverter to realize PWM decoding on PCB. The system was manufactured using FR-4 substrate material with a size of 5 cm × 4 cm × 0.6 cm, harvesting energy at the ISM frequency of 924 MHz with a $PCE$ of $42.12\%$ at a bit rate of 15 Kbps. Moreover, the system consumes only 355 μW of power and maintains correct harvesting and decoding operation in the antenna separation range of 6–12 cm. This work aims to provide an alternative to IC realization by implementing the system entirely using commercial discrete components, reducing costs, adding flexibility, reducing development time, and allowing for simple debugging.

1. Introduction

Simultaneous Wireless Information and Power Transfer (SWIPT) has attracted a plethora of attention in the recent literature as a mechanism used for powering up and communicating with standalone devices such as Internet-of-Things (IoT), biomedical implants, electric vehicles, and underwater applications [1,2,3,4,5,6]. This concept brings about removing power and data wired connectivity, improving flexibility, and removing the need for batteries for the system. SWIPT is based on the combination of two technologies. The first is Wireless Power Transfer (WPT), which transfers RF power wirelessly from a dedicated source or ambience to the receiver, from which the RF power is converted to DC to power up said receiver. This power transfer can be performed in the near field using inductive links or radiative fields using antennas. The second is Wireless Information Transfer (WIT), which is based on the modulation and demodulation of the RF signal to transfer data wirelessly. This combination can be in a separate-channel scheme where the power and data are orthogonal to each other, which would make them unimpacted by one another at the expense of increased area of implementation, or it can be in a shared-channel scheme, which improves compactness at the cost of performance reduction [2,3].

Communication schemes can be categorized in a shared-channel SWIPT system as single modulation or double modulation. Amplitude Shift Keying (ASK), On–Off Keying (OOK), Frequency Shift Keying (FSK), and Phase Shift Keying (PSK) are all examples of single modulation category. In ASK, the modulating carrier is shifted high and low according to the data bits at the input of the modulator. This modulated signal can be demodulated in a coherent (synchronous) way using clock-generating circuitry and a Phase-Locked Loop (PLL) at the receiver side or in a noncoherent (asynchronous) way using an envelope detector, which removes the need for the clock generation and PLL circuitries [7]. Noncoherent ASK in SWIPT brings the advantages of low complexity, low power consumption, and the removal of phase detection. However, the disadvantages are impacted performance due to the continuously varying power envelope of the RF power, which would impact the power transfer efficiency and low data rate compared to FSK and PSK [8]. OOK is similar to ASK but with a modulation index of 100%. This scheme simplifies the receiver structure even more compared to ASK due to the wide range between bits “1” and “0”, but for WPT purposes, it is inefficient since during data transmission of bit “0”, power is discontinued from the receiver. FSK and PSK are based on digitally changing the frequency and phase of the modulating signal to change the data bits. Both FSK and PSK require phase detection and clock-generating circuitries, which would increase the power consumption, area utilization, and receiver complexity. Also, FSK and PSK are usually incorporated with Gaussian filtering and differential signaling, respectively, adding to the receiver’s complexity, area utilization, and power consumption [9]. FSK and PSK have high data rates and constant power envelope advantages, whereas the latter advantage is suitable for WPT. However, the cons of FSK and PSK outweigh the pros in terms of WPT performance.

Instead of a single modulation scheme, a double modulation scheme can be used to gain more advantages, such as asynchronous clock extraction and improved receiver functionality [10]. This led to an emerging double-modulation scheme in the recent literature used heavily in short-range SWIPT systems for biomedical applications: Amplitude Shift Keying with Pulse Width Modulation (ASK-PWM). Instead of using ASK for data decoding, the ASK signal is demodulated to extract the asynchronous clock from the ASK-PWM signal. At the same time, the PWM is decoded to extract the data based on the digital pulse width of the decoded ASK signal. ASK-PWM maintains the advantages of noncoherent ASK demodulation regarding receiver complexity, area reduction, and power consumption. Also, when limiting the ASK modulation index within 5–10% of the RF power envelope, the RF power envelope will not change drastically in a way that would impact power efficiency and would also maintain a good room for demodulating the ASK signal, reducing the Bit Error Rate (BER) [11].

Earlier work in the literature has utilized ASK-PWM SWIPT, primarily focusing on Integrated Circuit (IC) implementation for biomedical applications. In [11], an 11 μW transceiver was presented for powering and communicating with implantable devices. The IC was fabricated using a 65 nm process and utilized ASK-PWM at a reconfigurable data rate between 4 and 20 Mbps; it also used an off-chip antenna at the frequency of 1.32 GHz at a separation of 3.5 cm from a 125 mW transmitting antenna. In [12], a 13.56 MHz inductively coupled WPT system was presented. It used a hybrid organic/metal oxide process to achieve a bit rate of 75 bits/s using ASK-PWM with a size of 11 × 11 cm for organic applications. A 4.5 μW 3-channel wireless intra-cardiac acquisition system was presented in [13]. The system was implemented using a 180 nm process, inductively coupled WPT at 13.56 MHz with a data rate of 88.3 Kbps. In [14], an implantable device capable of locomotion in a fluid medium was implemented using a 65 nm process. It received 500 μW power from a 2 W source at a frequency of 1.86 GHz with a separation distance of 5 cm at a data rate of 2.5–25 Mbps using ASK-PWM. A Silicon-on-Chip (SoC) WPT using magnetic induction with ASK-PWM scheme for the flexible dithering feature is presented in [15]. They used a 180 nm process to implement the system with a power consumption of 50 mW. In [16], a comparator-less ASK-PWM design for inductive coupling WPT was implemented. It used a frequency divider, frequency multiplier, and data sampler for clock and data recovery of ASK-PWM realized using a 180 nm process at a data rate of 2 Mbps. A cochlear implant system for stimulation using an 8-channel inductive link with ASK-PWM was presented in [17]. A custom chip was designed for the receiver part with a data rate of 120 Kbps at a total current consumption of 105 mA. A 900 MHz, inductively coupled ASK-PWM system with a 10 Mbps data rate is presented for brain implant purposes [18]. The system was composed of 32 ICs manufactured using a 65 nm process. A 180 nm SoC near field resonant inductive link with ASK-PWM at 40.68 MHz is presented in [19]. The system enabled up to 16 implantable stimulators at an 8 cm separation with a data rate of 10 Kbps, consuming 27 μW of power from a 2 W transmitter.

As seen from the state-of-the-art review, the focus was mainly on implementing an inductively coupled ASK-PWM WPT system implemented on an IC for biomedical applications. Although IC realization brings the advantages of miniaturization and high integration, it increases complexity, costs, inflexibility, and development time. For example, producing a PCB prototype typically requires 2–3 weeks, whereas an IC prototype takes 24–48 weeks. These disadvantages can be avoided by implementing the system entirely on PCB using commercially available discrete components. As of this date, no work has been conducted to achieve such an option. The state-of-the-art did not present a detailed design approach for the energy harvester with an ASK-PWM decoder.

Three challenges were faced when attempting to realize this system in a discrete fashion. The first was the parasitic inductor that existed at the output of the rectifier’s filter, which caused the RF to leak into the output regardless of the rectification capacitor’s value. The second challenge is that the Power Conversion Efficiency ($PCE$) value was impacted by the load resistance value at the output of the communication rectifier, which reduced the flexibility in changing the time constant of the communication filter. The last challenge was the inflexibility of changing the aspect ratio of the inverter’s discrete P-Field Effect Transistor (P-FET) in the PWM decoder to achieve the skewing operation necessary for successful data decoding. The first two solutions improve the performance of the discrete implementation, while the third one is critical to realize the system in a discrete fashion.

In this work, we implemented a fully discrete ASK-PWM energy harvesting system using commercially available components. The PCB is an FR-4 substrate of size 5 cm × 4 cm × 0.6 cm and harvests energy at the 924 MHz ISM frequency, while the ASK-PWM bit rate is at 15 Kbps. The contributions are highlighted in the complete discrete implementation of the system on PCB, its detailed design approach, and the solutions to the challenges exhibited in implementing such a system in a discrete format. These solutions and improvements are described as follows:

• The impact of the inductive parasitic effects was solved by splitting the big rectification capacitor at the output of the rectification filter into multiple smaller capacitors. This reduced the inductive contribution to a large extent, leading to a smoother DC output;
• A lossy resistor was added in series with the communication’s path rectifier to drop the amount of current in this path to a minimal value. This allowed the $PCE$ of the harvester’s path to remain at an almost constant value regardless of changes in the load value of the communication rectifier, adding flexibility in tuning the time constant of the communication filter;
• The aspect ratio inflexibility for the skewing operation was solved by adding a potentiometer between the P-FET drain terminal and the inverter output. The potentiometer controls and increases the time constant to achieve and set the correct level of the skewing operation.

Furthermore, commercial antennas were used to harvest radiative energy so that more applications can be targeted using this system other than biomedical applications, such as beamforming control systems, Wireless Sensor Networks (WSNs) powering, and wireless actuator control. The system was tested with an antenna separation distance of 6–12 cm.

The paper is structured as follows: Section 2 is the proposed circuit structure, and Section 3 contains the design approach split into four phases, including the proposed solutions and improvements. Section 4 presents the complete system’s PCB and its measurements under radiative-field operation for validating harvesting, data, and clock recovery. Section 5 is the conclusion.

2. Proposed Circuit Structure

The complete circuit structure of the energy harvesting ASK-PWM system implemented using discrete components on PCB is shown in Figure 1. Also, the figure annotates with dashed lines the proposed solutions and improvements highlighted in the list of the previous section with their corresponding numbers. The structure comprises four main blocks: the receive antenna (ANT), the matching network, the harvesting path, and the communication path.

The receive antenna here collects the RF power and the ASK-PWM modulation signal. This antenna has a characteristic resistance $R_0$. The matching network here was chosen to be a shunt capacitor $C_M$ series inductor $L_M$, which does not perturb the low-frequency ASK-PWM signal. This network provides good matching between $R_0$ and the input impedance of the harvester path. $L_M$ here also provides resonance peaking for the RF voltage suitable for controlling the location of the peak efficiency of the harvesting rectifier.

Secondly, the harvester path contains a voltage doubler structure $C_1$, $D_1$, $D_2$, $C_2$, a voltage regulator $REG$, load capacitance $C_L$, load resistance $R_L$, and regulated supply output $V_{DD}$. Here, the voltage doubler should convert the RF input power into a DC voltage $V_{EH}$ that is higher than the necessary regulated output voltage $V_{DD}$; additionally, $V_{EH}$ should be given enough room for the modulation of ASK in such a way that the minimum peak voltage is higher than the regulated output voltage. $C_1$, here, should be large enough to allow the input reactance to be dominated by $D_1$ and $D_2$; hence, this capacitor does not block RF power. N×$C_2$ combines N capacitors in a shunt to make a large capacitor (item ①). The main reason for this shunt combination is to reduce the inductive parasitic effects to improve the DC output smoothness; Section 3 will provide more details. The regulator provides a stabilized DC voltage that is not impacted by the ASK-PWM and switching noises from the system. It also powers up $R_L$ and supplies a stable voltage $V_{DD}$ to power up the system’s comparators and inverters. $C_L$ should be very large to filter any noises at the regulator’s output and help with the regulator’s frequency stability.

The communication path is composed of an ASK-PWM demodulator and decoder. It contains a voltage doubler $C_3$, $D_3$, $D_4$, $R_M$, $C_4$, a voltage divider $R_1$, $R_2$, an ASK filter comprising $R_{DIV}$, $R_{CM}$, $C_{CM}$, comparators $COM{P}_1$, $COM{P}_2$, a PWM decoder containing an inverter made out of $M_1$, $M_2$, a skewing inverter made out of $M_3$, $M_4$, $R_{SK}$, $C_{SK}$, comparator $COM{P}_3$, a delay buffer comprising $M_5$, $M_6$, $M_7$, $M_8$, and $C_D$. In this communication path, $C_3$ is chosen to be in the nanofarad range to provide Alternating Current (AC) coupling. $R_M$ with the help of $R_1$ and $R_2$ is used to drop down the voltage of the voltage doubler to a value suitable for $COM{P}_1$ (within the range of its input common-mode range $ICMR$). Additionally, $R_M$ (item ②) provides isolation between the loading of the communication rectifier and the harvester rectifier by reducing the amount of current passing through it. This ensures the $PCE$ is unimpacted by the changes in the loading of the communication rectifier and, hence, adds additional flexibility in tuning the time constants. This voltage doubler produces the communication voltage $V_{COMM}$, an ASK-PWM modulated signal.

As for the ASK filter, N×$C_4$ is made out of several parallel capacitors to reduce inductive effects, and it results in a time constant ${\tau }_1$, which can be approximated assuming $R_{CM}$ is in the megaohm range and the remaining resistors in the filter in the kiloohm range as:

$${\tau }_1\simeq N{C}_4(R_1+R_2)$$

(1)

where $R_1$ and $R_2$ are used mainly to set up ${\tau }_1$ with $C_4$ and divide the voltage even further for the filter. This combination produces the envelope voltage $V_{ENV}$. The voltage division $R_{DIV}$ and $R_{CM}$ with $C_{CM}$ are used to establish the second time constant ${\tau }_2$, which can be approximated to:

$${\tau }_2\simeq N{C}_{CM}(R_{DIV}+R_2)$$

(2)

This combination produces the common-mode voltage $V_{CM}$. ${\tau }_1$ here should be designed to be smaller than ${\tau }_2$ to give $V_{ENV}$ enough voltage swing at the ASK-PWM frequency to be amplified by $COM{P}_1$; ${\tau }_2$ is designed to be about 100 times larger than ${\tau }_1$ to reduce the ASK-PWM modulation. This is achieved by having $C_4$ in the lower sub 10 picofarad range while $C_{CM}$ is two orders of magnitudes larger (since $R_1$, $R_2$, and $R_{DIV}$ are in the 100 s kiloohms range). $R_{CM}$ should be in the megaohm range, and hence, the division between $R_{DIV}$ and $R_{CM}$ should be small. This is used to achieve two goals. The first is that by having such a small voltage division, $V_{CM}$ would be centered between the two peaks of $V_{ENV}$, causing $V_{CM}$ to act as the average of $V_{ENV}$ and, hence, biases $COM{P}_1$ as a common-mode DC voltage. The second goal is to never allow $V_{CM}$ to cross either peaks of $V_{ENV}$ during steady-state operation (i.e., during constant harvesting with no data transmission). As a result, $COM{P}_1$ would amplify the difference between the two peaks of $V_{ENV}$ with the bias of $V_{CM}$, and then it would go into $COM{P}_2$ to maximize the voltage swing into square waves with a reference voltage $VDD/2$. The output of $COM{P}_2$ produces the recovered clock $CLK$ signal demodulated from the ASK modulation.

Moving on to the PWM decoder, after the inversion (through $M_1$ and $M_2$) of the $CLK$ signal containing the PWM modulation, it passes through the skewed inverter ($M_3$, $M_4$, $R_{SK}$ (item ③), $C_{CK}$) followed by $COM{P}_3$ to extract the pre-data $V_{PD}$. The skewing inverter with $COM{P}_3$ is used to distinguish between bits “0” and “1” based on the pulse width of the $CLK$ signal. If the pulse has a narrow-width high signal, it will be decoded as a “0”; if it has a wide-width high signal, it will be decoded as “1”. This is achieved by making the charging time for the skewing inverter long and by making the discharging time as fast as possible, after which $COM{P}_3$ outputs a high signal only when its skewed input crosses its reference voltage $V_{REF}$, outputting bit “1”. Finally, $V_{PD}$ output from $COM{P}_3$ goes through a buffer ($M_5$–$M_8$) that adds a small delay using $C_D$ producing the final data output $V_D$. This delay is necessary to synchronize the negative edge-trigger of $CLK$ with $V_D$ so that the data can be stored and digitally processed for the designed application.

Figure 2 shows illustrative plots of the working principles of the ASK-PWM demodulator by modulating the RF power with the bit pattern “0010”. The plots show the voltage received by the antenna $V_{ANT}$, and they also show $V_{ENV}$,$V_{CM}$, $CLK$, $V_{SK}$, $V_{REF}$, $V_{PD}$, and $V_D$. The plots also highlight the synchronization between $CLK$ and $V_D$ with red dashed lines, as discussed.

3. Design Phases and Proposed Solutions

This section presents the design phases leading to the complete PCB implementation. In these phases, we will show the design approaches, ideas, and proposed solutions that would allow the complete PCB to be implemented in a discrete format.

3.1. Phase 1: Voltage Doubler Design with Parasitic Inductance Impact and Reduction

In the design of a voltage doubler, system analysis led to the definition of the targeted specifications. The harvesting frequency is 900 MHz; the harvested voltage should be at 4 V, while the power delivered should be at 4 mW with a $PCE$ > 50%. Figure 3a shows the schematic of the voltage doubler implemented in the Advanced Design System (ADS). $L_P$ was added to model the parasitic inductance due to the trace and ground vias, which was set to zero initially. The capacitance $C_1$ is a 10 pF capacitor for the reasons highlighted in the previous section, and N× $C_2$ is a 6 × 100 pF capacitor made large to reduce the capacitive ripples at the harvested output voltage node. $R_L$ is made of 4 k$\mathrm{\Omega }$ such that when harvesting 4 V, the power is at 4 mW. The diodes are SMS3922-079LF from Skyworks Solutions Inc., which are sourced from Irvin, CA, USA, and their SPICE model can be found in the datasheet. The matching network is designed by sweeping $L_M$ from 1 nH to 100 nH while parametrically sweeping $C_M$. Figure 3b shows the $S_{11}$ plotted on a Smith chart using Large-Signal S-Parameter (LSSP) simulation. Each circle on the Smith chart represents a $C_M$ plotted for the various $L_M$ values. Values of $L_M$ = 33.68 nH and $C_M$ = 2 pF were selected to match the input of the RF voltage doubler to 50 $\mathrm{\Omega }$ (these values, however, will be modified with PCB layout design). Figure 3c shows the simulated DC harvested voltage and $PCE$, obtaining 4.2 V with a $PCE$ of 71.0 % at a $P_{in}$ = 8 dBm.

A transient simulation was performed to the circuit in Figure 3a with $L_P$ removed, as shown in Figure 4a. It can be noticed that the transient simulation is free from both ripples and RF variations due to the good rejection of the output filter to the RF and any of its harmonics. The output filter’s response is shown in Figure 4b, which resembles a low-pass filtering operation, rejecting the 900 MHz RF and its harmonics. An initial layout using an FR4 substrate with a 0.6 mm thickness was created to produce a reliable simulation, as shown in Figure 4c. A transient co-simulation was performed to visualize the output DC voltage of the harvester, as shown in the figure. As can be seen from the figure, the amount of RF content was large and was not related to how large $C_2$ was. By looking at the frequency response of the output filter, shown in Figure 4d, we can see that the response now is a notch filter, which is caused by the inductive path of the rectification filter through the vias to the ground plane. This was modeled in the ideal schematic of Figure 3a by making $L_P=$ 1.2 nH, which reproduced the results in Figure 4c,d. The output filter response can be written as follows:

$${\displaystyle \frac{V_{\mathrm{out}}\left(s\right)}{V_{\mathrm{in}}\left(s\right)}}={\displaystyle \frac{R_L}{R_0+R_L}}{\displaystyle \frac{s^2+\frac{N}{L_P{C}_2}}{s^2+s\left(\frac{R_0{R}_L}{R_0+R_L}\frac{N}{L_P}\right)+\frac{N}{L_P{C}_2}}}$$

(3)

which confirms the output filter response as a notch filter, which has a resonance frequency $f_0$ at:

$$f_0={\displaystyle \frac{1}{2\pi }}\sqrt{{\displaystyle \frac{N}{L_P{C}_2}}}$$

(4)

From Equation (4), it can be deduced that by increasing N (increasing the number of parallel capacitive branches while keeping the cumulative capacitance the same), it would effectively reduce the inductive parasitic effect and, hence, $f_0$ would increase. As $f_0$ increases, the 3-dB half power frequencies also increase, which improves the rejection at 900 MHz. After this analysis, we split the 600 pF capacitor into 6 × 100 pF capacitors in parallel, as shown in Figure 4e. The transient co-simulation presented in Figure 4e shows that the intensity of RF leakage has reduced drastically after the splitting of capacitances, which reduced the amount of inductance through the vias to the ground plane. Shunting multiple paths with multiple capacitances will reduce the equivalent inductance since $L_P$ will be divided approximately by the number of shunt capacitances. The frequency response is shown in Figure 4f where the increase in $f_0$ is noticeable; hence, the rejection of the RF at 900 MHz is improved from −17 dB to −35 dB. Although an increase of $f_o$ can be achieved by reducing $C_2$ instead of $L_P$, which would also reduce the RF leakage into the output, it would increase the amount of capacitive ripples, which are unwanted. Hence, reducing $L_P$ while keeping $C_2$ large would reduce both capacitive ripples and RF leakage. This technique was applied throughout the work to reduce the amount of voltage ripples and RF leakage at critical nodes.

We conclude our analysis of this phase with the relation between the number of parallel capacitive branches and the amount of RF leakage into the output of the harvesting rectifier. Figure 5 shows the amount of RF leakage vs. the number of parallel branches with annotated differences between consecutive data points. It can be noticed from the plot that, as we increase the number of branches, the RF leakage reduces as expected. It is noted that the incremental benefits reduce with each additional branch, indicating a point of diminishing returns where a further increase in the number of capacitive branches yields progressively smaller improvements. We have chosen six as an appropriate number of elements since they can be compactly placed on the PCB while efficiently reducing RF leakage into the output.

3.2. Phase 2: Interfacing Harvester Path with Communication Path

The second phase is related to the interface between the harvester path and the communication path, which is shown in Figure 6. In this schematic, we modeled the output of the communication’s rectification load with a shunt capacitance $C_2$ and $R_{eq}$, where $R_{eq}$ is approximately the series combination of $R_1$ and $R_2$ in Figure 1. The values of the matching network here do not change from that of phase 1 due to the inclusion of $R_M$, which isolates the power from the two main paths. A critical time constant that allows the ASK modulation to reach the output node of the communication path is ${\tau }_3$, which can be written approximately as:

$${\tau }_3\simeq C_3(R_{eq}+R_M)$$

(5)

where $R_{eq}$ is set at 150 k$\mathrm{\Omega }$ initially to reduce the current amount through the communication path. This time constant results in a high-pass operation; hence, $C_3$ should be designed to be large enough to allow the ASK to pass to the output of the communication path. Figure 7a shows the testbench for the AC simulation to obtain the frequency response at the output, which is plotted in Figure 7b for different values of $C_3$. Since we are designing the bit rate at a low value (15 kbps) to reduce dynamic power consumption, we chose $C_3$ to be at 1000 pF, which would result in a ${\tau }_3$ = 150 μs, which translates to a cutoff frequency for the high pass response at 964 Hz. A plot of the transient response of the circuit in Figure 6 is shown in Figure 8a,b using $C_3$ = 10 pF and 1000 pF, respectively. We can see that we can obtain the modulation correctly according to the calculations and frequency response.

Since a voltage doubler is used in the communication’s path and $R_{eq}$ is large, the output voltage may be too high for the $ICMR$ range of $COM{P}_1$. For that reason, a lossy resistor $R_M$ was added in the series path of $D_3$ in the communication’s path to reduce the output voltage. Additionally, a split of $R_{eq}$ into $R_1$ and $R_2$ was performed to drop the voltage further. $R_M$ also serves another purpose: it reduces the impact of changing $R_{eq}$ in the communication’s path on the $PCE$ of the harvester path. Figure 9a,b show that without having $R_M$, changing $R_{eq}$ leads to voltage reduction at the output of the communication’s path but at the cost of a drastic decrease in $PCE$ in the harvesting path. However, when placing $R_M$, the amount of current flowing through $D_3$ and $D_4$ is reduced drastically, which allows the voltage to be dropped while keeping the $PCE$ high in the harvesting path, regardless of variations in $R_{eq}$ as shown in Figure 9c,d. This adds additional flexibility since now $R_{eq}$ can be used to adjust ${\tau }_1$, ${\tau }_2$, and ${\tau }_3$ with minimal impact on the $PCE$ of the harvester. In a sense, the inclusion of $R_M$ provided good isolation between the harvester and communication paths. Furthermore, the transition in $V_{COMM}$ is more linear in Figure 9c compared to Figure 9a, allowing for a more flexible voltage level choice for $V_{COMM}$. Despite the attenuation that may occur in the communication path’s rectifier due to the addition of $R_M$, the cascaded comparators and the sustainable amount of power being harvested would still guarantee successful demodulation of the ASK signal.

As for $R_M$’s value selection, two objectives must be met. The first is achieving good isolation between the harvester and communication paths, such that when changing $R_{eq}$, the $PCE$ of the harvester path remains constant. The second is to reduce $V_{COMM}$ to an appropriate voltage (center of $ICMR$ of $COM{P}_1$). Both objectives are achieved when increasing $R_M$, which results in better isolation and reduces the impact of $R_{eq}$ on the $PCE$ of the harvester path due to the current reduction in the communication paths discussed above. However, when $R_M$ increases, the attenuation and drop in $V_{COMM}$ increases; additionally, decreasing $R_{eq},$ further adds to the attenuation and voltage drop, as was shown in Figure 9c. An appropriate value of $R_M$ can be selected by first choosing both an $R_{eq}$ that tunes ${\tau }_1$ with $C_4$, and an $R_2$ that tunes ${\tau }_2$ with $C_{CM}$ ($R_1$ is simply obtained by calculating $R_{eq}-R_2$); then, $R_M$ is increased gradually in the simulations until the $PCE$ of harvester’s path is maximized and $V_{ENV}$ is at around the middle of $ICMR$ of $COM{P}_1$.

As for the $PCE$ simulations and measurements, a co-simulation was performed of the circuit in Figure 6. For harvesting a DC power of 4 mW, a $PCE$ of 56.55% was obtained as opposed to the ideal schematic’s $PCE$ of 62.5%. For a 2 mW harvested power, the $PCE$ was co-simulated at 51%. The latter $PCE$ was used as a comparative reference when the 2 V regulator was applied to a 2 k$\mathrm{\Omega }$ load, which provided a power delivery of 2 mW. A prototype was built for this phase, measuring a $PCE$ of 42.12% for an output power of 2 mW.

3.3. Phase 3: ASK Filter and Demodulator

As for the design of the ASK filter and demodulator, the design is mainly concerned with the following: the appropriate envelope voltage swing needs to be close to the center of the $ICMR$ of the comparator, the extracted common mode voltage should be close to the center of the envelope and as constant as possible, and the comparators should produce square waves for clock recovery. For this part, we set $R_M$ = 15 k$\mathrm{\Omega }$ (tuned to 100 k$\mathrm{\Omega }$ after layout), with $R_1$ and $R_2$ both being 75 k$\mathrm{\Omega }$ and $C_4$ = 1 pF. This led to $V_{COMM}$ centered at 2.3 V with AM modulation at 15 KHz, as shown in Figure 10a. This voltage was dropped by half to be close to the center of a full-swing $ICMR$ of a 2V-operated $COM{P}_1$, which is shown as $V_{ENV}$ in Figure 10b. ${\tau }_1$ from Equation (1) was calculated as 900 ns, which translates to a low-pass cutoff frequency of 176.8 KHz, which passes the 15 kHz modulation frequency while attenuating the 900 MHz RF frequency. As for ${\tau }_2$ from Equation (2), with $R_{DIV}$ = 150 k$\mathrm{\Omega }$, $R_{CM}$ = 8 M$\mathrm{\Omega }$, and $C_{CM}$ = 100 pF, it would be equal to 135 μs, which gives a low-pass cutoff frequency of 1.18 kHz, which removes the ASK modulation from $V_{CM}$ but keeps the DC average of $V_{ENV}$, as shown in the blue wave in Figure 10b. The wide range of values selected between ${\tau }_1$, ${\tau }_2$, and ${\tau }_3$ allows for successful demodulation of the ASK for different modulation frequencies ranging from 4 KHz up to 150 KHz. As a result of this wide range, any small variance that may be caused by the selected component would still allow for correct clock recovery. The ASK filter is also dynamic in the sense that if the power changes in a way that still keeps the envelope voltage inside the $ICMR$ of $COM{P}_1$, the common mode voltage would track the average of the envelope, maintaining the correct operation of $CLK$ generation. Additionally, due to $V_{CM}$ being extracted from $V_{ENV}$, they would be in sync; hence, the $CLK$ signal is synced to the frequency of $V_{ENV}$ and $V_{CM}$, regardless of the phase difference between the two latter signals. The $CLK$ signal coming from $COM{P}_2$ is shown in Figure 10c. Note that $V_{CM}$ is not centered exactly in the middle of $V_{ENV}$ due to the voltage division between $R_{DIV}$ and $R_{CM}$, which brings $V_{CM}$ down by 2%, which reduces switching errors during idle state (no data transmission), as shown in Figure 10d. It takes two “0” bits to bring the system from an idle state to the data transmission state. As for the response time of the demodulator, it is limited by the start-up conditions of the demodulator, which is about 0.2–0.3 ms for this specific design choice, which is comparable to that of the regulator’s output time constant.

3.4. Phase 4: PWM Decoder

As discussed in Section 2, the PWM decoder requires a skewing operation for data decoding. The skewing operation is traditionally implemented by making the transistor length $M_3$ large enough to result in the skewing operation by increasing the RC charging time constant while making the aspect ratio ${(W/L)}_4$ as high as possible to allow for a fast discharge time. The former is easy to implement on an IC since there is flexibility in increasing the length of the transistor; however, in discrete PCB implementation, this flexibility is not an option. For this reason, we implemented a solution shown in the inverter $M_3$ and $M_4$ of Figure 1. By adding the skewing resistor $R_{SK}$ between the drain of $M_3$ and the output of the inverter, we can increase the charging time constant by increasing the resistance of the charging path without impacting the discharge path. $C_{SK}$ was also added to the output of the skewing inverter to support this time-constant increase. We denote this time constant as ${\tau }_4$, which can be written as:

$${\tau }_4\simeq C_{SK}\left(R_{SK}\right)$$

(6)

$C_{SK}$ = 100 pF was chosen while $R_{SK}$ = 250 k$\mathrm{\Omega }$. This leads to a time constant of 25 μs. For a 33 μs bit “0” pulse at a supply of 2V, it translates to 1.466 V of peak charging voltage, while a wide pulse of 99 μs indicating bit “1” has a peak charged voltage of 1.96 V. These values are smaller by about 0.4 V in simulations due to the zero undershoot of the gate-to-drain capacitors. Hence, we chose a reference of 1.5 V to distinguish between bits “0” and “1”. Figure 11a shows a simulation plot of the $CLK$ signal sending a repetitive pattern of “0010” to the skewing inverter. Figure 11b shows the skewing operation of the proposed PWM decoder, while Figure 11c presents the data recovery simulation based on the $CLK$ signal’s width.

4. Complete PCB Measurement and Validation

To validate the implementation of such a system in discrete format with the proposed solutions and improvements, we implemented the system entirely on a two-layer FR4 substrate of size 5 cm × 4 cm × 0.6 cm. An FR4 substrate was chosen to minimize the cost and production time without compromising significant performance, which lines up with the objectives of this work. The first layer contains all the components and interconnects, while the second layer is the ground plane. The PCB is shown in Figure 12a with the annotated circuit blocks. $L_M$ is an RF inductor from Murata LQW15AN5N2B80D sourced from Kyoto, Japan. The inductor has a value of 5.2 nH and a Q factor of 70 at 900 MHz. This inductor’s Self-Resonance Frequency $SRF$ is 8 GHz, which is about 9 times higher than the harvesting frequency. The diode is SMS3922-079LF from Skyworks in Irvine, CA, USA: a Schottky diode with a low turn-on voltage, series resistance, and junction capacitance. The breakdown voltage is 8 V, which is suitable for the maximum voltage level in our design. The regulator used is a TLV70220PDBVR manufactured by Texas Instruments in Dallas, TX, USA. This part regulates the voltage at 2 V, draws a bias current of 35 μA only, which makes it suitable for harvesting applications, and has a Power Supply Rejection Ratio $PSRR$ of 68 dB at 1 kHz. Stabilization for this regulator was achieved by making $C_L$ = 100 nF and 6 ×$C_2$ = 600 pF. As for the comparator, BU5265HFV-TR was chosen from Rohm Semiconductor in Japan, which has full input swing and can operate at a $V_{DD}$ range from 1.8 to 5.5 V, suitable for our 2 V regulator. The supply current of this comparator is at a low value of 22 μA, making it ideal for harvesting. The maximum clock frequency for such a comparator is 14.28 MHz, which is more than enough for the bitrate of our system. It is critical to note that these comparators are CMOS and, hence, do not load the ASK filter, especially with the 8 M$\mathrm{\Omega }$ resistor $R_{CM}$ shunted with the input of the comparator. The inverters are made out of bsh103bk NMOS and bsh205g2 PMOS, which are made by Nexperia in USA. The NMOS has a typical threshold voltage of 1 V, while the PMOS has a typical threshold voltage of −0.7 V. Both are suitable for a 2 V supply. The maximum switching frequencies for the NMOS and PMOS are 166.67 MHz and 33.33 MHz, respectively, higher than the designed data rate. The dynamic power consumption of these inverters is at 3 μW at a switching frequency of 15 KHz, 100 pF loading and 2 V supply power, which are reasonable for harvesting. The total power consumption of the system was 355 μW. $R_{SK}$ here is made out of a potentiometer to tune ${\tau }_4$ to control the peak of the skewing output voltage of different bits. As a result, by adjusting the potentiometer, successful bit decoding can be ensured when re-configuring the bit rate for the system.

The measurement setup of radiative field harvesting is shown in Figure 12b. A signal generator SME 06 from Rhode & Schwarz was used to produce an ASK-PWM modulated wave. The output power of the signal generator was set at 16 dBm (calibrated to output 12 dBm) at a frequency of 924 MHz. Although the SME 06 is capable of digital modulation, it does not perform ASK modulation directly. To solve this problem, we controlled the digitally controlled attenuator using a bit pattern at a switching rate of 30 KHz to achieve ASK-PWM modulation. We assigned a 99 μs wide-high pulse followed by a 33 μs of narrow-low pulse for bit “1”, and assigned a 33 μs narrow-high pulse followed by a 33 μs of narrow-low pulse for bit “0”. The signal generator was connected to an 8 dBi HG908PCR Right-Half Circular Polarized (RHCP) commercial antenna. Another antenna was connected to the PCB. Both antennas were characterized using a Vector Network Analyzer (VNA), presenting close to 50 ohms impedances near the 924 MHz frequency. Hence, we operated at that frequency. The separation distance between the antennas was kept at 8 cm. However, the system operated correctly from 6 cm up to 12 cm. The PCB contained several test points connected to the hlRTB2004 Rhode & Schwarz oscilloscope to obtain waveform measurements. The regulator powered up all the inverters and comparators in the PCB; hence, no power supply was needed. All the required references for the comparators were set by voltage division with respect to the regulator voltage. The regulator’s enable pin was connected to $V_{EH}$, which needs to be maintained above 2 V to keep the regulator in normal operating condition.

Figure 13 shows the most critical measurements of the PCB in Figure 12a. Figure 13a shows the harvested voltage $V_{EH}$ and regulated voltage $V_{REG}$. A bit pattern of “100” was transmitted repeatedly, as shown in the red wave in the figure. The voltage swung from 5.2 V to 2.9 V, centered at 4.2 V. The voltage was never below 2 V, keeping the regulator at the correct normal operating condition. The blue wave shows the regulator output voltage was constant at 2 V regardless of variations in the harvested voltage due to modulation. This 2 V was applied to an $R_L$ of 2 k$\mathrm{\Omega }$, hence delivering a power of 2 mW at a total receiver efficiency of 12.5%. Figure 13b shows $V_{COMM}$ being dropped by $R_M$ down to 2.31 V, swinging up to a maximum of 3 V and a minimum of 1.32 V. $R_1$ and $R_2$ dropped this voltage by half, as seen by the blue wave in Figure 13c, producing $V_{ENV}$. We can note that the $V_{ENV}$ range was between 1.5 V and 0.73 V, within the $ICMR$ of $COM{P}_1$. $V_{CM}$ is also shown as the blue line in Figure 13c. Figure 13d presents the output of the proposed skewing inverter (red) and the reference voltage (blue) used to distinguish between a wide- and a narrow-high pulse. Figure 13e shows the data output $V_D$ (red) correctly presenting bit “1” for a wide pulse and bit “0” for a narrow pulse. Also, shown in the same plot, the $CLK$ was produced from $V_{ENV}$, $V_{CM}$, $COM{P}_1$, and $COM{P}_2$. The system performed correct data and clock recovery even with different data bits transmitted due to the asynchronous extraction of both voltages. As for the separation distance validation, a plot showing the relationship between both the minimum peak $V_{EH}$ and power delivered by the regulator vs. the separation distance between the antennas is shown in Figure 13f. We can note three critical regions on the plot: The first is at 8 cm where efficient polarization was achieved and, hence, the highest minimum peak $V_{EH}$ was achieved. The second is after 12 cm where minimum peak $V_{EH}$ dropped below 2 V, which caused the regulator voltage to drop below 2 V. The last region is after the 18 cm mark, where the internal reference inside the regulator collapsed completely and the power plummeted. As a result, the system operated correctly and provided a constant 2 mW power at a separation distance between 6 cm and 12 cm. Finally, The synchronization between $V_D$ and $CLK$ is shown in Figure 14. For bit “1”, the $CLK$ signal dropped before $V_D$; hence, a bit “1” would be stored in a shift register with a negative edge trigger. When the $CLK$ triggered negatively and there was no high signal, it would record a bit “0”.

A comparison between this work and the previous literature is shown in

Table 1. Comparison with the state of the art.

References	[11]	[12]	[13]	[14]	[15]	[16]	[18]	[19]	This Work
Harvesting Frequency	1.32 GHz	13.56 MHz	13.56 MHz	1.86 GHz	N/A	N/A	900 MHz	40.68 MHz	924 MHz
Bitrate	20 Mbps	75 bps	88.3 kbps	25 Mbps	N/A	2 Mbps	10 Mbps	10 kbps	15 kbps
$PCE$	N/A	N/A	N/A	55%	N/A	N/A	N/A	55%	42.12% (12.5%) *
Power Consumption	11 μW	800 μW	4.5 μW	7 μW	50 mW	129 μW	N/A	27 μW	355 μW
Separation Distance	3.5 cm	N/A	2 mm	5 cm	N/A	N/A	1 cm	80 mm	6–12 cm
Harvesting Technology	Radiative Field	N/A	Inductive WPT	Radiative Field	Magnetic Induction	Inductive WPT	Inductive Coupling	Inductive Coupling	Radiative Field
Manu-facturing Tech-nology	65 nm	Hybrid/CMOS	180 nm SoC	65 nm	180 nm BCD	180 nm	65 nm	180 nm	FR4 PCB

* Receiver efficiency with regulator included.

. We can note that this work is the only work that implemented an ASK-PWM harvesting system on an FR4 substrate using discrete components only. Additionally, the separation distance is the largest at a 12 cm distance.

5. Conclusions

This paper presented a radiative-field ASK-PWM decoded energy harvester implemented using discrete components. The paper presented the design approach, proposed solutions, and improvements to the PCB design. One solution targeted the inductive voltage parasitic effect existing at the harvested voltage, which was solved using parallel connections of rectification capacitors to reduce inductive effects. A lossy resistor to the communication rectifier was added to isolate the current between the harvester path and the communication path to minimize the impact on $PCE$; this also allows for additional flexibility in tuning the time constants without impacting the $PCE$. A skewing inverter was implemented using a skewing resistor to achieve the skewing operation instead of the typical design, which is challenging to accomplish on a PCB design. The design was implemented and validated on an FR4 substrate using radiative field measurements at 924 MHz at a bit rate of 15 kbps, consuming a power of 355 μW. It also presented correct harvesting operation and data and $CLK$ recovery from 6 to 12 cm of antenna separation. The work presented is targeted to allow the option of designing an ASK-PWM decoded harvester on an FR4 substrate instead of IC realization and to enable the implementation to target several applications other than biomedical applications at a low cost and reduced manufacturing time.