Kong, X.; Zhu, Z.; Feng, C.; Zhu, Y.; Zheng, X.
An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate Array Systems. Electronics 2025, 14, 466.
https://doi.org/10.3390/electronics14030466
AMA Style
Kong X, Zhu Z, Feng C, Zhu Y, Zheng X.
An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate Array Systems. Electronics. 2025; 14(3):466.
https://doi.org/10.3390/electronics14030466
Chicago/Turabian Style
Kong, Xiangcong, Zixuan Zhu, Chujun Feng, Yongxin Zhu, and Xiaoying Zheng.
2025. "An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate Array Systems" Electronics 14, no. 3: 466.
https://doi.org/10.3390/electronics14030466
APA Style
Kong, X., Zhu, Z., Feng, C., Zhu, Y., & Zheng, X.
(2025). An On-Chip Architectural Framework Design for Achieving High-Throughput Multi-Channel High-Bandwidth Memory Access in Field-Programmable Gate Array Systems. Electronics, 14(3), 466.
https://doi.org/10.3390/electronics14030466