A Unified Design Methodology for Front-End RF/mmWave Receivers

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

RF design typically relies on optimization and routines, so I do not see anything particularly special or novel in what the authors propose. It appears to be a well-executed design exercise; however, there is no implementation of the circuits. In this regard, it should be clarified whether the comparison tables referencing other works refer to measurement-based or simulation-based results (measurement results should, in fact, be compared with other measurements).

The introduction is repetitive and generic. The authors should provide a more detailed description of the state-of-the-art and related references while better outlining their novel contributions. What is meant by a "unified" design methodology? What are the specific target applications and their quantitative constraints? Such a comparison should be methodological, especially since the authors claim to propose new design approaches.

Author Response

The authors would like to sincerely thank the reviewers for their comments and suggestions. In the replies to the comments below, the authors address the concerns raised by the reviewers. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This manuscript reports a unified design methodology for front-end receiver. The current version contains some major concerns as below:

1. in Section 2, there are too many fundamental equiations on receiver, low noise amplifier and VCO. It is suggested that the authors try to squeeze the theoretical analysis, while try to add more comprehensive discussion on the design flow-chart of Fig. 13 and 15.

2. In this manuscript, only the layouts of LNA and VCO are given, with their similation results. However, as is known, for integrated circuits design, the fabrication and measurement are much more important. Therefore, in this work, it is much better to add these sections.

Author Response

The authors would like to sincerely thank the reviewers for their comments and suggestions. In the replies to the comments below, the authors address the concerns raised by the reviewers. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

In this paper, the authors present a unified design methodology for front-end RF/mmWave receivers. This methodology aims to significantly accelerate the design procedure of the front-end RF blocks in complex RX/TX chain implementations, focusing on the task of synthesizing Low-Noise Amplifiers (LNAs) and Voltage-Controlled Oscillators (VCOs) with industry-standard performance. The reviewer's concerns and comments are listed below:

1.        Figure 2 presents the NFMIN cost function in relation to input transistor sizing and bias voltage. Could the authors elaborate on the methodology used to derive this cost function and discuss its applicability across various design scenarios and technologies?

2.      It is necessary to explain how the S-parameters depicted in Figure 4 are derived from the parameters of inductors LS, Lg, Ld, and the gate-source capacitance Cgs as shown in Figure 3.

3.      What platform or tools were utilized to synthesize the low-noise amplifiers and voltage-controlled oscillators presented in the study?

4.      Could the authors provide details on the time required to synthesize the LNA and VCO as mentioned in the paper? Additionally, how many iterations were necessary for the synthesis process of these components?

5.      Is the current algorithm limited to synthesizing only the common source cascoded LNA and the cross-coupled LC VCO, or is it capable of synthesizing other types of RF components?

6.      Tables 5 and 8 should include comparisons of LNAs or VCOs with the same technology process at similar frequencies. Furthermore, the labeled a in these tables indicates measured data. The authors should provide chip photographs to validate these measurements or clarify if these are simulation results, including details on the simulation setup.

7.      In Table 7, the output voltage (Vout) in the SS condition is 0.3V, which is less than the design target of Vout > 0.5V specified in Figure 15. The authors should explain this discrepancy.

8.        In Table 7, the output voltage (Vout) in the SS condition is 0.3V, which is less than the design target of Vout > 0.5V specified in Figure 15. The authors should explain this discrepancy.

9.        Figure 13 specifies requirements for S11 and S21 but not for S22. Additionally, there is a significant difference between the pre-layout and post-layout results for S22 as shown in Figure 18. The authors should justify the absence of S22 requirements and account for the observed variations, providing insights into the design decisions and their impact on performance.

Author Response

The authors would like to sincerely thank the reviewers for their comments and suggestions. In the replies to the comments below, the authors address the concerns raised by the reviewers. Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Thanks for replying to the comments.

Reviewer 2 Report

Comments and Suggestions for Authors

no more comments