Fully DC Aggregation Topology with Power Self-Balancing Capacitors for Offshore Wind Power Transmission: Simulation Study

Abstract

This paper focuses on the Input-Independent Output-Series (IIOS) DC converters within fully DC aggregation systems, which enable independent submodule control and high voltage gain. DC aggregation systems experience output voltage imbalance among submodules due to offshore wind power fluctuations. The proposed isolated DC/DC converter topology incorporates power-balancing capacitors, leveraging intrinsic characteristics to achieve self-power balancing within the system. In addition, this paper proposes an innovative PFMT-PSMN hybrid control strategy that is well-suited for the proposed topology. Firstly, this study performs a time-domain analysis of the intrinsically power-balanced DC series-connected aggregation topology and elucidates the corresponding power-balancing principle. Secondly, based on soft-switching boundary conditions, a hybrid control strategy, PFMT-PSMN, adjusts phase-shift duty cycles to maintain soft-switching conditions while minimizing the system operating frequency. Finally, MATLAB/Simulink simulations validate the power-balancing capability of the intrinsically balanced DC series-connected aggregation system and the effectiveness of the proposed PFMT-PSMN control strategy.

1. Introduction

The rapid growth of offshore wind power continues to drive a steady increase in global installed capacity. The demand for long-distance, high-capacity transmission in offshore wind farms underscores the suitability of DC-based collection and transmission systems [1,2,3,4,5]. In fully DC aggregation systems, modular architectures are commonly constructed by interconnecting individual converter submodules. Typical configurations include Input-Parallel Output-Series (IPOS), Input-Series Output-Series (ISOS), and Input-Parallel Output-Parallel (IPOP) [6,7,8,9,10,11,12]. The Input-Independent Output-Series (IIOS) architecture [13,14,15,16,17] supports independent multi-port control and high-gain series output while maintaining single-stage power conversion, making it well suited for large-scale wind energy aggregation. The IIOS converter serves as the foundational architecture for fully DC aggregation systems. Addressing the inherent challenges within IIOS converters is essential for enhancing the overall performance of DC transmission systems. The yellow-highlighted section in Figure 1 presents the Input-Independent Output-Series DC aggregation topology for offshore wind power. This configuration offers a streamlined solution for achieving high voltage gain, improved cost-effectiveness, enhanced efficiency, and reliable multi-input DC power conversion.

In IIOS converters, submodules are connected in series at the output. Uniform output current, coupled with input power mismatch, leads to voltage imbalance among submodules [18,19,20,21,22]. The series-connected DC aggregation topology mainly has the following issues: (1) Sensitivity to power imbalance: When the voltages or power outputs of individual submodules or sources are inconsistent, the entire series system is prone to power imbalance, which may cause some modules to overload or reduce efficiency; (2) Voltage fluctuations and overvoltage issues: Due to the non-uniform voltages of the modules, the output may experience significant voltage fluctuations or transient overvoltage, affecting equipment reliability; (3) Low fault tolerance: A failure in a single module can impact the current and voltage distribution across the entire series chain, reducing overall system reliability.

Severe power discrepancies may cause overvoltage breakdown in components. Ensuring safe and stable operation while minimizing losses and cost remains a technical challenge. Existing output voltage balancing methods generally fall into three categories:

Category 1: Dynamic power clamping of submodules using control algorithms [23]. This method defines clamping thresholds based on real-time power measurements across submodules to maintain balanced power levels and reduce output voltage deviation. It requires no additional circuitry and offers low cost but introduces a trade-off between efficiency and peak power capability.

Category 2: Integration of secondary voltage-regulation topologies. Ref. [24] introduces impedance-source networks at the front end of each IIOS submodule to enhance voltage regulation flexibility. Ref. [25] combines half-bridge structures with impedance-source networks to further extend the voltage adjustment range. Although these methods mitigate power mismatch, they involve two-stage power conversion, resulting in additional system losses.

Category 3: Power-balancing units inserted between adjacent IIOS submodules. Refs. [26,27,28] employ bidirectional Buck-Boost converters to enable power transfer between neighboring submodules, thereby equalizing mismatched wind power. However, this approach requires numerous power switches and operates under hard-switching conditions, limiting efficiency improvements. In [29], a modular IIOS step-up converter integrates LC series-resonant self-balancing units. These units utilize AC components in resonant networks to achieve power balancing, yet the LC branch design depends on fixed operating frequency, causing power balancing to fail under frequency variations.

To reduce cost and enable power self-balancing, the high-voltage side incorporates a voltage-doubling rectifier network composed of diodes and capacitors. The topology of the proposed IIOS converter with a Self-Power-Balancing capacitor adopted in this paper is illustrated in Figure 2. The power-balancing capacitor establishes distinct current paths during the conduction of the upper and lower bridge arms. This configuration achieves power equilibrium among submodules. In power electronic converters, Pulse-Frequency Modulation (PFM) is well suited for wide-range power regulation, as it effectively reduces switching losses, improves efficiency, and suppresses electromagnetic interference (EMI). However, in the proposed topology, achieving power self-balancing among submodules requires a unified switching frequency across the total system. Phase-Shift Modulation (PSM) allows output voltage regulation through adjustment of phase-shift duty cycles without altering the system frequency. However, relying solely on PSM may compromise soft-switching conditions for the IGBTs. To address this issue, an innovative PFMT-PSMN hybrid control strategy is proposed. In this scheme, the total system switching frequency is regulated using PFM, while the phase-shift duty cycles of the n submodules are determined based on the soft-switching boundary conditions of the IGBTs and controlled via PSM. The PFMT-PSMN strategy enables simultaneous adjustment of the global switching frequency and the individual phase-shift duty cycles, ensuring soft-switching operation while minimizing the system switching frequency. Furthermore, the proposed method achieves effective power balancing within the converter. The effectiveness of the proposed topology and hybrid control strategy is verified through simulations conducted in the MATLAB/Simulink environment.

2. Proposed Topology and Operation

2.1. Topology Description

This paper analyzes a configuration using a full-bridge two-level topology on the low-voltage (LV) side and a half-bridge topology on the high-voltage (HV) side, as shown in Figure 2.

The system consists of m series-connected submodules. The nth submodule is selected as a representative to illustrate the operating principles. C_Ln refers to the LV capacitor, S_n1:S_n4 are LV side IGBTs (D_n1:D_n4 are anti-parallel diodes), and DT_n1:DT_n2 are HV side diodes. L_rn is the transformer leakage inductance, C_rn is the resonant capacitor, the transformer ratio is 1:k, and C_Hn1 and C_Hn2 are the HV dividing capacitors. V_Ln is the input voltage on the low-voltage side, V_Hn is the input voltage on the high-voltage side, v_Crn is the resonant capacitor voltage, i_Lrn is the resonant inductor current, v_ABn is the resonant tank input voltage, and v_CDn is the resonant tank output voltage. C_bn is the power-balancing capacitor, v_Cbn is the power-balancing capacitor voltage, and i_Cbn is power-balancing capacitor current. V_H is the total output voltage of the entire system, M_Fn is the voltage gain of the nth submodule. Output voltage balancing and energy transfer in series-connected DC/DC converter topologies are achieved through power-balancing capacitors.

Simultaneously, the proposed topology retains the capability for fault isolation. In the event of a failure in the nth submodule, the fault can be mitigated by turning off all switches on the submodule’s low-voltage side and disconnecting the balancing capacitor associated with the faulty submodule. Moreover, the topology can alleviate power deficiency resulting from the failure of an individual wind turbine through the incorporation of additional redundancy.

2.2. Operation Principle

Prior to theoretical analysis, define the switching frequency as f_s, the switching period as T_s, and the resonant frequency as f_rn, the resonant angular frequency as ω_rn, the characteristic impedance as Z_rn, and the phase-shift duty cycle as D_n.

$$\left\{\begin{array}{l}{Z}_{\mathrm{rn}}=\sqrt{L_{\mathrm{rn}}/C_{\mathrm{rn}}}\\ f_{\mathrm{rn}}={\displaystyle \frac{1}{2\pi \sqrt{L_{\mathrm{rn}}{C}_{\mathrm{rn}}}}}\\ {\omega }_{\mathrm{rn}}=2\pi f_{\mathrm{rn}}\end{array}\right.,$$

(1)

Figure 3 shows the trigger pulses of the proposed converter submodule, along with key waveforms of the power-balancing capacitor during steady-state operation. The converter operates in six distinct modes within each switching cycle. Here, V_Hn denotes the output voltage of the nth submodule. For analysis, it is assumed that the output voltage of the nth submodule exceeds that of the mth submodule; specifically, V_Hn > V_HN > V_Hm, while the remaining submodules operate at the rated voltage V_HN. The equivalent circuits corresponding to each operating mode are illustrated in Figure 4. Figure 3 illustrates the waveforms under relatively ideal conditions. However, due to the influence of magnetic components [30,31], the same power converter may exhibit different waveforms at varying voltage and power levels. For instance, V_ABn is typically accompanied by oscillations, which in turn affect other waveforms. In addition, i_Lrn and u_crn show ripples of varying magnitudes depending on the voltage level and operating frequency. This phenomenon should be carefully considered in practical applications, as it may influence the stability and efficiency of the system.

The operating principles and waveform characteristics of the mth submodule are analogous to those of the nth submodule. The following analysis focuses on:

• Operation principles and waveforms of the nth submodule within the proposed DC/DC topology.
• Energy transfer between the nth and mth submodules via the power-balancing capacitor C_bn.

Mode 1 (t₀–t₁): As shown in Figure 4a. IGBT S_n4 receives trigger signals. Switch S_n3 hard switches off, while switch S_n1 stays active. The negative leakage inductance current i_Lr initiates freewheeling through diodes D_n1 and D_n4 on the low-voltage side. This clamps the voltage across switches S_n1 and S_n4 to zero, enabling zero-voltage switching (ZVS) to turn on. On the high-voltage side, capacitors C_Hn2 charge. Conducting diodes DT_n2 and DT_m2 form a closed loop with power-balancing capacitor C_bn, enabling C_bn to discharge into C_Hm1 and C_Hm2. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_0)\\ v_{\mathrm{cn}}(t-t_0)\end{array}\right]=\left[\begin{array}{cc}\cos {\omega }_{\mathrm{rn}}(t-t_0)& -\sin {\omega }_{\mathrm{rn}}(t-t_0)\\ \sin {\omega }_{\mathrm{rn}}(t-t_0)& \cos {\omega }_{\mathrm{rn}}(t-t_0)\end{array}\right]\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t_0)\\ v_{\mathrm{cn}}(t_0)\end{array}\right]+\left[\begin{array}{l}\sin {\omega }_{\mathrm{rn}}(t-t_0)\\ 1-\cos {\omega }_{\mathrm{rn}}(t-t_0)\end{array}\right](k{V}_{\mathrm{Ln}}+{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_0)\\ v_{\mathrm{cb}}(t-t_0)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_{\mathrm{H}}}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_0)\\ \cos {\omega }_{\mathrm{o}}(t-t_0)\end{array}\right](m-n)V_{\mathrm{Hm}}\end{array},$$

(2)

Mode 2 (t₁–t₂): As shown in Figure 4b. At t₁, the leakage inductance current i_Lr crosses zero from negative to positive enabling ZVS turn-on of switching devices S_n1 and S_n4. Simultaneously, the application of reverse voltage forces DT_n2 and DT_m2 to be turned off. The available turn-off period spans half the switching cycle. High-voltage capacitors C_Hn1 charge. With Diodes DT_n1 and DT_m1 conducting, nth submodule capacitors C_Hn1 and C_Hn1 and power-balancing capacitor C_bn form a closed loop enabling C_Hn1 and C_Hn2 to discharge into C_bn. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_1)\\ v_{\mathrm{cn}}(t-t_1)\end{array}\right]=\left[\begin{array}{l}-\sin {\omega }_{\mathrm{rn}}(t-t_1)\\ \cos {\omega }_{\mathrm{rn}}(t-t_1)\end{array}\right]v_{\mathrm{cn}}(t_1)+\left[\begin{array}{l}\sin {\omega }_{\mathrm{rn}}(t-t_1)\\ 1-\cos {\omega }_{\mathrm{rn}}(t-t_1)\end{array}\right](k{V}_{\mathrm{Ln}}-{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_1)\\ v_{\mathrm{cb}}(t-t_1)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_{\mathrm{H}}}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_1)\\ \cos {\omega }_{\mathrm{o}}(t-t_1)\end{array}\right](m-n)V_{\mathrm{Hn}}\end{array},$$

(3)

Mode 3 (t₂–t₃): As shown in Figure 4c. At time t₂, switch S_n1 turns off under hard-switching conditions, while S_n2 receives its trigger signal. Switch S_n4 remains conducting. The positive leakage inductance current i_Lr directs the low-voltage-side current through S_n4 and diode D_n2. High-voltage capacitors C_Hn1 charge. Diodes T_n1 and T_m1 remain conducting on the high-voltage side. A discharge path persists between high-voltage capacitors C_Hn1/C_Hn2 and power-balancing capacitor C_bn, enabling C_Hn1 and C_Hn2 to discharge into C_bn. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_2)\\ v_{\mathrm{cn}}(t-t_2)\end{array}\right]=\left[\begin{array}{cc}\cos {\omega }_{\mathrm{rn}}(t-t_2)& -\sin {\omega }_{\mathrm{rn}}(t-t_2)\\ \sin {\omega }_{\mathrm{rn}}(t-t_2)& \cos {\omega }_{\mathrm{rn}}(t-t_2)\end{array}\right]\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t_2)\\ v_{\mathrm{cn}}(t_2)\end{array}\right]+\left[\begin{array}{l}\sin {\omega }_{\mathrm{rn}}(t-t_2)\\ 1-\cos {\omega }_{\mathrm{rn}}(t-t_2)\end{array}\right](-{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_2)\\ v_{\mathrm{cb}}(t-t_2)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_{\mathrm{H}}}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_2)\\ \cos {\omega }_{\mathrm{o}}(t-t_2)\end{array}\right](m-n)V_{\mathrm{Hn}}\end{array},$$

(4)

Mode 4 (t₃–t₄): As shown in Figure 4d. At time t₃, IGBT S_n3 received trigger signals. Switch S_n4 hard switches off, while switch S_n2 stays active. The positive leakage inductance current i_Lr initiates freewheeling through diodes D_n2 and D_n3 on the low-voltage side. This clamps the voltage across switches S_n2 and S_n3 to zero, enabling zero-voltage switching (ZVS) to turn on. High-voltage capacitors C_Hn1 charge. A discharge path persists between high-voltage capacitors C_Hn1/C_Hn2 and power-balancing capacitor C_bn, enabling C_Hn1 and C_Hn2 to discharge into C_bn. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_3)\\ v_{\mathrm{cn}}(t-t_3)\end{array}\right]=\left[\begin{array}{cc}\cos {\omega }_{\mathrm{rn}}(t-t_3)& -\sin {\omega }_{\mathrm{rn}}(t-t_3)\\ \sin {\omega }_{\mathrm{rn}}(t-t_3)& \cos {\omega }_{\mathrm{rn}}(t-t_3)\end{array}\right]\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t_3)\\ v_{\mathrm{cn}}(t_3)\end{array}\right]+\left[\begin{array}{l}-\sin {\omega }_{\mathrm{rn}}(t-t_3)\\ -1+\cos {\omega }_{\mathrm{rn}}(t-t_3)\end{array}\right](k{V}_{\mathrm{Ln}}+{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_3)\\ v_{\mathrm{cb}}(t-t_3)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_{\mathrm{H}}}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_3)\\ \cos {\omega }_{\mathrm{o}}(t-t_3)\end{array}\right](m-n)V_{\mathrm{Hn}}\end{array},$$

(5)

Mode 5 (t₄–t₅): As shown in Figure 4e. At time t₄, the leakage inductance current i_Lr crosses zero from positive to negative enabling the ZVS turn-on of switching devices S_n2 and S_n3. Simultaneously, reverse voltage application forces DT_n1 and DT_m1 to turn off. The available turn-off period spans half the switching cycle. High-voltage capacitors C_Hn2 charge. With diodes T_n2 and T_m2 conducting, nth submodule capacitors C_Hm2 and C_Hm2 and power-balancing capacitor C_bn form a closed loop, enabling C_bn to discharge into C_Hm2 and C_Hm2. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_4)\\ v_{\mathrm{cn}}(t-t_4)\end{array}\right]=\left[\begin{array}{l}-\sin {\omega }_{\mathrm{rn}}(t-t_4)\\ \cos {\omega }_{\mathrm{rn}}(t-t_4)\end{array}\right]v_{\mathrm{cn}}(t_4)+\left[\begin{array}{l}-\sin {\omega }_{\mathrm{rn}}(t-t_4)\\ -1+\cos {\omega }_{\mathrm{rn}}(t-t_4)\end{array}\right](k{V}_{\mathrm{Ln}}-{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_4)\\ v_{\mathrm{cb}}(t-t_4)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_{\mathrm{H}}}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_4)\\ \cos {\omega }_{\mathrm{o}}(t-t_4)\end{array}\right](m-n)V_{\mathrm{Hm}}\end{array},$$

(6)

Mode 6 (t₅–t₆): As shown in Figure 4f. At time t₅, switch S_n2 turns off under hard-switching conditions, while S_n1 receives its trigger signal. Switch S_n3 remains conducting. The negative leakage inductance current i_Lr directs the low-voltage-side current through S_n3 and diode D_n1. High-voltage capacitors C_Hn2 charge. Diodes DT_n2 and DT_m2 remain conducting on the high-voltage side. A discharge path persists between high-voltage capacitors C_Hm1/C_Hm2 and power-balancing capacitor C_bn, enabling C_bn to discharge into C_Hn1 and C_Hn2. The time-domain relationships for the inductor and capacitor are defined as:

$$\begin{array}{l}\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t-t_5)\\ v_{\mathrm{cn}}(t-t_5)\end{array}\right]=\left[\begin{array}{cc}\cos {\omega }_{\mathrm{rn}}(t-t_5)& -\sin {\omega }_{\mathrm{rn}}(t-t_5)\\ \sin {\omega }_{\mathrm{rn}}(t-t_5)& \cos {\omega }_{\mathrm{rn}}(t-t_5)\end{array}\right]\left[\begin{array}{l}{Z}_{\mathrm{rn}}{i}_{\mathrm{Ln}}(t_5)\\ v_{\mathrm{cn}}(t_5)\end{array}\right]+\left[\begin{array}{l}-\sin {\omega }_{\mathrm{rn}}(t-t_5)\\ -1+\cos {\omega }_{\mathrm{rn}}(t-t_5)\end{array}\right](-{\displaystyle \frac{V_{\mathrm{Hn}}}{2}})\\ \left[\begin{array}{l}{i}_{\mathrm{cb}}(t-t_5)\\ v_{\mathrm{cb}}(t-t_5)\end{array}\right]=\left[\begin{array}{l}0\\ {\displaystyle \frac{m+1}{2}}-k\end{array}\right]{\displaystyle \frac{V_H}{n}}-\left[\begin{array}{l}{C}_{\mathrm{bn}}\sin {\omega }_{\mathrm{o}}(t-t_5)\\ \cos {\omega }_{\mathrm{o}}(t-t_5)\end{array}\right](m-n)V_{\mathrm{Hm}}\end{array},$$

(7)

2.3. Power Balancing Principle

The proposed topology achieves inherent power balancing by enforcing a unified operating frequency across all submodules. Figure 5 illustrates the power self-balancing mechanism of the proposed IIOS topology with integrated power-balancing capacitors. When the upper arm on the high-voltage side is turned on, the balancing capacitor forms a current loop with the output capacitor of the preceding submodule. When the lower arm is turned on, it connects with the output capacitor of the subsequent submodule. Alternating the conduction of the upper and lower arms enables effective power transfer among cascaded submodules.

2.4. Soft-Switching Implementation

Ref. [32] established the boundary conditions required to maintain IGBT soft-switching operation over the full power range. For series resonant converters, achieving zero-voltage switching (ZVS) for IGBTs is critical to minimizing switching losses. However, ZVS is conditional; it requires the IGBT output capacitance to be fully charged or discharged within the designated dead time. Between the two bridge legs, soft switching is more difficult to achieve in the lagging leg than in the leading leg.

I_dt is defined as the minimum current required to charge or discharge the output capacitance within the dead time. Given the short duration of the dead time, the current can be approximated as a constant current source during this interval. Accordingly, the ZVS boundary condition for the IGBTs and the expression for I_dt are given by Equation (7).

Defining the rated power of Submodule n as P_Nn and the rated voltage as V_Nn and neglecting the reactive components in the system, the rated current is I_Nn.

$${\displaystyle \frac{i_{\mathrm{Lrn}}\left(t_0\right)}{I_{\mathrm{Nn}}}}={\displaystyle \frac{I_{\mathrm{dt}}}{k{I}_{\mathrm{Nn}}}},I_{\mathrm{dt}}=-{\displaystyle \frac{2C_{\mathrm{oss}}{V}_{\mathrm{Ln}}}{t_{\mathrm{d}}}},I_{\mathrm{Nn}}={\displaystyle \frac{P_{\mathrm{Nn}}}{V_{\mathrm{Nn}}}},$$

(8)

C_oss denotes the output capacitance of the IGBTs, and t_d is the dead time.

i_Lrn(t₀) = 0 represents the ideal case where the effect of output capacitance is neglected, while i_Lrn(t₀) = −0.1I_Nn accounts for the capacitive effect. The threshold value of 0.1 is considered the minimum normalized current required to achieve ZVS for the IGBTs. At a fixed positive voltage gain, the phase-shift duty cycle corresponding to the ZVS boundary decreases as the switching frequency increases.

2.5. Performance Comparison with Other IIOS Converters

Taking

Table 1. Performance comparison with other IIOS converters.

	Proposed Converter	PSFB + Buck-Boost Converter [26]	PSFB + Buck-Boost + Phase-Shift LC Solution [28]	DAB + Self-Balancing LC Solution [29]
Semiconductor device	4m IGBTs and 2m Diodes	4m + 2(m − 1) IGBTs and 2m Diodes	4m + 2(m − 1) IGBTs and 2m Diodes	8m IGBTs
Additionally circuits	(m − 1) capacitor circuits	2(m−1) Buck-Boost circuits	2(m − 1) Buck-Boost and LC circuits	(m − 1) LC circuits
Control loop	m	2m − 1	2m − 1	m
Implementation and control complexity	Simple	Complex	Very Complex	Simple
Input ripple	Low	Large	Large	Large
Cost	Very Low	High	Very High	High
Dynamic response	Slightly Slow	Fast	Very Fast	Slow
Switching loss	Low	Large	Large	Low

as an example, the proposed topology is compared with mainstream power-balancing methods in terms of switching loss, control complexity, cost, and dynamic response. On the low-voltage side, the proposed topology employs a full-bridge structure with IGBTs to enable both frequency and phase control. On the high-voltage side, a voltage-doubling rectifier network composed of diodes and output capacitors is adopted to minimize the switching cost. The balancing circuit relies solely on a single balancing capacitor to achieve power balancing, thereby significantly reducing the number of switching devices compared with the schemes in [26,28,29]. In [26,28], additional control circuits are also required.

The proposed PFMT-PSMN control strategy further lowers switching frequency, thereby reducing losses and ripple. Although the self-balancing mechanism yields a slightly slower response than [26,28], simulations confirm its capability to achieve stable power balancing. Compared with the LC resonant self-balancing in [29], direct DC energy transfer in the proposed topology reduces losses and improves response.

In conclusion, the proposed topology demonstrates clear cost advantages, simplifies control through self-balancing, and, with PFMT-PSMN, achieves reduced switching loss and enhanced dynamic performance.

3. PFMT-PSMN Hybrid Control Strategy for Proposed Topology and Simulation

3.1. PFMT-PSMN Hybrid Control Strategy

Building on this approach, this paper presents an improved control strategy tailored to the proposed power-balancing circuit. The total output voltage is regulated using Pulse-Frequency Modulation (PFM), while the optimal phase-shift duty cycle for each of the n submodules is calculated based on the switching frequency determined by the PFM stage. The enhanced method is defined as the PFMT-PSMN hybrid control strategy.

This approach enhances converter efficiency while limiting the variation range of the switching frequency. The proposed topology requires the precise synchronization of the switching frequency across all m submodules. An optimized soft-switching control strategy determines the optimal phase-shift duty cycle for each submodule, enabling system-wide performance improvement.

The analytic expression for D_n (f_s, M_Fn, i_Hn) and f_sn is obtained as:

$$\begin{array}{l}{D}_{\mathrm{n}}\left(f_{\mathrm{s}},M_{\mathrm{Fn}},i_{\mathrm{Hn}}\right)={\displaystyle \frac{1}{2}}-{\displaystyle \frac{B{f}_{\mathrm{s}}}{\pi f_{\mathrm{rn}}}}-\Delta D M_{\mathrm{Fn}}={\displaystyle \frac{V_{\mathrm{Hn}}}{k{V}_{\mathrm{Ln}}}}\\ B={\tan }^{-1}A+{\sin }^{-1}\left[\left(M_{\mathrm{Fn}}-{\displaystyle \frac{1}{\sqrt{1+A^2}}}\right)\sin \left({\displaystyle \frac{\pi f_{\mathrm{rn}}}{2f_{\mathrm{s}}}}\right)+{\displaystyle \frac{A}{\sqrt{1+A^2}}}\cos \left({\displaystyle \frac{\pi f_{\mathrm{rn}}}{2f_{\mathrm{s}}}}\right)\right]\\ A={\displaystyle \frac{I_{dt}}{k\left(-\frac{\pi f_{\mathrm{rn}}}{f_{\mathrm{s}}}-1-\frac{M_{\mathrm{Fn}}}{2}\right)}}\end{array}$$

(9)

t_d is the dead time, and ΔD represents the design margin introduced to ensure ZVS, accounting for approximation errors and neglecting the influence of dead time, and M_F is the voltage gain.

3.2. PFMT-PSMN Hybrid Control for Proposed Topology

Figure 6 illustrates the control block diagram of the PFMT-PSMN hybrid control strategy. The system generates an error signal by subtracting the measured input/output voltage from its reference value, enabling voltage regulation (input or output) while maintaining forward power transfer. An empirical feedforward term f_const is summed with the PI compensatory output to determine the switching frequency f_s, thereby improving dynamic response and suppressing oscillation. The phase-shift duty cycle D_n is calculated via the function D_n (f_s, M_Fn, i_Hn). This architecture achieves coordinated PFMT-PSMN hybrid control with adaptive parameter adjustment.

4. Simulation Results

4.1. Simulation Parameters

Table 2. Simulation parameters.

Parameters	Values	Parameters	Values
Output power Pout	360 kW	Transformer ratio 1:k	1:2.2
Resonant frequency fr	4 kHz	Rated voltage VHN	1.5 kV
Commutation turn-off time tc-off	50 μs	Resonant inductance Lrn	400 µH
Resonant capacitance Crn	4 µF	Dead time td	1 µs
The high-voltage capacitors CHn1/CHn2	1 mF	Power-balancing capacitor Cbn	0.1 mF

summarizes key simulation parameters. The proposed converter operates at a resonant frequency of 4 kHz across all submodules. The power-balancing capacitance is set to 0.1 mF (one-tenth of the high-voltage-side output capacitance), as excessive capacitance prolongs balancing time while insufficient capacitance fails to achieve power balance. The system input power, constrained by the source characteristics, has a rated power P_N and rated voltage V_N; the system operates under PFMT-PSMN hybrid control.

4.2. Simulation Results of PFMT-PSMN Hybrid Control

Figure 7a,b compare two control strategies: conventional PFM control and a hybrid PFMT-PSMN control approach. Since this section focuses on control strategy verification through simulation, two proposed DC/DC topologies are connected in series, and power balancing is achieved via power-balancing capacitors. Under series connection, identical output currents from both converters imply that equal output voltages correspond to balanced power. Regardless of the control method, the system consistently maintains a total output voltage of 3 kV and achieves power balancing, with each converter delivering 180 kW.

As shown in Figure 7b, the switching frequency before power balancing under hybrid PFMT-PSMN control is 5.344 kHz and 5.307 kHz after balancing—both significantly lower than the 6.245 kHz observed with conventional PFM control. This reduction in switching frequency through hybrid PFMT-PSMN control facilitates device selection and simplifies magnetic component design.

In Figure 7b, the phase-shift duty cycle of Topology 1 changes from 0.291 before voltage balancing to 0.302 after, while that of Topology 2 shifts from 0.282 to 0.293. This demonstrates that the hybrid PFMT-PSMN control modifies the phase-shift duty cycles of both topologies. Since the input powers of the two converters differ, their duty cycles naturally vary according to Equation (8). By introducing an additional control variable, phase-shift duty cycle—alongside switching frequency—the hybrid control strategy increases the system’s control flexibility. This decoupling of voltage regulation from frequency alone significantly reduces the required switching frequency and simplifies the realization of soft switching across the system.

Figure 8 presents the steady-state waveforms at 0.6 s from Figure 7b, during which the total output voltage remains at 3 kV. As shown, the resonant currents at time t₁ are −127 A and −156 A for the two topologies, respectively, while the actual value of I_sw/k is −134 A. This indicates that the system operates near the boundary of soft switching, enabling zero-voltage switching (ZVS) turn-on for the IGBTs.

4.3. Simulation Results of the Operating Characteristics of Series-Connected Submodules and the Power-Balancing Capacitor

To verify the operating principle illustrated in Figure 2, four proposed converter topologies were connected in series, and power balancing among different submodules was achieved using three power-balancing capacitors. As shown in Figure 9, at t = 0.1 s, power-balancing capacitor C_b1 is connected, enabling power balancing between Submodules 1 and 2, while the output voltages of Submodules 3 and 4 remain nearly unchanged. At t = 0.15 s, C_b2 is introduced, extending power balancing to Submodules 1–3. Finally, at t = 0.2 s, C_b3 is connected, achieving power balancing across the entire series-connected system.

During the connection of each balancing capacitor, the total output voltage remains constant at 6 kV under hybrid PFMT-PSMN control. The right-hand plot in Figure 9 shows the voltage and current waveforms of capacitor C_b1 at a steady state. At time t₁, the upper bridge of the high-voltage side is conducting, allowing C_H11/C_H12 of Submodule 1 to discharge into C_b1, resulting in a voltage rise across the capacitor. At t₄, the lower bridge conducts, and C_b1 discharges into C_H21/C_H22, causing the capacitor voltage to decrease. The waveforms of the other balancing capacitors follow the same principle.

By alternating conduction of the upper and lower bridge arms, the power-balancing capacitor serves as an energy transfer bridge between C_Hn1/C_Hn2, ensuring uniform output voltages across all submodules. Consequently, the voltage stress on the high-voltage switches of each submodule is equalized. The integration of power-balancing capacitors thus contributes to protecting the high-voltage-side switching devices in each submodule.

5. Conclusions

This paper addresses the output power balancing challenge in offshore wind DC aggregation systems caused by power fluctuations. A novel series-connected DC aggregation topology incorporating power self-balancing capacitors is proposed to enable energy equalization among submodules. Based on soft-switching boundary conditions, a PFMT-PSMN hybrid control strategy is proposed that simultaneously regulates the phase-shift duty cycle and switching frequency. The main contributions of this work are summarized as follows:

• A series-connected DC aggregation topology incorporating power-balancing capacitors is proposed. The working principles of the balancing capacitor and the resonant components are analyzed using time-domain methods.
• Based on soft-switching boundary constraints, conventional PFM and PSM methods are refined and a PFMT-PSMN hybrid control strategy is proposed. This strategy enables simultaneous adjustment of the switching frequency and phase-shift duty cycle, achieving soft-switching operation while reducing the switching frequency. It is well suited for series-connected DC aggregation topologies with power self-balancing capacitors. The PFMT-PSMN control method adopted in this paper requires real-time monitoring of multiple parameters (voltage, current, and gain), which may increase the control cost; however, it can be appropriately simplified for practical applications.
• The effectiveness of the proposed power-balancing topology and PFMT-PSMN control strategy is verified through MATLAB/Simulink simulations. A hardware prototype is currently under design, and future work will involve experimental validation to further corroborate the theoretical analysis and simulation results presented in this paper.

The proposed strategy introduces a higher degree of control freedom, significantly reducing switching losses. The self-balancing topology provides a feasible solution to output voltage imbalance caused by power instability in series-connected aggregation systems. This approach is also applicable to other fully DC aggregation and transmission systems in renewable energy generation.