Research on Low-Spurious and High-Threshold Limiter

Abstract

In this paper, a low-spurious and high-threshold limiter is proposed for C-band applications, where power dividers and phase shifters are used to improve the threshold and reduce the spurious response, respectively. Through the principles of multipath synthesis and phase cancellation, the enhancement of fundamental frequency signals and the suppression of harmonic spurs are achieved. The simulated and measured results demonstrate that the presented design can realize a harmonic suppression ratio (HSR) of more than 38.0 dB in the frequency band of 2.6–3.1 GHz. The threshold of the limiter is improved by 3.0 dB, the maximum insertion loss is less than 1.0 dB, and the return loss is more than 13.0 dB.

1. Introduction

Limiters are critical components that protect modern radio frequency (RF) receivers from damage caused by high-power incident waves. They are typically installed at the front end of the signal receiver to suppress the front-door coupling of high-power signals while ensuring low-loss transmission of small signals [1]. However, in the process of suppressing high-power incident waves, signal distortion will inevitably be introduced due to the nonlinear effect of PIN diodes. The in-band intermodulation signals caused by distortion can severely degrade the sensitivity of the signal receiver [2]. Therefore, the distortion rate, primarily manifested as harmonic generation, is a critical metric for system performance.

Currently, distortion suppression technologies are mainly employed in fault current limiters (FCLs). The following describes several advanced limiter technologies that incorporate distortion suppression.

①

Solid-State Fault Current Limiting and Interrupting Device (FCLID) [3,4]

An FCLID consists of a bidirectional switch, varistor, and snubber circuit. Harmonics originate from repetitive switching during fault current limiting. Anti-distortion methods include (a) adjusting the switching strategy (e.g., increasing I_min) to narrow the current bandwidth, raising switching frequency to shift harmonics to higher frequencies, which are easier to filter and (b) adding a small series inductor to attenuate high dv/dt effects on sensitive loads like SMPS, reducing current spikes and voltage distortion.

②

Resistive Superconducting FCL (RSFCL) [5]

Harmonics in an RSFCL stem from current oscillations in the flux flow state. Anti-distortion is achieved by reducing the volume of superconducting elements: a smaller volume (e.g., 0.01 m³) lowers the total harmonic distortion (THD) from 13% to 3.9%, though this requires balancing the fault current limiting capability.

③

Inductive Superconducting FCL [6]

The 6-pulse and 12-pulse configurations generate harmonics (5th, 7th, 11th, 13th). The anti-distortion methods include (a) using passive LC filters tuned to specific harmonics (5th, 7th for 6-pulse; 11th, 13th for 12-pulse) and (b) adopting a 12-pulse bridge configuration to eliminate the fifth and seventh harmonics inherently, reducing the need for filtering.

④

76–81 GHz Radar Receiver Limiter [7]

This limiter employs third-order intermodulation distortion (IM3) cancellation in the LNA: an auxiliary core generates IM3 components out-of-phase with those from baseband blocks, achieving destructive interference. Additionally, a unique detector monitors the LNA’s first-stage operating point, turning off the stage at high input power (>4 dBm) to prevent transistor damage, with minimal impact on the signal path integrity via isolated sensing circuitry.

⑤

Converter-based FCL [8]

This FCL integrates a series inductor and a voltage source inverter (VSI). In standby mode, the VSI operates as a virtual capacitor to compensate for the voltage drop across the series inductor. To suppress distortion, it employs a harmonic compensation strategy: harmonic voltages are detected by comparing the measured line voltage with a reference signal, and a compensation signal is generated to counteract these harmonics. This dual-function control (voltage drop compensation + harmonic suppression) ensures minimal distortion without active power input, relying on DC-side capacitors for energy support.

From the above-mentioned literature, it is evident that distortion suppression techniques are predominantly deployed in high-power grid transmission systems, whereas their application in radar receiver front-end limiters remains notably scarce. This study aims to address this technological gap by proposing a novel distortion suppression scheme. Specifically, this work integrates multi-path synthesis and phase cancellation technologies to develop a low-spur PIN diode limiter, which enables effective suppression of harmonic frequencies and a significant reduction in the signal distortion. Furthermore, benefiting from multi-channel power synthesis, the threshold of the limiter is improved by at least 3.0 dB. The fabricated limiter achieves a harmonic suppression ratio (HSR) exceeding 38.0 dB within the frequency range of 2.6–3.1 GHz, thus demonstrating substantial potential for applications in radar and communication systems.

2. Limiting Principle of PIN Diodes

The PIN diode is the core component of the limiter, offering advantages such as a short response time, low parasitic parameters, and ease of integration, making it widely used in integrated circuit processes [9]. The PIN diode consists of lightly doped P-type and N-type semiconductors sandwiching an intrinsic (I) layer [10]. Under high-level RF signals, its limiting principle is based on the conductivity modulation effect [11].

During the positive half-cycle of the signal, carriers from the P and N layers are driven into the I layer under the influence of the electric field, causing a significant accumulation of carriers at the boundaries of the I layer, as shown in Figure 1a. During the negative half-cycle, the carriers in the I layer drift back toward the P and N regions. However, due to the much higher carrier concentration at the I layer boundaries compared to the center, some carriers continue to diffuse toward the center. At high frequencies, the RF signal period is much shorter than the average carrier lifetime; so, not all carriers recombine during the negative half-cycle, leaving residual carriers. After several cycles, the carrier concentration in the I layer stabilizes, as shown in Figure 1b. At this point, the PIN diode can be modeled as a current-controlled variable resistor [12], causing impedance mismatch in the circuit and reflecting high-power signals to achieve limiting [13].

It is important to note that the steady-state distribution does not imply static carrier concentrations. The I-layer carrier concentration reaches a dynamic equilibrium, where the carriers diffusing into the I layer balance those recombining, equivalent to a continuous current flow through the PIN diode [10]. Thus, an external DC bias is required for the diode [13]. The simplest PIN diode limiter consists of a shunt PIN diode, with one end connected to the input and the other grounded, alongside a choke coil to provide DC bias [14]. However, the low Q-factor of choke coils makes them impractical for MMIC processes. In practice, two identical diodes are often connected in antiparallel, allowing mutual DC bias and ensuring DC continuity [13]. Since limiters are passive devices, the DC bias for the PIN diode is derived from the input signal itself. For small input signals, the DC bias is insufficient to fully turn on the PIN diode, allowing low-loss signal transmission. For high-power signals, the signal strength is adequate to turn on the diode, activating the limiting function. This is the fundamental principle of PIN diode limiting.

The selection of the PIN diode is critical in limiter design. The width of the intrinsic layer (W) significantly influences the limiter’s sensitivity. A smaller W increases the sensitivity of the I-layer conductivity to RF signal variations [15], enabling faster stabilization of the carrier concentration and reducing the response time, thereby minimizing spike leakage effects. At room temperature, the carrier transit time T_W and transit frequency f_T are expressed as [13] T_W = 0.38 × W², f_T = 2600/W², where the units of W, T_W, and f_T are μm, ns, and MHz, respectively. Among existing PIN diode models, the one proposed in [16] accurately predicts the impedance–frequency behavior. Assuming equal electron and hole concentrations in the base region and Shockley–Read–Hall recombination [16,17], the carrier distribution in this region is governed by the bipolar diffusion equation:

$${\displaystyle \frac{{\partial }^{2}p}{\partial x^2}}={\displaystyle \frac{p}{L_a^2}}+{\displaystyle \frac{1}{D_a}}{\displaystyle \frac{\partial p}{\partial t}}.$$

(1)

The boundary conditions for Equation (1) at the P⁺-I (x = 0) and I-N⁺ (x = W) junctions are [18]

$${\displaystyle \frac{\partial p}{\partial x}}\left(0,t\right)=-{\displaystyle \frac{b}{1+b}}{\displaystyle \frac{i\left(t\right)}{qA{D}_a}}+{\displaystyle \frac{h_p}{D_a}}p{\left(0\right)}^2,$$

(2)

$${\displaystyle \frac{\partial p}{\partial x}}\left(W,t\right)={\displaystyle \frac{1}{1+b}}{\displaystyle \frac{i\left(t\right)}{qA{D}_a}}-{\displaystyle \frac{h_n}{D_a}}p{\left(W\right)}^2,$$

(3)

where h_p and h_n account for the emitter recombination. Applying these boundary conditions and performing a Laplace transform on Equation (3) yields the frequency-domain solution, as shown below [16].

$$\begin{array}{ll}P\left(x,s\right)=& {\displaystyle \frac{L_{a_{e}ff}}{\sinh \left(\frac{W}{L_{a_{e}ff}}\right)}}\\ & \left[\left({\displaystyle \frac{1}{1+b}}{\displaystyle \frac{I\left(s\right)}{qA{D}_a}}-{\displaystyle \frac{h_n}{D_a}}P{\left(W\right)}^2\right)\cosh \left({\displaystyle \frac{x}{L_{a_{e}ff}}}\right)-\left(-{\displaystyle \frac{b}{1+b}}{\displaystyle \frac{I\left(s\right)}{qA{D}_a}}+{\displaystyle \frac{h_p}{D_a}}P{\left(0\right)}^2\right)\cosh \left({\displaystyle \frac{W-x}{L_{a_{e}ff}}}\right)\right]\end{array}$$

(4)

Here, $L_{a_{e}ff}=L_a/\sqrt{1+s\tau }$ is the effective diffusion length in the base region. The junction current can be derived by solving P(x, s) at x = 0 and x = W, applicable to both small- and large-signal excitations. The total junction current I(s) is calculated using Equation (4) and the Boltzmann relation.

3. Circuit Design

The nonlinear effects of PIN diodes introduce a certain degree of distortion in the limiter, particularly when reverse-biased, where the variation in reverse capacitance further exacerbates the signal distortion [19]. The harmonic components generated by signal distortion can interfere with subsequent circuits, making harmonic suppression a critical performance metric for limiters and the primary technical goal of this paper.

In this work, multi-path synthesis and phase cancellation technologies are combined to reduce the harmonic generation. Figure 2 shows the circuit schematic diagram of the limiter. Specifically, the input RF signal is partitioned into multiple branches via power dividers with tailored power-division ratios. Each branch incorporates a dedicated limiter module and a phase shifter. The phase shifters are configured to impart precise phase disparities among the signals traversing different branches. Ultimately, these signals are recombined, exploiting the introduced phase differences to suppress harmonic components through constructive and destructive interference.

As a specific case in point, this design presents a low-spur limiter operating in the C-band based on microstrip structures. The input RF signal is first split into two equal-power signals by a T-junction power divider. Then, one of the two signals is further split into two equal signals, resulting in three RF signals with a power distribution ratio of 2:1:1. Each signal path is subjected to limiting by a pair of anti-parallel PIN diodes. Owing to the symmetry of the circuit, the even-order harmonic components cancel each other out, leaving only the odd-order harmonics to be considered. Additionally, due to the reflective limiting principle inherent to PIN diodes, reflections induced by impedance mismatches at the power divider ports need not be accounted for, thereby eliminating the requirement for isolation resistors.

First, the improvement in the limiting threshold achieved by this design is analyzed. Assuming the total input power is P_total, it is divided into three signals by a power divider with a ratio of 2:1:1, corresponding to powers of P₁ = 0.5P_total, P₂ = 0.25P_total, and P₃ = 0.25P_total, respectively. Each limiting unit in the respective paths is identical, with its limiting threshold defined as P_th,single. For a multi-channel system, activation of the limiting function necessitates that all channels reach their respective thresholds simultaneously (to ensure cooperative reflection of excess power). This imposes the condition: min{P₁, P₂, P₃} ≥ P_th,single. It follows that P_total ≥ 4P_th,single. Therefore, the limiting threshold of this limiter is P_th,multi = 4P_th,single, while for a single-channel limiter, its limiting threshold is only P_th,single. Thus, the increase in the limiting threshold of this limiter is P_add = 10lg(P_th,multi/P_th,single) = 10lg(4) ≈ 6 dB. Naturally, the foregoing analysis pertains to an ideal scenario. In practical measurements, the T-junction power divider introduces non-negligible insertion loss, which attenuates the effective power delivered to each channel. Furthermore, the limiting module does not exhibit an abrupt activation behavior but rather a gradual transition characteristic. When the input power is at a moderately high level, the channel carrying higher power (Channel 1, 0.5P_total) may initiate limiting earlier than the other channels, thereby mitigating the theoretically anticipated 6 dB improvement. Despite these practical constraints, the multi-channel architecture still achieves a net threshold enhancement of 3 dB, enabling the limiter to tolerate higher input power levels prior to activation. This attribute is critical for withstanding transient high-power signals in beam-scanning systems (e.g., sudden target reflections during beam steering) and enhances the limiter’s robustness within the dynamic electromagnetic environment of C-band beam-scanning systems.

Next, the suppression of distortion in this design is discussed, with specific focus on the suppression of harmonic frequencies. Assuming that the phase shifts of the three paths are θ₁, θ₂, and θ₃, respectively, and each signal undergoes a linear transformation, the resultant combined signal is primarily composed of the fundamental component, along with the third-, fifth-, and seventh-order harmonic signals. The other higher-order harmonics can be negligible. Here, the purpose of multi-path synthesis and phase cancellation is to suppress higher-order harmonics, which can be denoted as HD₃, HD₅, and HD₇, respectively,

$$\left\{\begin{array}{l}H{D}_3=\sqrt{2}A{e}^{-3j{\theta }_1}+A{e}^{-3j{\theta }_2}+A{e}^{-3j{\theta }_3}\\ H{D}_5=\sqrt{2}A{e}^{-5j{\theta }_1}+A{e}^{-5j{\theta }_2}+A{e}^{-5j{\theta }_3}\\ H{D}_7=\sqrt{2}A{e}^{-7j{\theta }_1}+A{e}^{-7j{\theta }_2}+A{e}^{-7j{\theta }_3}\end{array}\right..$$

(5)

Normalizing and applying Euler’s formula yields

$$\overline{H{D}_m}=\sqrt{2}\cos m{\theta }_1+\cos m{\theta }_2+\cos m{\theta }_3-j\left(\sqrt{2}\sin m{\theta }_1+\sin m{\theta }_2+\sin m{\theta }_3\right)$$

(6)

where m = 3, 5, 7. Setting the real and imaginary parts of the harmonic components to be zero results in six equations with three unknowns (θ₁, θ₂, θ₃). Here, a vector-based approach is adopted. We can define

$$\left\{\begin{array}{l}\stackrel{\rightharpoonup }{A}=\sqrt{2}\left(\cos m{\theta }_1-j\sin m{\theta }_1\right)\\ \stackrel{\rightharpoonup }{B}=\cos m{\theta }_2-j\sin m{\theta }_2\\ \stackrel{\rightharpoonup }{C}=\cos m{\theta }_3-j\sin m{\theta }_3\end{array}\right..$$

(7)

Then, we should have

$$\stackrel{\rightharpoonup }{A}=-\left(\stackrel{\rightharpoonup }{B}+\stackrel{\rightharpoonup }{C}\right).$$

(8)

Obviously, if the vectors, $\stackrel{\rightharpoonup }{B}$ and $\stackrel{\rightharpoonup }{C}$, are orthogonal, their combined magnitude equals $\sqrt{2}$, matching the magnitude of vector A. Therefore, we should have

$$\left\{\begin{array}{l}m{\theta }_2=m{\theta }_1-0.75\pi +2n\pi \\ m{\theta }_3=m{\theta }_1+0.75\pi +2p\pi \end{array}\right.,$$

(9)

or

$$\left\{\begin{array}{l}m{\theta }_2=m{\theta }_1+0.75\pi +2n\pi \\ m{\theta }_3=m{\theta }_1-0.75\pi +2p\pi \end{array}\right.,$$

(10)

where n and p are integers. Once the phase shift of the first path is determined, the phase shits of other paths can be obtained from the above equations. However, distinct harmonics necessitate varying phase shifts. In order to satisfy the requirement that each harmonic component remains extremely small, the root mean square (RMS) value of the phase shifts is typically employed. For example, if the phase shift of the first path is θ₁ = π/2, for the third harmonic (m = 3), we should have θ₂ = π/4 and θ₃ = π/12 (n = 0, p = −1); for the fifth harmonic (m = 5), we should have θ₂ = π/10 and θ₃ = 2π/5 (n = 0, p = 0); and for the seventh harmonic (m = 7), we should have θ₂ = π/7 and θ₃ = π/14 (n = 0, p = −1). Then, the RMS values of θ₂ and θ₃ are 1.003 rad (57.5°) and 0.752 rad (43.1°), respectively.

Due to the nonlinear effects of PIN diodes, parasitic parameters, and insertion losses of the microstrip lines [20,21], the simulated results often deviate from the theoretical calculations slightly. Therefore, we need to further optimize the circuit parameters in the simulation platforms. The final phase shifts of the three paths are θ₁ = 90°, θ₂ = 65°, and θ₃ = 45°, respectively.

4. Simulation and Measurement

The limiter was modeled and simulated in the 2020 version of Advanced Design System (ADS) software platform. The circuit layout is shown in Figure 3. The capacitors are Murata model GRM188R71C224KA01. The substrate is F4BM220 with a dielectric constant (ε_r) of 2.2, loss tangent (tanδ) of 0.001, and height (H) of 0.762 mm. Based on transmission line theory, the width of the 50-Ω line is w₁ = 2.30 mm, and the width of the 70.7 Ω line is w₂ = 1.30 mm. The other dimensions are w₃ = 2.00 mm, w₄ = 4.58 mm, and w₅ = 2.68 mm. For circuit miniaturization purposes, the transmission lines in the topmost phase-shifting unit were meandered. The dimensions of the seven meandered transmission line sections (width w and length l) are specified in

Table 1. Transmission line parameters in phase-shifter.

Line	TL1	TL2	TL3	TL4	TL5	TL6	TL7
w/mm	1.44	1.10	1.49	1.49	1.44	2.37	1.26
l/mm	6.90	3.72	3.80	1.82	3.46	5.89	1.70

. In this design, the PIN diode (SMP1320-011LF) from Skyworks is selected. The relevant parameters are listed in

Table 2. SMP1320-011LF parameters.

Parameter	Symbol	Value
Max reverse voltage	VR	50 V
Reverse saturation current	IR	10 μA
Max power dissipation	PD	400 mW
I-layer width	W	7 μm
Carrier lifetime	Tau	400 ns
Ohmic resistance @10 mA	RS	0.75 Ω
Junction capacitance	Cj0	0.15 pF
Package capacitance	CP	0.11 pF
Package inductance	LS	1.8 nH

.

Then, the low-spurious limiter was fabricated and measured. Figure 4 shows the photograph of the design, and Figure 5 shows the simulated and measure transmission properties under small-signal conditions. From Figure 5, we can see that, in the frequency band of 2.6–3.1 GHz, the measured return loss is more than 13.0 dB, and the insertion loss is less than 1.0 dB. In the measurement results, the actual S₁₁ parameter is several dB worse than the simulated value. Potential contributing factors include machining tolerances in the phase shifters, parasitic effects arising from the PIN diodes and capacitors, as well as temperature fluctuations and noise interference during testing, all of which may lead to increased reflection.

Then, the low-spurious limiter was tested under large-signal conditions. For comparison, the limiter circuit without the phase-shifting unit was also fabricated. High-power signal tests were performed utilizing an MG3710A RF signal generator and an N9020A spectrum analyzer. Specifically, the output power of the signal generator was incrementally increased from 0 dBm to 17.0 dBm, while frequency points were sampled at 100 MHz intervals across the entire operating frequency band. Figure 6 presents the measured output power of the fundamental and the third harmonic with and without the phase shifters at an input power of 17.0 dBm. From the figure, we can see that for the 17.0 dBm input power, the output fundamental wave is limited to around 11.5 dBm. The third harmonic generated by the limiter circuit without phase shifters fluctuates between −4.4 dBm and −13.8 dBm, while that of the limiter circuit with the phase shifters fluctuates between −27.7 dBm and −40.6 dBm. Therefore, the third harmonic suppressions are improved more than 23.0 dB with the phase cancellation technology. Furthermore, owing to the suppression of the third harmonic, the fifth and seventh harmonic components are submerged in the noise floor, rendering them unmeasurable. Therefore, the phase-shifter-equipped circuit achieves a harmonic suppression ratio of more than 38.0 dB in the frequency band of 2.6–3.1 GHz.

A comparison of key parameters between the proposed limiter and those in the referenced studies is provided in

Table 3. Key parameter comparison: proposed limiter vs. limiters in listed documents.

Ref.	Limiter Type	Insertion Loss	Harmonic Suppression (THD/HSR)	Target Harmonics	Application Scenario
[3]	Solid-state FCLID	Low (with a 100 μH inductor)	Reduced by ~50% (adjusting Imin)	Wideband harmonics	Low-voltage distribution systems
[4]	FCLID (with transformer)	Not specified	0.42% (THD)	5th, 7th, 11th, 13th harmonics	Low-voltage distribution systems
[5]	Resistive Superconducting RSFCL	Very low (superconducting state)	3.9~13% (THD)(determined by the superconducting element volume)	Broadband harmonics	High-power systems
[6]	Inductive Superconducting SFCL (12-pulse)	Low	1.9~3.1% (THD) (with tuned filters)	11th, 13th harmonics	High-voltage transmission systems
[7]	76–81 GHz Radar Receiver Limiter	~1 dB	Not specified	IM3	76–81 GHz automotive radar
[8]	Converter-based FCL	Not specified	3.0~5.3% THD	Line voltage harmonics	Power distribution networks
This work	Multi-path synthesis and phase cancellation	<1.0 dB	>38.0 dB (HSR)	Third, fifth, seventh harmonics	C-band radar, communication systems

Note: THD: total harmonic distortion; HSR: harmonic suppression ratio.

. As shown, the proposed design outperforms the counterparts in harmonic suppression: its HSR (>38.0 dB) exceeds the converter-based FCL (THD reduced from 5.3% to 3.0% in standby mode) and solid-state FCLID (~50% harmonic reduction). Its insertion loss (<1.0 dB) is comparable to the 76–81 GHz radar limiter (~1 dB) and avoids filter-induced losses in inductive superconducting SFCLs. The 3.0 dB threshold improvement, unmatched by resistive superconducting RSFCLs or transformer-equipped FCLIDs, enhances its suitability for dynamic C-band scenarios. Thus, it offers a superior solution for C-band radar and communication front-ends.

5. Potential Application in C-Band Beam-Scanning Antenna Systems

The proposed low-spurious and high-threshold limiter exhibits significant potential for integration into C-band beam-scanning antenna systems, where robust protection against high-power signals and suppression of spurious emissions are critical. Beam-scanning systems, such as those used in radar, satellite communication, and intelligent transportation infrastructure (e.g., roadside units for vehicle-to-infrastructure applications), often operate in dynamic electromagnetic environments, encountering fluctuating input power levels from target reflections, interference, or multi-user signals [22].

The limiter’s enhanced threshold (improved by 3.0 dB) ensures it can withstand sudden high-power incursions during beam transitions, preventing damage to sensitive receiver components like low-noise amplifiers (LNAs) and mixers. This is particularly valuable in scenarios where beam pointing shifts rapidly, exposing the system to transient high-power signals from unexpected sources.

Moreover, the exceptional harmonic suppression (>38.0 dB HSR in 2.6–3.1 GHz) addresses a key challenge in beam-scanning systems: spurious emissions generated by nonlinear devices (e.g., PIN diodes, power amplifiers) can degrade the signal-to-noise ratio (SNR) and interfere with adjacent frequency bands. By mitigating harmonics through phase cancellation, the limiter minimizes interferences that could otherwise corrupt beamforming accuracy or communication integrity.

The low insertion loss (<1.0 dB) and good return loss (>13.0 dB) further ensure minimal signal degradation and impedance matching, which are essential for maintaining the efficiency of beam-scanning arrays—especially in phased-array configurations where signal amplitude and phase stability directly impact beam steering precision.

In summary, the limiter’s combined attributes of high threshold, low spurious response, and efficient signal transmission make it a promising candidate for enhancing the reliability and performance of C-band beam-scanning antenna systems in diverse applications.

6. Conclusions

This paper first expounds on the limiting mechanism of PIN diodes under high-frequency conditions. Subsequently, in the design of a limiter operating within the 2.6–3.1 GHz frequency band, power dividers and phase shifters are employed to achieve multi-path synthesis and phase cancellation. Both the simulation and experimental results validate the effectiveness of the proposed design: the fabricated limiter achieves low insertion loss (<1.0 dB), favorable return loss (>13.0 dB), and high harmonic suppression (>38.0 dB) within the target frequency range. These performance metrics, combined with the 3.0 dB improvement in limiting threshold enabled by multi-channel power synthesis, demonstrate the design’s robustness and practical value.

Overall, the proposed low-spurious high-threshold limiter addresses key challenges in C-band receiver protection and signal integrity, highlighting its significant potential for engineering applications in radar, communication, and beam-scanning systems.