Design and Analysis of 3–12 GHz UWB Flat Gain LNA in 0.15 µm GaAs pHEMT Technology

Abstract

This paper presents the design and implementation of an ultra-wideband (UWB) and flat gain low noise amplifier (LNA) using 0.15 µm GaAs pHEMT technology, specifically tailored for applications that benefit from multi-band capability, such as satellite communication. The designed LNA consists of three stages: Two stages are cascoded using source degeneration with a resistor for low noise and high linearity, and the third cascaded stage is utilized for high gain. The designed UWB LNA exhibits a measured gain of 17.4 ± 1 dB between 312 and GHz and a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz). It achieves a noise figure (NF) of 2.5–4.3 dB and an output P1dB of 15 dBm. The chip size is $3\times 1$ ${\mathrm{mm}}^2$, and it operates without the need for any external components. When compared to LNAs in the literature, the proposed design stands out for its flat gain in the specified frequency band, making the LNA particularly attractive for volume-limited and power-constrained applications.

1. Introduction

Ultra-wideband (UWB) technology has become more attractive due to the demand for higher bandwidth and data rate than other existing technologies [1]. In UWB applications, the performance of low noise amplifiers (LNAs) is crucial since the noise and gain performance of the LNA determines the overall sensitivity of the system [2]. Various UWB LNA designs based on GaAs pHEMT technology have been reported in the literature [3,4,5,6,7,8,9]. In [3], a cascode LNA with source degeneration is introduced to enhance noise figure (NF) and stability. Similarly, ref. [4] details an LNA design without negative RLC feedback, while [5,6,7,8,9] employ inductive source degeneration for different frequency bands.

This study presents the design, fabrication, and measurement of a monolithic microwave integrated circuit (MMIC) LNA using a 0.15 µm GaAs pHEMT process. By integrating cascode and cascade topologies with the resistive source degeneration technique (RSDT), the design enhances bandwidth and gain flatness. The LNA achieves a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz), a peak gain of 18.45 dB at 11 GHz, and input/output return losses of less than −10 dB within the band. The integration of RSDT with cascode topology significantly enhances flat gain performance compared to existing UWB LNAs [10,11,12,13].

The remainder of this paper is organized as follows: Section 2 provides a detailed overview of the circuit design, including the employed process technology, analytical calculations, and key design parameters. This section also presents a parametric analysis focusing on the dominant factors affecting gain flatness. Section 3 presents the simulation and measurement results of the fabricated LNA. In Section 4, the results are discussed, the key features of the proposed LNA are highlighted, and its performance is compared with similar designs reported in the literature. Finally, in Section 5 conclusions are drawn.

2. Circuit Design

In this section, the circuit design is explained in detail. The schematics of the designed LNA are shown in Figure 1a, and the small signal model of the device shown is in Figure 1b. Briefly, the design process is based on analytically evaluating the gain and input impedance of the design in Figure 1 for the available values in the foundry’s process design kit (PDK) considering bandwidth, flat gain, etc., and determining the most influencing parameters on the gain. Then, a parameter sweep is performed using the circuit simulations for those parameters to further improve the design. Finally, EM simulations are performed to complete the design process.

At the end of this design process, the determined values of all passive components such as inductors, capacitors, and resistors used in the design, along with the sizing details of the active devices including the transistors, are provided at

Table 1. Component values used in the designed LNA.

Parameter	Value	Parameter	Value	Parameter	Value
$L_1$	0.37 nH	$C_2$	4.16 pF	$R_5$	60 $\Omega$
$L_2$	1.2 nH	$C_3$	4.16 pF	$R_6$	300 $\Omega$
$L_3$	6.7 nH	$R_1$	70 $\Omega$	$R_7$	1680 $\Omega$
$L_4$	0.9 nH	$R_2$	5 $\Omega$	$M_1$	$4\times 70$ ($\mathsf{\mu }$m) CPW
$L_5$	1.2 nH	$R_3$	92 $\Omega$	$M_2$	$4\times 40$ ($\mathsf{\mu }$m) CPW
$C_1$	4.16 pF	$R_4$	5 $\Omega$	$M_3$	$4\times 40$ ($\mathsf{\mu }$m) CPW

. These components were carefully selected to achieve the desired impedance matching, gain, and stability characteristics, while also considering layout feasibility and EM behavior.

2.1. Process Technology and Analysis

An LNA with a single transistor offers low noise figure ($NF$) but insufficient gain, necessitating cascode and cascade topologies for improvement [14]. While the cascade topology enhances gain and linearity [15], additional stages are required to meet gain targets [16]. However, ensuring unconditional stability, quantified by the Roulette stability factor (k), becomes more challenging as the number of stages increases [17]. Specifically, increasing the number of stages improves the gain parameter ($S_{21}$) but has minimal impact on input and output return losses ($S_{11},S_{22}$) [18]. To address these challenges, instead of a three-stage cascaded design [19], a cascode configuration is employed in the first two stages to leverage its advantages, including low noise, optimized input matching, enhanced linearity, and improved stability with proper design considerations [20]. A third cascaded transistor is then added to further boost gain, as shown in Figure 1a.

2.2. Circuit Design and Calculations

Figure 1a shows the schematic of the proposed GaAs-based UWB LNA consisting of two cascoded and a third cascaded stages, and Figure 1b shows the small signal model of the GaAs pHEMT device. In Figure 1b, $L_g$, $L_s$, $C_{gs}$, and $g_m$ represent the input gate inductor, source degeneration inductor, parasitic gate–source capacitance of the input transistor, and the transconductance of the GaAs pHEMT device in units of Siemens (A/V), respectively.

The input impedance of the first stage is critical for $NF$ optimization. Therefore, the values of $C_1$, $L_1$, $L_2$, and $R_1$ in Figure 1a are selected according to [21], and the input impedance of the GaAs pHEMT device is calculated as shown in [22]. As a result, the impedance seen from the input port of the LNA, i.e., $Z_{\mathrm{in}}$, can be calculated as

$$\begin{array}{cc}\hfill Z_{\mathrm{in}}& =\left(-{\displaystyle \frac{j}{\omega C_1}}+j\omega L_1\right)-j\left({\displaystyle \frac{g_{m_1}{R}_2}{\omega C_{g{s}_1}}}\right)\hfill \\ \hfill & +\left((j\omega L_2+R_1)//\left(R_2+j\left(\omega L_g-{\displaystyle \frac{1}{\omega C_{g{s}_1}}}\right)\right)\right).\hfill \end{array}$$

(1)

In most of the GaAs LNA designs, an external capacitance between the gate and the source of the first device is required to cancel out the imaginary part of the input impedance $Z_{\mathrm{in}}$ [23]. Instead, in this work, $Z_{\mathrm{in}}$ is adjusted as close as possible to the optimum wideband input impedance value via evaluating Equation (1) for the parameters $L_1$, $L_2$, $C_1$, and $R_1$ using manufacturable capacitor, inductor, and resistor values available in PDK.

The voltage gain of a FET device ($A_v$) is generally expressed as shown in [24]; since the third device is cascaded to the second device, the total voltage gain ($A_o$) of the entire LNA can be expressed as the product of individual voltage gains of these three stages ($A_{v1}$, $A_{v2}$, and $A_{v3}$), i.e., $A_o=A_{v3}\times A_{v2}\times A_{v1}$, which can be obtained as

$$\begin{array}{cc}\hfill A_o& =\stackrel{A_{v1}}{\overbrace{{\displaystyle \frac{g_{m_1}\left(j\left(\omega L_{d_1}-\frac{1+g_{m_2}{R}_2}{\omega C_{d{s}_1}}\right)+R_2\right)}{\left(1+g_{m_1}{R}_2\right)}}}}\hfill \\ \hfill & \times \underset{A_{v2}}{\underbrace{{\displaystyle \frac{-j{g}_{m_2}\omega L_3\Vert \left(j\omega L_4+\frac{1}{j\omega C_3}+\left(\left(j\omega L_5+R_3\right)\Vert j\omega L_{g_3}+R_4-\frac{j}{\omega C_{g{s}_3}}+\frac{g_{m_3}{R}_4}{j\omega C_{g{s}_3}}\right)\right)}{\left(1+j{g}_{m_2}\left(\omega L_{d_1}-\frac{1+g_{m_2}{R}_2}{\omega C_{d{s}_1}}\right)+R_2\right)}}}}\hfill \\ \hfill & \times \underset{A_{v3}}{\underbrace{{\displaystyle \frac{-g_{m_3}\left(R_5\Vert R_6\Vert \left(R_7+\frac{1}{j\omega C_2}\right)\right)}{\left(1+g_{m_3}{R}_4\right)}}}}.\hfill \end{array}$$

(2)

In Equation (2), to obtain $A_{v2}$, the impedance seen from the drain of the first device, i.e., the output impedance of the first stage $Z_{{\mathrm{out}}_1}$, and the input impedance of the third device $Z_{{\mathrm{in}}_3}$ are required to determine the voltage gain of the second stage. Assuming the large resistance values as open circuit, $Z_{{\mathrm{out}}_1}$ and $Z_{{\mathrm{in}}_3}$ can be calculated from the small signal model given in Figure 1b as

$$Z_{{\mathrm{out}}_1}=j\left(\omega L_{d_1}-{\displaystyle \frac{1+g_{m_1}{R}_2}{\omega C_{d{s}_1}}}\right)+R_2\Vert {\displaystyle \frac{1}{g_{m_2}}}\Vert R_1,$$

(3)

$$Z_{{\mathrm{in}}_3}=j\omega L_{g_3}+R_4-{\displaystyle \frac{j}{\omega C_{g{s}_3}}}+{\displaystyle \frac{g_{m_3}{R}_4}{j\omega C_{g{s}_3}}},$$

(4)

where $L_d$ and $C_{ds}$ represent the drain inductor and parasitic drain-source capacitance, respectively, as shown in Figure 1b.

A similar evaluation to $Z_{\mathrm{in}}$ in Equation (1) is also carried out for $A_o$ via evaluating Equation (2) to obtain the widest bandwidth and flattest gain using the available values in PDK. By examining Equation (2), it is observed that the most dominant components influencing $A_o$ are $L_1$, $L_4$, $R_2$, and $R_4$.

2.3. Parametric Analysis

A parametric sweep is performed for the values of $L_1$, $L_4$, $R_2$, and $R_4$ to further improve the design. Each of these components are individually varied to demonstrate their effect on $A_o$, while other component values are fixed to the values given in Table 1 to isolate their specific effect on the amplifier characteristics.

Gate inductor $L_1$ is critical for the flat gain in the frequency range, as shown in Figure 2a. Since $L_1$ is also a part of the input-matching network, as the value of $L_1$ is increased from 0.37 nH, $S_{11}$ performance of the designed LNA increases, and $NF$ increases as well. When the value of $L_1$ is increased higher than 1.2 nH, the flatness of the gain deteriorates, as seen in Figure 2a.

According to the analysis results in previous section, it is observed that the inductor $L_4$ has the highest effect on the gain flatness of the amplifier. As illustrated in Figure 2b, the flatness of the gain is very sensitive to the value of $L_4$, and variations in $L_4$ cause significant deviations in the gain response; specifically, a decrease in $L_4$ results in reduced voltage gain.

In the proposed design, source degeneration resistors $R_2$ and $R_4$ are used instead of inductors to improve the gain flatness and simplify the layout, and are selected as 5 $\Omega$ resistors. This design choice, i.e., using resistors instead of inductors, introduces additional thermal noise; however its impact on overall NF remains limited due to the low resistance values. Moreover, it enables better control over gain flatness throughout the frequency band without relying on sensitive on-chip inductors. The values of the resistors have a direct effect on providing high voltage gain since they are located in the denominator of the total voltage gain in Equation (2). In the proposed design, the trade-off between slightly increased NF and improved gain flatness is considered acceptable. Consequently, increasing or decreasing the values of $R_2$ and $R_4$ results in degraded NF, and increasing the values of the resistors decreases the forward transmission coefficient $S_{21}$, as shown in Figure 2c,d, as expected.

3. Measurement Results

The proposed LNA MMIC is fabricated using 0.15 µm GaAs pHEMT technology [25], as shown in Figure 3. Specifically, Figure 3a shows the die microphotograph of the fabricated LNA, and Figure 3b illustrates the 3D microscope image of the chip, providing a more detailed view of the layout. The fabricated chip occupies an area of $3\times 1$ ${\mathrm{mm}}^2$. The supply voltage of the LNA is 3.3 V with a current consumption of 270 mA. It should be emphasized here that there is no need for any off-chip capacitors or inductors for the measurements since all necessary matching, biasing, and decoupling functionalities are fully integrated on-chip, which enables a compact and standalone measurement setup without the need for any external circuit elements. This feature significantly simplifies the test environment, and from one point of view, validates the completeness of the integrated design.

The fabricated LNA was characterized through on-wafer measurements using GSG probes under a FormFactor MPS150 thermal probe station (FormFactor Inc., Livermore, CA, USA). S-parameters were measured using a Rohde & Schwarz ZVA40 vector network analyzer (Rohde & Schwarz GmbH & Co. KG, Munich, Germany). The NF was evaluated by the Y-factor method using a Noisecom NC346B noise source (Noisecom, Parsippany, NJ, USA) and a Keysight N8975A noise figure analyzer (Keysight Technologies, Santa Rosa, CA, USA). For linearity metrics, including output 1-dB compression point (P1dB) and output third-order intercept point (OIP3), measurements were conducted using a Rohde & Schwarz SMB100A signal generator and a spectrum analyzer (Rohde & Schwarz GmbH & Co. KG, Munich, Germany). All DC biases were supplied by a Keysight E3640A DC power supply. During the entire measurement process, ambient conditions were kept thermally stable to ensure accuracy (Keysight Technologies, Santa Rosa, CA, USA).

The measured and simulated S-parameters are presented in Figure 4. As shown in Figure 4, there is good agreement in the simulation and measurement results. It can be seen in Figure 4 that the fabricated LNA achieves a maximum forward gain ($S_{21}$) of 18.45 dB at 11 GHz, while the LNA shows minimum and average gains of 15.4 dB and 16.3 dB throughout 1.6 GHz to 14 GHz frequency band, respectively. The gain of the LNA is relatively flat in this band, with a 3 dB fractional bandwidth of 158 %, which is notably wide and highlights the broadband nature of the design. The gain at the start and end of the frequency spectrum, i.e., 1 GHz and 15 GHz frequencies, are 8 dB and 8.9 dB, respectively.

The input return loss ($S_{11}$) of the fabricated LNA is measured as −8.8 dB at 1 GHz, and remains below −10 dB from 1.6 GHz to 14 GHz, indicating good input matching over a wide frequency range, as shown in Figure 4. Similarly, the output return loss ($S_{22}$) of the LNA is measured as −5 dB at 1 GHz; then, it drops below −10 dB around 3.5 GHz and maintains this level up to 15 GHz. These results demonstrate that both input and output ports are well matched in the intended operating bandwidth, contributing to the amplifier’s overall performance and stability.

In addition, Figure 5a plots the Rollett’s stability factor (k), a widely accepted criterion to assess unconditional stability in microwave circuits [17], which is calculated in AWR Microwave Office using

$$k={\displaystyle \frac{1-|S_{11}{|}^2-|S_{22}{|}^2+{|S_{22}{S}_{11}-S_{21}{S}_{12}|}^2}{2|S_{12}\left|\right|S_{21}|}}.$$

(5)

Maintaining $k>1$ throughout the operating frequency range is essential to ensure robust and predictable performance. It can be seen from Figure 5a that k consistently remains above unity within the entire simulation range and the minimum value of k is 6.37 at 11.3 GHz. This confirms that the proposed LNA design maintains unconditional stability not only within the intended operating band (e.g., 3–12 GHz) but also over a broader spectrum.

Another essential parameter is the noise factor, denoted as F, used to evaluate the noise performance of an amplifier. This metric quantifies the degradation of the signal-to-noise ratio (SNR) as a signal passes through a two-port network and is defined as the ratio between the input and output SNRs, i.e., ${\mathrm{SNR}}_{\mathrm{IN}}$ and ${\mathrm{SNR}}_{\mathrm{OUT}}$, respectively [26]:

$$F={\displaystyle \frac{{\mathrm{SNR}}_{\mathrm{IN}}}{{\mathrm{SNR}}_{\mathrm{OUT}}}}={\displaystyle \frac{S_{\mathrm{IN}}/N_{\mathrm{IN}}}{S_{\mathrm{OUT}}/N_{\mathrm{OUT}}}},$$

(6)

where $S_{\mathrm{IN}}$ and $S_{\mathrm{OUT}}$ represent the signal power at the input and output of the amplifier, respectively, and $N_{\mathrm{IN}}$ and $N_{\mathrm{OUT}}$ denote the corresponding noise powers. $F=1$ implies a noise-free amplifier, while values greater than 1 reflect an increased noise contribution. For convenience, this parameter is typically expressed in logarithmic scale in decibels (dB) as the following noise figure:

$$NF=10{log}_{10}\left(F\right).$$

(7)

The measured NF is 4.5 dB at 2 GHz and gradually decreases with the frequency increase, falling below 3 dB after 8 GHz. Even though there is a 0.5 dB difference with the simulated and measured NF, their behaviors are similar as seen in Figure 5b.

P1dB and OIP3 characteristics of the LNA are illustrated in Figure 6a and Figure 6b, respectively. Both the measured and simulated P1dB values are in good agreement. The P1dB performance remains relatively flat in the operating frequency range of 1.6 GHz to 14 GHz, exhibiting values above 15.5 dBm throughout this band. This confirms that the amplifier maintains linear behavior under high input power conditions. Similarly, the OIP3 performance maintains values around 25.5 dBm between 3 and 13 GHz. This indicates that the LNA offers robust linearity in terms of third-order intermodulation distortion throughout the wideband operating range. Based on these measurements, the corresponding input-referred third-order intercept point (IIP3) is 8.5 dBm, as seen in Figure 7.

4. Discussion and Comparison

The results presented in the previous section demonstrate the high and broadband gain, gain flatness, linearity, and low noise characteristics of the designed LNA over a wide frequency range, making it highly suitable for broadband RF front-end applications [27].

Table 2. Comparison of the designed and fabricated LNA and the LNAs in the literature.

Ref.	Tech. GaAs pHEMT	$\mathbf{B}\mathbf{W}$ [GHz]	$\mathbf{B}\mathbf{W}$frac [%]	Gain [dB]	Pdc [mW]	$\mathbf{N}\mathbf{F}$ [dB]	Chip Area [mm2]	FOM [%GHz/ mW]	GF
[28]	0.15 µm	1–12.5	165	23	87.5	1.25–2.5	3	194	0.033
[29]	0.15 µm	3–14	122	18	600	<2.3	7.44	17.5	0.033
[30]	0.15 µm	3–15	133	28	200	2.5	2	89	0.047
[31]	0.15 µm	3.3–11.3	109	28.5	85	5–2	6	78	0.114
[32]	0.15 µm	6–21	111	23	135	1.03–1.76	1.04	161	0.030
[33]	0.15 µm	0.1–20	198	28	505	3.1–5.8	1.53	38	0.046
[34]	0.15 µm	1–40	170.2	26	207	2.8–3.9	0.06	239	0.055
[35]	0.25 µm	1.5–2.7	57	20	300	0.4–0.8	9	5.7	0.059
[36]	0.1 µm	73–101	32.2	23	96	5.5–5.7	0.98	38	0.020
This work	0.15 µm	3-12	120	18	270	2.5-4.3	3	17	0.025
This work *	0.15 µm	1.6-14	158	18	270	2.9–4.9	3	54	0.040

* 3 dB frequency band.

summarizes the important parameters for the designed and fabricated LNA, denoted as “This work,” for both the intended design frequency band and 3 dB frequency band and compares the properties of the LNA and the LNAs based on GaAs pHEMT technology operating within various frequency bands in the literature. The first four rows of Table 2 are specifically selected and gathered because their operating frequency ranges are similar to the proposed LNA.

In order to obtain an intuition about the design, the figure of merit (FOM) [24] is usually calculated. The definition of FOM, which is related to gain in dB, bandwidth ($BW$) in GHz, fractional bandwidth ($B{W}_{\mathrm{frac}}$) in percentage, $NF$ in dB, and DC power consumption ($P_{\mathrm{dc}}$) in mW, is given as

$$\mathrm{FOM}={\displaystyle \frac{S_{21}\left[\mathrm{dB}\right]\times BW\left[\mathrm{GHz}\right]\times B{W}_{\mathrm{frac}}[\%]}{NF\left[\mathrm{dB}\right]\times P_{\mathrm{dc}}\left[\mathrm{mW}\right]}}.$$

(8)

The proposed LNA achieves an FOM of 17 %GHz/mW and a fractional bandwidth ($B{W}_{\mathrm{frac}}$) of 120 % for the 3–12 GHz band, and for the 3 dB frequency band FOM increases to 54 %GHz/mW with an increased $B{W}_{\mathrm{frac}}$ of 158%. Compared to the similar works in Table 2, the proposed LNA exhibits a lower FOM for the 3–12 GHz band and an acceptable FOM for the 3 dB frequency band. On the other hand, e.g., in [32], $S_{22}$ exceeds −10 dB over a significant portion of the 6–12 GHz band; ref. [28] has a high FOM, its gain varies by 5 dB, and $S_{22}$ exceeds −10 dB between 9 and 12.5 GHz. Although ref. [31] reports a high FOM, its input return loss ($S_{11}$) remains above −10 dB for a substantial part of its operating bandwidth. Similarly, [34] achieves a higher FOM by targeting higher frequencies but lacks gain flatness. Consequently, designs with higher FOM suffer from significant gain variations, which can reduce their effectiveness in applications requiring flat gain performance. Although some of the works achieve broader bandwidths, they tend to do so with the trade-off of increased power consumption, as in [33], or NF, as in [36].

It is obvious that simply considering the FOM does not provide any insight into the gain flatness. Since the aim of the proposed design is to obtain flat gain over a wide frequency range, as a measure, gain flatness (GF) is introduced to assess the uniformity of the gain in the operating frequency range and evaluated as:

$$\mathrm{GF}={\displaystyle \frac{1}{\left[f_{max}-f_{min}\right]}}{\int }_{f_{min}}^{f_{max}}{\displaystyle \frac{\left|S_{21}\left(f\right)-S_{21\mathrm{ave}}\right|}{\left|S_{21\mathrm{ave}}\right|}}df,$$

(9)

where $S_{21}\left(f\right)$ is the gain at frequency f and $S_{21\mathrm{ave}}$ is the average gain over $f_{min}$ to $f_{max}$. It can be seen from Equation (9) that GF is unit-less and lower GF values indicate a more uniform gain in the frequency range with the promotion of a larger bandwidth.

The GF for the proposed LNA is 0.025 within the 3–12 GHz frequency range, suggesting that its gain stands out compared to the LNAs listed in Table 2. For the 3 dB frequency range of 1.6–14 GHz, the GF is 0.040, which is still noteworthy. Among the referenced studies, only [36] achieves a better GF, but its higher operating frequency and excessive NF reduce its overall performance; eventually, a direct comparison is less meaningful despite its improved gain uniformity. Other studies, including [28,29,30,31,33,34], show considerable gain fluctuations, further highlighting the superiority of the gain flatness of the proposed design.

Consequently, the suggested LNA achieves a reasonable balance between FOM and GF, maintaining both efficiency and consistent gain throughout its operational bandwidth. While the FOM is lower than some prior designs, it provides the best GF over the specified bandwidth, which makes it a viable choice for wideband applications that require both performance consistency and optimized power usage.

5. Conclusions

A UWB LNA utilizing resistive source degeneration, both cascode and cascade topologies, fabricated with a 0.15 µm GaAs pHEMT process, is presented. Simulated and measured S-parameters show good agreement. The LNA achieves a peak gain of 18.45 dB at 11 GHz with a 3 dB bandwidth of 12.4 GHz (1.6–14 GHz). The proposed design offers high gain and low NF without external feedback capacitors. Although it employs conventional topologies, the design stands out for its gain flatness, making it well-suited for volume-limited and power-constrained applications.