A Novel Loss-Balancing Modulation Strategy for ANPC Three-Level Inverter for Variable-Speed Pump Storage Applications

Abstract

The non-uniform thermal distribution in the active neutral-point clamped (ANPC) topology causes significant thermal gradients during high-power operation, restricting its use in large-capacity power conversion systems like variable-speed pumped storage. This study introduces a novel hybrid fundamental frequency modulation strategy. Through a dynamic allocation mechanism based on a reference signal, this strategy alternates inner and outer power switches at the fundamental frequency, ensuring balanced switching frequency across devices. Consequently, it effectively mitigates the inherent loss imbalance in conventional ANPC topologies. Quantitative analysis using a power device loss model shows that, compared to conventional carrier phase-shift modulation, the proposed method reduces total system losses by 39.98% and improves the loss-balancing index by 18.27% over inner-switch fundamental frequency modulation. A multidimensional validation framework, including an MW-level hardware platform, numerical simulations, and test data, was established. The results confirm the proposed strategy’s effectiveness in improving power device thermal balance.

1. Introduction

As the global energy transition accelerates, the share of renewable energy sources like wind and solar power in the grid continues to grow, profoundly affecting its stability [1,2]. Energy storage, a key regulatory resource, is essential for maintaining grid stability. Among energy storage technologies, pumped storage dominates due to its large capacity, long lifespan, and low cost [3,4,5]. However, conventional pumped storage systems exhibit slow dynamic responses and limited regulation accuracy, which constrain their effectiveness in providing fast frequency regulation, accurate real-time power balancing, and flexible ancillary services required by modern power grids. As a result, variable-speed pumped storage, with rapid response, adaptability to water head variations, and broad regulation range, has become a key trend in pumped storage evolution [6].

The high power capacity and cost constraints of full-power converters make large-scale implementation of variable-speed pumped storage units above 300 MW challenging. Consequently, AC excitation variable-frequency technology remains the preferred choice for large-capacity variable-speed pumped storage projects [7]. By adjusting the rotor winding current’s frequency and phase, this technology enables wide-range, continuous speed regulation, ensuring fast dynamic response and strong grid support. Additionally, as the converter processes only slip power, its capacity requirement is significantly lowered. As the core of an AC excitation system, the converter’s performance directly impacts unit efficiency and overall system reliability. Converter topologies fall into two main categories: indirect AC-DC-AC and direct AC-AC conversion. For high-power, high-voltage applications, cascaded H-bridge (CHB), and modular multilevel converters (MMC) are widely used for their voltage-stacking capability [8,9]. Among these, multilevel topologies are the dominant choice for high-power converters, as their stepped output reduces switching stress, enhances waveform quality, and minimizes filter size. In multilevel topologies, the traditional neutral-point clamped (NPC) inverter generates a three-level output using clamping diodes. However, it has inherent drawbacks, including uneven power loss distribution and neutral-point voltage fluctuations [10,11,12], which restrict output power. To mitigate these issues, the active neutral-point clamped (ANPC) topology replaces some clamping diodes with active switches, allowing for flexible state control. This method optimizes loss distribution, enhances voltage balancing, and boosts system efficiency, ultimately increasing power capacity [13,14,15]. However, the additional switches in ANPC topology increase control complexity. Moreover, uneven loss distribution and related thermal management challenges hinder its large-scale application.

A suitable pulse-width modulation (PWM) strategy provides a more practical solution than topology optimization for mitigating uneven temperature rise in ANPC three-level inverters. Without hardware modifications, a well-designed PWM strategy can balance power loss and adapt to varying load conditions [16,17,18,19], ensuring the long-term stability of high-capacity converters. The PWM strategy directly controls power device states and indirectly affects their loss characteristics. To address switching loss imbalances, various modulation strategies have been proposed. To address switching loss imbalances, various modulation strategies have been proposed. Ma et al. [17] introduced modulation waves that enable internal and external switches to achieve distinct sequences by selecting an appropriate stress-in/stress-out mode ratio, distributing losses. However, insufficient adaptability to complex operating conditions could lead to the introduction of additional harmonics. The strategy in [20] employed a single neutral state (O), directing neutral-point current through two neutral-line paths to reduce conduction losses in internal switches. However, frequent operation of the external switching devices resulted in significant switching losses. Deng et al. [21] proposed an adaptive frequency-doubling modulation strategy with two modulation waves. This approach adjusted the switching state duty cycle for each period to optimize power loss distribution. However, frequent switching operations within a single period could result in output voltage saturation. Wang et al. [22] examined inverter modulation strategies under unity and non-unity power factors. Considering the phase angle of the non-unity power factor, switching device operating modes were reconfigured to reduce loss differences between internal and external switches. To reduce inverter power loss, Song et al. [23] adopted control strategies tailored for high and low switching frequency modes. In low-frequency mode, a single PWM mode was used, while in high-frequency mode, two PWM modes are combined based on a specific duty cycle. Chen et al. [24] proposed a mode-switching strategy using optimization algorithms to balance device junction temperatures, with the mode ratio derived from optimization for different modulation degrees and power factor angles. However, this method involved high computational complexity. Leveraging the low conduction loss of IGCT devices, low-frequency modulation strategies can significantly reduce converter losses. As pumped storage units scale to higher power levels, the shortcomings of traditional modulation strategies become more evident. Meanwhile, high-order modulation algorithms are limited by controller computing capacity, making real-time operation within short switching cycles difficult. Thus, developing novel modulation strategies that balance high efficiency and computational simplicity is a pressing need.

Converters used in variable-speed pumped storage units commonly adopt the three-level active neutral-point clamped (ANPC) topology based on integrated gate-commutated thyristors (IGCTs) [25,26]. Given the low conduction loss characteristic of IGCT devices, incorporating a low-frequency modulation approach can significantly optimize converter losses. This paper proposes a novel and easily implementable loss-balancing strategy for ANPC inverters, leveraging the advantages of both inner and outer switch fundamental frequency modulation. By alternating the operation of inner and outer switches at the fundamental frequency, the proposed method ensures a balanced distribution of switching events and switching losses, thereby enhancing overall system efficiency.

The paper is structured as follows: Section 2 analyzes the topology, switching states, and commutation methods of the ANPC three-level inverter. It also discusses the switching losses of power devices under various operating conditions. In Section 3, three conventional PWM strategies are introduced, and the working principle of the novel hybrid base frequency modulation strategy proposed in this paper is explained in detail. Section 4 presents the loss calculation model for the ANPC three-level converter’s power devices. Section 5 provides a comparative analysis of total losses and loss distribution under different modulation strategies. It also examines the impact of power factor, carrier frequency, and operating conditions on loss distribution for the proposed PWM strategy. Finally, the feasibility and effectiveness of the hybrid base frequency modulation scheme for this topology is verified by simulation and experiments.

2. Principle of Operation of ANPC Three-Level Inverter

2.1. Topological Structure

The topology of the active neutral-point clamped (ANPC) converter based on IGCT is shown in the Figure 1. Each phase unit has six IGCTs, T1, T2, T3, T4, T5, and T6 (respectively, with freewheeling diode D1, D2, D3, D4, D5, and D6 in parallel); capacitors C1 and C2 are connected to the positive and negative DC bus, respectively; and a neutral point is drawn between Cbus1 and Cbus2 and connected to the midpoints of T5 and T6.

Compared to the NPC topology, the ANPC converter uses fully controlled power devices, such as IGCTs, as clamping devices, and is equipped with anti-parallel freewheeling diodes, allowing for it to output three voltage levels: positive (P), negative (N), and zero (O). Since the clamping current has bidirectional flow capability, the ANPC inverter has four possible zero-voltage current paths, denoted as OU1, OU2, OL1, and OL2. By appropriately selecting one of these four zero-voltage current paths, it is possible to effectively balance the losses and junction temperatures of the power devices.

2.2. Switching State

According to different switching states and current flow paths, six states can be achieved, which are shown in

Table 1. ANPC three-level converter switching states.

States	${\mathit{T}}_1$	${\mathit{T}}_2$	${\mathit{T}}_3$	${\mathit{T}}_4$	${\mathit{T}}_5$	${\mathit{T}}_6$	Output
P	1	1	0	0	0	1	$+U_{dc}/2$
OU1	0	1	0	0	1	0	0
OU2	0	1	0	1	1	0	0
OL1	0	0	1	0	0	1	0
OL2	1	0	1	0	0	1	0
N	0	0	1	1	1	0	${-U}_{dc}/2$

.

The switching states and current paths for each state are described as follows:

State 1: Positive level and output current greater than zero

IGCT T1 and T2 are turned on, and T6 is also ON. The current is output from the positive bus through the IGCT T1 and T2, as shown in Figure 2a.

State 2: Negative level and output current greater than zero

IGCT T3 and T4 are turned on, and T5 is also ON. The current is output from the positive bus through the FWD D3 and D4, as shown in Figure 2b.

State 3: Positive level and output current less than zero

IGCT T1 and T2 are turned on, and T6 is also ON. The current flows from the FWD D1 and D2 to the positive bus, as shown in Figure 2c.

State 4: Negative level and output current less than zero

IGCT T3 and T4 are ON, and T5 is also ON. The current flows from IGCT T3 and T4 to the negative bus, as shown in Figure 2d.

State 5: Zero-level and output current greater than zero

When the current of the ANPC converter is greater than zero in the zero-level state, there are two current flow paths at the same time. The first, current is output from the neutral point of the capacitor through the FWD D5 and the IGCT T2 and is in the zero-level OU1 or OU2 state, as shown in Figure 3a; The second, current is output from the neutral point of the capacitor through the IGCT T6 and the diode D3, and is in the zero-level OL1 or OL2 state, as shown in Figure 3b.

State 6: Zero-level and output current less than zero

When the current of the ANPC converter is less than zero in the zero-voltage state, there are two current flow paths at the same time. The first type of current is output from the AC side through the FWD D2 and the IGCT T5 and is in the zero-level OU1 or OU2 state, as shown in Figure 3c; the second, current is output from the AC side through the IGCT T3 and the diode D6 in the zero-level OL1 or OL2 state, as shown in Figure 3d.

For the load current, there are two paths in the ANPC converter when it flows out at the zero state, and there are two paths when it flows in. Therefore, during operation, there are four possible combinations for the flow of load current in and out of the converter. The power losses of the devices vary for each combination. By appropriately distributing the operating time of these combinations, it is possible to achieve loss balancing control of the power devices.

3. ANPC Three-Level Inverter PWM Strategy

3.1. Conventional Modulation Strategy

The introduction of fully controlled power switches T5 and T6 in the ANPC three-level topology enables two bidirectional current paths at zero level states. The two zero-level current paths alternate, allowing for inner switches T2 and T3 to operate in complementary mode instead of being turned on simultaneously. Thus, three-level ANPC can be regarded as a combination of three half-bridge circuits: T1/T5, T2/T3, and T4/T6. Among them, T1 and T6 share the same switching pattern, as do T4 and T5. This ensures that the half-bridge formed by T2/T3 always withstands half of the DC bus voltage.

Conventional PWM schemes for ANPC three-level converters can be categorized into three types: carrier phase-shifting modulation, inner switch frequency modulation, and outer switch fundamental frequency modulation.

In the carrier phase-shift modulation strategy, the three half-bridge circuits operate at equal switching frequencies. The phase difference between the two carriers is 180 degrees, corresponding to the switching of T1 and T2. This separation of drive signals enables alternate operation, reducing switching losses. However, this strategy suffers from relatively poor line voltage harmonic performance. The schematic diagram of the carrier phase-shift modulation strategy is shown in Figure 4a.

To enhance neutral-point balancing and reduce internal switching losses, one PWM method operates the internal switches at the fundamental frequency, while T1, T4, T5, and T6 operate at the carrier frequency. Figure 4b shows the schematic diagram of this modulation strategy. With internal switches modulated at the fundamental frequency, T1 and T5 experience significantly higher switching losses than T2. However, this suppresses the imbalance between internal and external switch losses. Additionally, when the output is at zero voltage, T5 and T6 conduct simultaneously, with each internal switch experiencing half of the load current. This reduces internal switch losses, achieving a balance in power device losses. However, this strategy results in relatively high switching losses for the external switches.

In contrast, another approach operates the external switches at the fundamental frequency, while T2 and T3 operate at the carrier frequency. The schematic diagram of this modulation strategy is shown in Figure 4c. However, this strategy exacerbates the switching losses of the internal switches and fails to address the uneven heating issue between internal and external switches in the three-level ANPC. This PWM strategy is mainly suited for hybrid topologies using SiC and Si devices [27,28].

3.2. Novel Hybrid Fundamental Frequency Modulation

A new PWM optimization strategy, hybrid fundamental frequency modulation, combines the advantages of inner and outer switch fundamental frequency modulation to optimize switching frequency and balance switching losses. The switching states of the converter under this modulation strategy are shown in the

Table 2. Hybrid fundamental frequency modulation switching states.

States	${\mathit{T}}_1$	${\mathit{T}}_2$	${\mathit{T}}_3$	${\mathit{T}}_4$	${\mathit{T}}_5$	${\mathit{T}}_6$	Output
P	1	1	0	0	0	1	+$U_{dc}/2$
OU2	0	1	0	1	1	0	0
OL2	1	0	1	0	0	1	0
N	0	0	1	1	1	0	${-U}_{dc}/2$

below.

First cycle: When the reference modulation wave is greater than 0, voltage states P and OU2 are used, keeping T2 conducting and T3 off. When the reference modulation wave is less than 0, voltage states N and OL2 are used, keeping T2 off and T3 conducting. Thus, during the first operating cycle, T2 and T3 operate at the fundamental frequency, while T1, T4, T5, and T6 operate at the carrier frequency.

Second cycle: When the reference modulation wave is greater than 0, voltage states P and OL2 are used, keeping T1 and T6 conducting and T4 and T5 off. When the reference modulation wave is less than 0, voltage states N and OU2 are used, keeping T1 and T6 off and T4 and T5 conducting. Thus, during the second operating cycle, T1, T4, T5, and T6 operate at the fundamental frequency, while T2 and T3 operate at the carrier frequency.

In the third and subsequent cycles, the two working states alternate. This strategy equalizes the switching frequencies of internal switches T2 and T3, external switches T1 and T4, and clamping switches T5 and T6, achieving balanced switching losses. This approach resolves the loss imbalance issue observed in the ANPC converter under different modulation strategies. A schematic diagram of the hybrid fundamental frequency modulation strategy is shown in Figure 5.

The periodic alternation logic in the proposed strategy follows a fixed, predefined pattern to achieve symmetric loss balancing. By combining inner and outer switch fundamental frequency modulation strategies, the ANPC three-level converter’s switch loss balance can be flexibly optimized. Hybrid fundamental frequency modulation offers multiple application options by tailoring modulation strategies for internal and external switches, effectively addressing uneven heating issues.

4. Loss Calculation Model for ANPC Three-Level Converter

The key parameters at typical junction temperatures of 25 °C and 125 °C can be obtained from the datasheet of the switching devices. Based on these parameters, a loss model for the power devices can be established.

4.1. Loss Calculation for IGBTs

The loss of IGCT consists of conduction loss and switching loss.

$$P_T=P_{con,T}+P_T$$

(1)

Power devices experience conduction losses due to initial saturation voltage drop and conduction resistance. The initial saturation voltage drop and conduction resistance vary approximately linearly with temperature. Therefore, the initial saturation voltage drop, conduction resistance, and conduction losses of power devices can be expressed as follows:

$$v_{0,T}=v_{0,T\_25°\mathrm{C}}+K_{v0,T}(T_{vj,T}-25 °\mathrm{C})$$

(2)

$$r_T=r_{T\_25°\mathrm{C}}+K_{r,T}(T_{vj,T}-25 °\mathrm{C})$$

(3)

$$P_{con,T}=v_{0,T}I+r_T{I}^2$$

(4)

where $v_{0,T\_25°\mathrm{C}}$ and $r_{T\_25°\mathrm{C}}$ denote the initial saturation voltage drop and conduction resistance of the IGCT at a junction temperature of 25 °C, respectively. $K_{v0,T}$ and $K_{r,T}$ are temperature correction coefficients for the IGCT’s initial saturation voltage drop and conduction resistance, respectively. $T_{vj,T}$ denotes the IGCT junction temperature, and $I$ is the instantaneous current flowing through it.

IGCTs incur switching losses during turn-on and turn-off processes. Switching energy losses can be indirectly calculated under test conditions by multiplying voltage and current and integrating over time. The IGCT datasheet typically provides a curve showing the variation of switching energy losses with load current under test voltage conditions at a junction temperature of 125 °C. Energy losses under varying voltages and junction temperatures can be corrected using power functions of the ratios between actual and test voltages and junction temperatures. Therefore, the switching energy loss of an IGCT can be expressed as

$$E_{sw,T}(I)=E_{on,T}(I)+E_{off,T}(I)=(A_{sw,T}{I}^2+B_{sw,T}I+C_{sw,T}){({\displaystyle \frac{U_{ce}}{U_{base}}})}^{D_{sw,T}}{({\displaystyle \frac{T_{vj,T}}{T_{base}}})}^{T_s}$$

(5)

where $A_{sw,T}$, $B_{sw,T}$, and $C_{sw,T}$ are quadratic fitting coefficients representing the variation of switching energy loss with current under test conditions. $D_{sw,T}$ and $K_{sw,T}$ are correction factors for the test voltage $U_{base}$ and junction temperature $T_{base}$ (typically 125 °C), respectively. $U_{ce}$ is the actual voltage across the device.

The IGCT average switching loss per cycle is

$$P_{sw,T}=f_{sw}{E}_{sw,T}(I)$$

(6)

where $f_{sw}$ is the switching frequency.

4.2. Loss Calculation for Diodes

Similar to the IGCT, the losses of the diode consist of conduction loss and reverse recovery loss:

$$P_D=P_{con,D}+P_{sw,D}$$

(7)

The initial saturation voltage drop, on-resistance, and conduction loss of the diode can be expressed, respectively, as

$$v_{0,D}=v_{0,D\_25°\mathrm{C}}+K_{v0,D}(T_{vj,D}-25 °\mathrm{C})$$

(8)

$$r_D=r_{D\_25°\mathrm{C}}+K_{r,D}(T_{vj,D}-25 °\mathrm{C})$$

(9)

$$P_{con,D}=v_{0,D}I+r_D{I}^2$$

(10)

where $v_{0,D\_25°\mathrm{C}}$ and $r_{D\_25°\mathrm{C}}$ denote the diode’s initial saturation voltage drop and conduction resistance at a junction temperature of 25 °C. $K_{v0,D}$ and $K_{r,D}$ are the temperature correction coefficients for the diode’s initial saturation voltage drop and conduction resistance. $T_{vj,D}$ denotes the diode’s junction temperature, and III is the instantaneous current through it.

Fast recovery diodes have negligible turn-on losses, which are typically ignored. However, they incur reverse recovery losses during turn-off. Similar to the IGCT, the diode’s switching energy losses are expressed using parameters from its datasheet as follows:

$$E_{rec,D}(I)=(A_{rec,D}{I}^2+B_{rec,D}I+C_{rec,D}){({\displaystyle \frac{U_{ce}}{U_{base}}})}^{D_{rec,D}}{({\displaystyle \frac{T_{vj,D}}{T_{base}}})}^{K_{rec,D}}$$

(11)

where $A_{rec,D}$, $B_{rec,D}$, and $C_{rec,D}$ are quadratic fitting coefficients representing switching energy loss variation with current under test conditions. $D_{rec,D}$ is the correction factor for the test voltage $U_{base}$; $K_{rec,D}$ is the correction factor for the test junction temperature $T_{base}$.

The average switching loss of the diode per switching cycle is

$$P_{sw,D}=f_{sw}{E}_{rec,D}(I)$$

(12)

5. Loss Analysis of Modulation Strategies

5.1. Switching Loss Distribution for Different Modulation Strategies

The waveforms of voltage and current during a modulation cycle are shown in Figure 6, where φ represents the power factor angle. A modulation cycle is divided into four regions based on the zero-crossing points of the current and voltage. With the current as the reference sinusoidal waveform, the voltage waveform exhibits a power factor angle.

Due to the symmetry of the ANPC converter’s upper and lower bridge arms, the analysis focuses on the power devices of the upper bridge arm. Let $\theta =\omega t+\phi$.

Table 3. Duty cycle of ANPC three-level converter switching devices.

Angle	Modulation Method	${\mathit{T}}_1$	${\mathit{T}}_2$	${\mathit{T}}_3$	${\mathit{T}}_4$	${\mathit{T}}_5$	${\mathit{T}}_6$
[0,$\pi -\phi$]	Inner switch fundamental frequency	$msin \theta$	1	0	0	0	$1-msin \theta$
	Outer switch fundamental frequency	$msin \theta$	$msin \theta$	0	0	0	0
	Hybrid fundamental frequency	$msin \theta$	${\displaystyle \frac{1+msin \theta }{2}}$	0	0	0	${\displaystyle \frac{1-msin \theta }{2}}$
[$\pi -\phi$,$\pi$]	Inner switch fundamental frequency	0	0	0	0	0	$0$
	Outer switch fundamental frequency	0	${\displaystyle \frac{1+msin \theta }{2}}$	0	0	0	${\displaystyle \frac{1+msin \theta }{2}}$
	Hybrid fundamental frequency	0	${\displaystyle \frac{1+msin \theta }{2}}$	0	0	0	${\displaystyle \frac{1+msin \theta }{2}}$
[$\pi$,2$\pi -\phi$]	Inner switch fundamental frequency	0	0	0	0	0	$0$
	Outer switch fundamental frequency	0	0	$1+msin \theta$	0	$1+msin \theta$	0
	Hybrid fundamental frequency	0	0	${\displaystyle \frac{1+msin \theta }{2}}$	0	${\displaystyle \frac{1+msin \theta }{2}}$	0
[$2\pi -\phi$,2$\pi$]	Inner switch fundamental frequency	0	0	$1-msin \theta$	$msin \theta$	1	$0$
	Outer switch fundamental frequency	0	0	0	$msin \theta$	$msin \theta$	0
	Hybrid fundamental frequency	0	0	${\displaystyle \frac{1-msin \theta }{2}}$	$msin \theta$	${\displaystyle \frac{1+msin \theta }{2}}$	0

lists the duty cycles of each switching device in the ANPC three-level converter under different conduction angles.

5.2. Comparison of Losses in Different Modulation Strategies

The system loss calculation formula is applied to a practical 10 MW-level ANPC three-level converter for verification. The typical parameters of the IGCT and the antiparallel diode selected for the calculation are shown in

Table 4. Typical parameters of the IGCT.

Typical Parameter	Parameter Value
Peak off-state voltage	4500 V
Continuous DC current	3000 A
Threshold voltage	1.22 V
Slope resistor	0.28 mΩ
Single turn-on energy	1.8 J
Single turn-off energy	17 J

and

Table 5. Typical parameters of the antiparallel diode.

Typical Parameter	Parameter Value
Peak off-state voltage	4500 V
Continuous DC current	3000 A
Threshold voltage	1.22 V
Slope resistor	0.28 mΩ
Single turn-on energy	1.8 J
Single turn-off energy	17 J

.

With an AC rated voltage of 3300 V, a DC rated voltage of 5000 V, and a rated power factor of 0.95, the RMS and peak AC current values are 1842 A and 2605 A, respectively. Each power device is subjected to half of the DC voltage (2500 V). Owing to the symmetry of the bridge arms, the loss calculation formulas for IGCT devices (e.g., T1/T4, T2/T3, T5/T6) are identical. Similarly, the loss calculation formulas for diodes (D1/D4, D2/D3, D5/D6) are identical. As the loss formulas for all six bridge arms are identical, the total loss of the three-phase ANPC is six times the single-phase loss.

With a power factor of 0.95 and a fixed carrier frequency of 750 Hz, the total losses and loss distribution for three modulation strategies—carrier phase-shift, inner switch fundamental frequency, and hybrid fundamental frequency modulation—are compared.

Table 6. Typical parameters of the antiparallel diode (unit: W).

Modulation Strategy	Carrier Phase-Shifting Modulation				Inner Switch Fundamental Frequency Modulation				Hybrid Fundamental Frequency Modulation
loss value	turn-on	turn-off	conduction	total	turn-on	turn-off	conduction	total	turn-on	turn-off	conduction	total
T1	167.3	1580	1271	3018	167.3	1580	1271	3018	83.6	790	1271	2145
D1	0	2.3	3.7	6	0	2.3	3.7	6	0	1.1	3.7	4.8
T2	167.9	1586	1478	3231	0	0	1656	1656	83.9	792.8	1478	2354
D2	0	652.8	265.4	918.4	0	0	210.9	210.9	0	326.4	265.6	591.9
T5	167.3	1580	548.2	2296	0.6	5.6	137	143.2	0.3	2.8	548.2	551.2
D5	0	650.7	255.3	905.9	0	650.6	489.6	1140	0	325.3	255.3	580.6
aggregate value	10,375.3				6174.1				6227.5
total three-phase losses	62,251.8				37,044.6				37,365

presents the calculated device losses for the three modulation strategies under a power factor of 0.95 and a carrier frequency of 750 Hz. The total losses for the three modulation strategies are 62,251.8 W, 37,044.6 W, and 37,365 W, respectively. With an equivalent switching frequency twice the carrier frequency, the total loss in carrier phase-shift modulation is significantly higher than in the other two strategies. Quantitative analysis shows that the total loss under hybrid fundamental frequency modulation is reduced by 39.98% compared to the carrier phase shift method. The total losses of inner switch and hybrid fundamental frequency modulation are comparable. However, in inner switch fundamental frequency modulation, T1 has the highest loss at 3018 W. In hybrid fundamental frequency modulation, T2 has the highest loss at 2354 W, lower than 3018 W.

To further analyze the loss distribution under the three modulation strategies, bar charts in Figure 7 compare device types and loss categories.

The chart shows that in the carrier phase-shift modulation strategy, turn-off losses dominate, while in inner switch fundamental frequency and hybrid fundamental frequency modulation strategies, conduction losses are the largest proportion. In the carrier phase-shift modulation strategy, losses in IGCT devices like T1, T2, and T5 are relatively uniform, simplifying heat sink design. However, its total losses are significantly higher than those of the other strategies, making carrier phase-shift modulation less favorable.

As the total losses in inner switch and hybrid fundamental frequency modulation are similar, the focus shifts to individual device loss distribution. For inner switch fundamental frequency modulation, T2 incurs a loss of 1656 W, while T1 incurs 3018 W, significantly higher than T2. In contrast, in hybrid fundamental frequency modulation, T1 and T2 experience losses of 2145 W and 2354 W, showing a more balanced distribution.

Additionally, in inner switch fundamental frequency modulation, most switching losses of T5 and D5 are borne by D5, totaling 1140 W. In hybrid fundamental frequency modulation, T5 and D5 incur losses of 511.2 W and 580.6 W, respectively, showing a more uniform distribution. A statistical analysis framework based on the coefficient of variation (CV) is developed to quantitatively assess the loss-balancing performance of the two modulation strategies. Calculation results show that with inner switch fundamental frequency modulation, the CV of power switch loss distribution is 1.04. In contrast, the proposed hybrid fundamental frequency modulation reduces this value to 0.85. Comparative analysis shows that the proposed strategy enhances loss balancing by 18.27% over the conventional approach.

Therefore, compared to carrier phase-shift modulation, inner switch fundamental frequency modulation reduces inner switches and overall device losses. Hybrid fundamental frequency modulation further balances device losses compared to inner switch fundamental frequency modulation, addressing uneven heating and improving ANPC converter reliability.

5.3. Effect of Power Factor and Carrier Frequency

The rated parameters of the ANPC converter and typical parameters of the IGCT and reverse parallel diode are consistent with the previous section. A further analysis focuses on device losses under hybrid fundamental frequency modulation, specifically examining the effects of power factor and carrier frequency on total losses and loss distribution.

Table 7. Calculated device losses for a half bridge arm module with a constant power factor of 0.95 and switching frequencies from 350 Hz to 950 Hz (unit: W).

Frequency	Loss Value	${\mathit{T}}_1$	${\mathit{D}}_1$	${\mathit{T}}_2$	${\mathit{D}}_2$	${\mathit{T}}_5$	${\mathit{D}}_5$	Aggregate Value	Total Three-Phase Losses
350 Hz	turn-on	39	0	39.2	0	0.1	0	4943.7	29,662.2
	turn-off	368.7	0.5	370	152.3	1.3	151.8
	conduction	1271	3.7	1478	265.5	548.2	255.3
	total	1678	4.2	1887	417.8	549.6	407.1
550 Hz	turn-on	61.3	0	61.6	0	0.2	0	5586.5	33,519
	turn-off	579.3	0.8	581.4	239.4	2	238.6
	conduction	1271	3.7	1478	265.5	548.2	255.3
	total	1912	4.5	2121	504.8	550.4	493.8
750 Hz	turn-on	83.6	0	83.9	0	0.3	0	6227.5	37,365
	turn-off	790	1.1	792.8	326.4	2.8	325.3
	conduction	1271	3.7	1478	265.5	548.2	255.3
	total	2145	4.8	2354	591.9	551.2	580.6
950 Hz	turn-on	106	0	106.3	0	0.4	0	6869.7	41,218.2
	turn-off	1001	1.5	1004	413.5	3.5	412
	conduction	1271	3.7	1478	265.5	548.2	255.3
	total	2378	5.2	2588	679	552.7	667.4

presents calculated device losses for switching frequencies from 350 Hz to 950 Hz at a fixed power factor of 0.95.

Table 8. Calculated device losses for a half bridge arm module with a constant switching frequency of 750 Hz and power factor from0.93 to 0.99 (unit: W).

Power Factor	Loss Value	${\mathit{T}}_1$	${\mathit{D}}_1$	${\mathit{T}}_2$	${\mathit{D}}_2$	${\mathit{T}}_5$	${\mathit{D}}_5$	Aggregate Value	Total Three-Phase Losses
0.93	turn-on	82.1	0	82.6	0	0.5	0	6199.6	37,197.6
	turn-off	775.3	1.9	780	321.1	4.6	319.2
	conduction	1247	6.3	1464	282.8	563.8	268.3
	total	2104	8.2	2327	603.9	568.9	587.6
0.95	turn-on	83.6	0	83.9	0	0.3	0	6227.5	37,365
	turn-off	790	1.1	792.8	326.4	2.8	325.3
	conduction	1271	3.7	1478	265.5	548.2	255.3
	total	2145	4.8	2354	591.9	551.2	580.6
0.97	turn-on	85.2	0	85.4	0	0.1	0	6255.9	37,535.4
	turn-off	805.1	0.5	806.4	332	1.3	331.5
	conduction	1296	1.7	1491	248	529.7	241.9
	total	2186	2.2	2383	580.2	531.1	573.4
0.99	turn-on	86.9	0	86.9	0	0	0	6281.1	37,686.6
	turn-off	820.6	0.1	820.9	338	0.2	337.9
	conduction	1321	0.4	1505	230.8	504.7	288.1
	total	2229	0.4	2412	568.8	504.9	566

presents calculated device losses for power factors from 0.93 to 0.99 at a fixed switching frequency of 750 Hz. The tables examine how switching frequency and power factor affect device losses, efficiency, and performance of the ANPC converter under hybrid fundamental frequency modulation.

For visual comparison, the data from the above table is plotted in a bar chart graph Figure 8 and Figure 9.

Figures and tables show that in hybrid fundamental frequency modulation, current primarily flows through T1, T2, D2, T5, and D5. This occurs because in inner switch mode, load current flows through T2 and D5 at zero voltage level, while in outer switch mode, it flows through D2 and T5. In hybrid fundamental frequency modulation, T2 incurs the highest switching loss of 2588 W. Additionally, at a switching frequency of 750 Hz and a power factor of 0.95, device losses achieve optimal total loss and loss distribution.

In summary, the proposed hybrid fundamental frequency modulation significantly improves loss distribution and reduces total system losses. It achieves up to 39.98% lower losses than carrier phase-shift modulation and enhances loss balance by 18.27% compared to inner switch modulation. Furthermore, sensitivity analyses under varying power factors and switching frequencies confirm that the hybrid fundamental frequency modulation maintains stable and efficient performance across typical operating conditions. These results demonstrate the method’s effectiveness in improving loss balance and enhancing the reliability of high-power ANPC converters, making it a promising design solution.

6. Simulation and Experimental Results

6.1. Simulation Results

A MATLAB/Simulink (R2018a) simulation model of the ANPC three-level inverter was developed to verify the control effectiveness of the hybrid fundamental frequency modulation strategy, with parameters listed in

Table 9. Parameters of ANPC converter simulation model.

Parameter	Parameter Value
Rated capacity	10 MW
Rated DC voltage	5000 V
Rated AC voltage	3300 V
AC side resistance	1.8857 Ω
AC side inductance	0.006 H
AC side capacitor	0.0017 F
Modulated wave frequency	50 Hz
Carrier frequency	1000 Hz
Modulation ratio	1

.

Figure 10a–c show the triggering signals for switches T1, T2, and T5 during the hybrid fundamental frequency modulation. As shown in Figure 10a–c, the inner switch modulation strategy is applied during the first cycle. When the reference modulation wave exceeds 0, T2 remains on, and T3 is off. When the reference modulation wave is below 0, T2 turns off, and T3 turns on. Therefore, in the first cycle, T2 and T3 operate at a fundamental frequency of 50 Hz, while T1, T4, T5, and T6 operate at a carrier frequency of 1000 Hz. In the second cycle, the outer switch modulation strategy is applied, where T1, T4, T5, and T6 operate at 50 Hz, and T2 and T3 at 1000 Hz.

Figure 11 illustrates current waveforms through various devices under the hybrid fundamental frequency modulation strategy. Figure 11a depicts the current waveform of T1 and D1. The figure shows that in both inner and outer switch fundamental frequency modes, when the modulation wave exceeds 0 and the output is positive, current flows continuously through T1.

Figure 11b depicts the current waveform of T2 and D2. It can be seen that in the inner switch fundamental frequency mode, the current flows through T2 when the modulation wave exceeds 0. In the outer switch fundamental frequency mode, current flows through T2 when the modulation wave exceeds 0 and the output is positive, and through D2 when the wave is below 0 and the output is zero.

Figure 11c depicts the current waveform of T5 and D5. In the inner switch fundamental frequency mode, current flows through D5 when the modulation wave exceeds 0 and the output is zero. In the outer switch fundamental frequency mode, current flows through T5 when the modulation wave is below 0 and the output is zero.

6.2. Experimental Results

To validate the proposed modulation strategy under practical conditions, a three-level ANPC power converter test platform was constructed to conduct two-phase power cycling tests, as shown in Figure 12. The setup is designed to evaluate the switching performance and losses of the integrated gate-commutated thyristor (IGCT) under rated power conditions, as well as to verify the device’s reliability under its operating voltage, current, and thermal stress.

The detailed circuit configuration of the experimental test setup for ANPC power module power cycling tests is illustrated in Figure 13. The core of this platform integrated two structurally identical ANPC power modules within the same test cabinet, operating in rectifier mode and inverter mode, respectively, thereby constituting a back-to-back power recirculation test platform. By connecting a load reactor between the AC output terminals of the two modules, a reactive power exchange channel was intentionally established, thus enabling active power to circulate in a closed loop between the modules. This arrangement simulated the electrothermal stresses imposed on the modules under actual high-power operating conditions. The external DC power supply was only required to provide the total power losses generated during system operation (primarily including switching losses, conduction losses of power devices, and line losses), which sufficed to maintain stable operation of the entire test platform. Consequently, this enabled efficient and economical stable and controllable testing of ANPC power modules under conditions approaching rated power levels.

The system’s rated values are provided in Table 9. The testing protocol initiated with no-load verification by disconnecting the load reactor while progressively elevating the DC-link voltage to ±5000 V and modulation index to 0.95. As illustrated in Figure 14, the inverter output voltage demonstrated a stable three-level waveform under no-load conditions, with no observable overshoot, oscillation, voltage spikes, or current discontinuity, confirming proper IGCT operation. Subsequently, the system commenced loaded testing at 10% rated power with load reactor engaged. Through controlled phase-shift angle and modulation depth adjustments, full-rated operation was achieved. Critical waveforms captured at rated conditions (phase-shift: $\mathsf{\Phi }=19°$) in Figure 15 exhibit 2500 V blocking voltage sustained by both IGCTs and freewheeling diodes, along with load reactor current peaking at 2600 A.

Figure 14 characterizes the inverter power unit’s no-load output, confirming baseline switching performance. Figure 15 captures coordinated operation of both units: inverter unit IGCT waveforms demonstrate active power regulation, while rectifier unit diode waveforms validate reverse recovery stress during power recirculation. The load reactor current quantifies internal power transfer magnitude. Governed by the proposed hybrid fundamental frequency modulation, the power switches cyclically alternated between inner switch and outer switch fundamental frequency modes. In both operating modes, the output current waveforms were analyzed using MATLAB’s FFT function. The calculated total harmonic distortion (THD) was below 3% in each case, confirming acceptable waveform quality. The measured output power was calculated using the standard three-phase power formula $P=\sqrt{3}\times U_L\times I_L\times cos \varnothing$, where $U_L=3280 \mathrm{V}$, $I_L=1838.5 \mathrm{A}$, and $cos \varnothing =0.95$. Compared to the rated power of 10 MW, the output power deviation remained within 0.8%. These results collectively demonstrate the operational feasibility of the proposed modulation strategy under high-power conditions.

To further validate the effectiveness of the proposed hybrid fundamental frequency modulation strategy, a systematic comparison between simulation and experimental results was conducted. The simulated switching waveforms (Figure 10) clearly demonstrate the intended cyclic alternation between inner and outer power switches throughout the modulation cycle. This behavior is highly consistent with the experimentally measured IGCT gate signals (Figure 14), particularly the alternating switching activities of devices $I_{s1}$–$I_{s6}$, confirming the correct hardware implementation of the hybrid modulation logic. Regarding the current conduction paths, the simulated waveforms of T1/D1, T2/D2, and T3/D3 (Figure 11) verify the expected conduction patterns under different operating modes, which are further supported by the experimental load current waveform ($I_L$), showing smooth sinusoidal shape and stable phase relationships. As shown in

Table 10. Comparison of Simulation and Experimental Results.

Indicator	Simulation Results	Experimental Results
Output current THD	1.69%	2.97%
Voltage overshoot (V)	0 V	200–300 V
Current ripple at no-load (A)	Negligible	±150 A

, in terms of output voltage waveform quality, the simulation under ideal switching conditions yields clean three-level outputs, while the experimental results exhibit the same three-level structure with minor voltage overshoot (200–300 V) and waveform jitter during switching transients. These discrepancies are primarily attributed to parasitic inductance in the power loop, gate driver delays, and snubber circuit dynamics in the physical system. For current ripple, the simulation demonstrates minimal ripple due to ideal filtering, whereas the experimental results show moderate ripple under no-load or light-load conditions, caused by practical filter limitations and switching noise coupling.

The comparative analysis reveals strong consistency between simulation and experimental platforms in terms of switching sequence, conduction behavior, waveform symmetry, and output performance. Furthermore, by integrating electrothermal models and parasitic parameters into the simulation, the model also provides credible estimations of internal losses that are difficult to measure directly in physical tests. This comparison confirms the practical feasibility of the proposed hybrid fundamental frequency modulation strategy.

7. Conclusions

This paper proposed a novel hybrid fundamental frequency modulation strategy for the three-level active neutral-point clamped (ANPC) inverter, aiming to achieve balanced switching operation among power devices. The proposed strategy addresses the issue of unequal loss distribution and localized thermal stress inherent in conventional modulation methods by alternating the roles of inner and outer switches on a cycle-by-cycle basis. This design enables loss equalization without increasing control complexity. Simulation and experimental results validated the effectiveness of the proposed method. Compared to conventional carrier-based and single-mode fundamental frequency modulation strategies, the hybrid approach reduced total system power loss by up to 39.98% and improved the loss-balancing index by 18.27%, which could enhance converter reliability in high-capacity variable-speed pumped storage systems. Future research may focus on the adaptive modulation strategies that respond to real-time thermal feedback, integration with advanced digital controllers for improved responsiveness, and the extension of the proposed method to other multilevel converter topologies and emerging power semiconductor technologies.