Initial/Last-State-Correlated SAR Control with Optimized Trajectory to Reduce Reverse Overshoot and Smooth Current Switching of Hybrid LDOs

Abstract

Conventional successive approximation recursive (SAR) control hybrid low-dropout regulators (LDOs) have problems such as significant reverse overshoot and discontinuous current switching. Based on trajectory optimization in the phase plane, this paper presented initial/last-state-correlated SAR control to address the aforementioned issues. Firstly, the operating principles of the conventional SAR controller are elucidated, which is depicted by a finite state machine (FSM). Secondly, large reverse overshoot and discontinuous current switching of the SAR control hybrid LDO are analyzed through the phase plane trajectory. Then, the initial/last-state SAR control is proposed by FSM to optimize the trajectory, thereby reducing the reverse overshoot and smoothing current switching. Finally, a series of design challenges of the initial/last-state-correlated SAR control are discussed. Implemented at 1.11 mm × 0.567 mm in a 180 nm bipolar-CMOS-DMOS (BCD) process, under a 0.1 nF output capacitor, the 6-bit hybrid LDO in this paper achieved an output voltage overshoot of 76 mV and a transient time of 18.8 μs at a 152 mA load current change. The experimental result demonstrates the distinct dynamic response advantages of the initial/last-state SAR control.

1. Introduction

Modern MCUs and CPUs employ multiple power supply domains, most of which are regulated by local low-dropout regulators (LDOs) [1,2,3,4]. Conventional analog LDOs (ALDOs) fail to achieve performance enhancements within the context of the scaling CMOS process. Moreover, their performances, such as transient response and load range, deteriorate due to the decreasing supply voltage and intrinsic gain of the transistors [5,6,7,8]. In contrast, digital LDOs (DLDOs) overcome the above drawbacks of ALDOs. However, DLDOs are afflicted with low accuracy and limit cycle oscillation because of the discrete output current [3,5,9,10]. Hence, hybrid LDOs are proposed to address the issues of conventional ALDOs and DLDOs. They typically consist of a large current part and a small current part [2,5,11,12].

For a large current part, mainstream digital controls are categorized into linear search and successive approximation recursive (SAR) search, which are implemented by shift register and successive approximation register, respectively [5,11,13,14,15,16]. Comparing the SAR search control, the DLDO controlled by linear search has issues of large overshoot and long transient response time due to the slow searching speed, as shown in Figure 1a [13,15,17]. However, the DLDO controlled by SAR search provides a large current (I/2) during the first clock cycle for the small load step (I/64), which causes the large reverse overshoot, as shown in Figure 1b. This issue significantly impacts MCUs and CPUs during the majority of their operating time.

To solve the low accuracy and limit cycle oscillation, CLASS-D and ALDO are commonly used in the small current part. CLASS-D adjusts the output voltage by modifying the duty cycle of PWM. However, PWM control causes the output voltage ripple and forfeits the advantage of LDO [1,13,18]. The Schmitt trigger cannot adjust the threshold voltage in different applications, resulting in a fixed output voltage [19]. Therefore, the PWM generator adopts two comparators and RS latch. To eliminate the output voltage ripple, [5,20,21] proposed to use ALDO in the small current part of hybrid LDOs. However, ALDO is more difficult to operate with DLDO than CLASS-D due to the complex current switching logic and stability compensation.

Based on the preceding discussion, two issues exist in hybrid LDOs, namely reverse overshoot and current switching. This paper analyzed these issues in the phase plane, and proposed the initial/last-state-correlated SAR control based on an optimized trajectory. Comparing conventional SAR control, there are two improvements: (1) The proposed SAR control regulates the output current by the initial state before SAR search to reduce reverse overshoot. (2) The proposed SAR adjusts the last state and gate voltage of ALDO before ALDO operation to smooth current switching.

The rest of this paper is arranged as follows: Section 1 introduces operating principles of the conventional SAR controller in hybrid LDO. Section 3 analyzes reverse overshoot and current switching of the SAR controller in the phase plane. Then, initial/last-state-correlated SAR control is discussed based on the SAR controller-optimized trajectory. Section 4 describes the design difficulties of the initial/last-state-correlated SAR control. Section 5 shows the chip, simulation, and experiment results. Section 6 concludes this paper.

2. Operating Principles of a Conventional SAR Controller in Hybrid LDO

To optimize trajectory of a conventional SAR controller, its operating principles, including adjusting process and current switching, are explained in the following contents.

2.1. Adjusting Process of Conventional SAR Controller

The conventional SAR control hybrid LDO is shown in Figure 2, where B [5:0] are driving signals of a digital power transistor, and CLK is the clock signal. Its adjusting process is executed according to three indication signals P, Q [1], and Q [0], which signify the output voltage level and changing direction. The truth table of P, Q [1], and Q [0] is presented in

Table 1. Truth Table of P, Q [1], and Q [0].

Output Voltage Level	Changing Direction	P	Q [1]	Q [0]
VrefL < Vout < VrefH	×	0	×	×
Vout < VrefL	↑	1	1	0
Vout < VrefL	↓	1	1	1
Vout > VrefH	↑	1	0	0
Vout > VrefH	↓	1	0	1

, where VrefH and VrefL are the upper and lower thresholds, respectively.

According to the indication signals P, Q [1], and Q [0], all adjusting cases of the conventional SAR controller are shown in Figure 3. The conventional SAR controller adjusts output current according to Figure 3:

• P = 1: The SAR controller continues to adjust the output current.
• P = 0: This represents one of the conditions for DLDO stopping operation in advance.
• Q [1:0] = 10/01: The SAR controller waits for several clock cycles.
• Q [1:0] = 11: The SAR controller regulates the DLDO to increase the output current.
• Q [1:0] = 00: The SAR controller regulates the DLDO to reduce the output current.

Furthermore, according to the above adjusting mechanism, the finite state machine (FSM) of the conventional SAR controller is presented in Figure 4, where the high level indicates power transistor turning-on. According to the FSM, the conventional SAR controller can be implemented by Verilog HDL.

2.2. Current Switching of Conventional SAR Controller with CLASS-D

In a conventional SAR controller with CLASS-D, to eliminate steady error of the output voltage, the current switching from DLDO to CLASS-D is executed after adjusting B [0] and P = 0. Among the typical control methods of CLASS-D, the simplest one is hysteresis control, which merely requires a hysteresis comparator, as shown in Figure 5. Comparing the limit cycle oscillation, the hysteresis control can reduce frequency of PWM, which is beneficial for the stability of the hybrid LDO.

3. Optimized Trajectory of Initial/Last-State Correlated SAR Controller with ALDO

To analyze reverse overshoot and smooth current switching in the SAR controller, the capacitance current I_C and output voltage V_out are used to plot the phase plane. Furthermore, based on the SAR control, the initial/last-state-correlated SAR control is analyzed in the phase plane to reduce the reverse overshoot and smooth current switching.

3.1. Trajectory of the SAR Controller with CLASS-D

For PMOS power transistor in linear region, its drain/source current is given by

$$\begin{array}{l}{i}_{ds}={\mu }_p{C}_{OX}\left({\displaystyle \frac{W}{L}}\right)\left[\left(V_{in}-V_{TH}\right)\left(V_{IN}-V_{out}\right)-{\displaystyle \frac{1}{2}}{\left(V_{IN}-V_{out}\right)}^2\right]\\ ={\mu }_p{C}_{OX}\left({\displaystyle \frac{W}{L}}\right)V_{IN}\left({\displaystyle \frac{1}{2}}{V}_{in}-V_{TH}\right)+{\mu }_p{C}_{OX}\left({\displaystyle \frac{W}{L}}\right)\left(V_{TH}-{\displaystyle \frac{1}{2}}{V}_{out}\right)V_{out}\end{array}$$

(1)

where μ_p is the channel mobility, C_OX is the gate capacitance value per unit area, and W/L is the width length ratio. V_in and V_out are input and output voltages, and V_TH is the threshold voltage.

In the DLDO, the capacitance current is given by

$$I_C=N{i}_{ds}-{\displaystyle \frac{V_{out}}{R_L}},N={\displaystyle \sum _{j}B\left[j\right]2^j}$$

(2)

where R_L is the load resistance value, and N is the number of turned-on power transistors.

Combing Equations (1) and (2), the capacitance current is derived as

$$\begin{array}{l}{I}_C=N{I}_0+\left[N{\mu }_p{C}_{OX}\left({\displaystyle \frac{W}{L}}\right)\left(V_{TH}-{\displaystyle \frac{1}{2}}{V}_{out}\right)-{\displaystyle \frac{1}{R_L}}\right]V_{out}\\ I_0={\mu }_p{C}_{OX}\left({\displaystyle \frac{W}{L}}\right)V_{in}\left({\displaystyle \frac{1}{2}}{V}_{in}-V_{TH}\right)\end{array}$$

(3)

where I₀ is equivalent current source of power transistor.

In circuit design, the load resistance value satisfies the following relationship:

$$R_L<<{\displaystyle \frac{1}{N{\mu }_p{C}_{OX}\left(\frac{W}{L}\right)\left(V_{TH}-\frac{1}{2}{V}_{out}\right)}}$$

(4)

Based on Equations (3) and (4), the capacitance current is approximately expressed as

$$I_C=N{I}_0-{\displaystyle \frac{1}{R_L}}{V}_{out}$$

(5)

To calculate the variations in output voltage and capacitance current in one digital clock cycle, combining Equation (5) and I_C = CdV_out/dt, the capacitance current and voltage are solved as

$${\displaystyle \frac{V_{out}\left(n+1\right)-N{I}_0{R}_L}{V_{out}\left(n\right)-N{I}_0{R}_L}}=-{\displaystyle \frac{i_C\left(n+1\right)}{i_C\left(n\right)}}=e^{-{\displaystyle \frac{T_{CLK}}{R_{L}C}}}$$

(6)

where V_out(n) and I_C(n) are finial values of the output voltage and capacitance current at the nth clock cycle, and V_out(n + 1) and I_C(n + 1) are finial values of the output voltage and capacitance current at the (n + 1)th clock cycle. T_CLK is the clock period.

An example is presented to illustrate the phase plane analysis. The parameters of this example are shown in

Table 2. Parameters of the example.

VIN	Vref	I0	fCLK	CL	VrefH	VrefL
1.8 V	1 V	5 mA	50 MHz	100 nF	1.01 V	0.99 V

. A total of 63 (6-bit) power transistors are utilized for the analysis, where N = 0, 1, 2, …, 63. According to Equation (5), trajectories of capacitance current and output voltage at different N are plotted in Figure 6.

When the load resistance value changes from R_L1 = 100 Ω to R_L2 = 3.5 Ω, trajectory of the capacitance current and output voltage satisfies l₂ instead of l₁ (O→A₁), as shown in Figure 6. Then, after one clock cycle, the circuit state moves from A₁ to A₂ (A₁→A₂), which satisfies Equation (6). Finally, by regulating the output current, the trajectory returns to l₃ and l₄, resulting in the output voltage near the reference voltage (A₂→O).

According to the operating principles of the SAR controller, when the load resistance value changes from R_L1 = 100 Ω to R_L2 = 3.5 Ω, the number of turn-on power transistors N is adjusted as follows: 2→63→31→47→55→59→57→58→57→58→57→58…, as shown in Figure 7. From Figure 7, hybrid LDO with the SAR controller exits the output voltage ripple.

To analyze the reverse overshoot, when the load resistance value changes from R_L1 = 100 Ω to R_L3 = 35 Ω, the number of turn-on power transistors N is adjusted as follows: 2→63→31→15→7→3→5→6→5→6→5→6…, as shown in Figure 8. From Figure 8, reverse overshoot of the SAR control hybrid LDO causes the long transient response at small load step.

3.2. Optimized Trajectory of the Initial/Last-State-Correlated SAR with ALDO

To reduce the reverse overshoot, eliminate the limit cycle oscillation, and ensure the smoothing current switching, the initial state and last state are introduced into the SAR control, and ALDO is used instead of CLASS-D in the small current part. The initial/last state-correlated SAR control hybrid LDO is presented in Figure 9, where C_M is the compensating capacitor, R_M1, R_M2, …, R_MK are compensating resistors, and A₁ and A₂ are the gate voltage adjusting signals of ALDO power transistor.

Staring position of the proposed SAR control is determined by the initial state before the load step and indication signals Q [1:0], as shown in

Table 3. Staring position setting logic.

Initial State	Q	Starting Position
000000–011111	11	100000 (>last state)
100000–111111	11	111111 (>last state)
000000–011111	00	000000 (<last state)
100000–111111	00	011111 (<last state)

. At the starting position, the output current is regulated to suppress the overshoot at large load step and reduce the reverse overshoot at small load step.

Ending position of the digital adjustment and the gate voltage of ALDO are determined by the last state after the digital adjustment and indication signals Q [1:0], as shown in

Table 4. Position setting logic.

Q	Ending Position	Gate Volatge
11	Last state	0
00	Last state-6′b000001	VDD

. At the ending position, the output current is regulated to smooth the current switching, which ensures continuity of the output voltage. Based on Table 3 and Table 4, FSM of the initial/last-state-correlated SAR control is shown in Figure 10, which can be implemented by ASIC.

To plot trajectory of the initial/last-state-correlated SAR with ALDO, it is necessary to analyze voltage and current at each node of ALDO quantitatively, as shown in Figure 11.

For the gate node and output node, ignoring ditch length modulation effect, the following equations are satisfied according to KCL:

$$\left\{\begin{array}{l}{I}_C=C_L{\displaystyle \frac{d{V}_{out}}{dt}}\\ {\displaystyle \frac{V_g}{R_g}}+C_M{\displaystyle \frac{d\left(V_g-V_M\right)}{dt}}=g_m\left(V_{out}-V_{ref}\right)\\ C_M{\displaystyle \frac{d\left(V_g-V_M\right)}{dt}}={\displaystyle \frac{V_M-V_{out}}{R_M}}\\ {\displaystyle \frac{V_M-V_{out}}{R_M}}+I_A+I_D=I_C+{\displaystyle \frac{V_{out}}{R_L}}\end{array}\right.$$

(7)

where C_M and R_M are the miller compensating capacitor and resistor, C_L and R_L are the output capacitor and load resistor, and R_g is the gate resistor. V_g, V_M, and V_out are the gate voltage, the miller compensating network voltage, and the output voltage, while I_C is current of the output capacitor.

Furthermore, to plot the trajectory of the ALDO, the differential Equation (7) is discretized, as shown in

Table 5. Calculating steps of V_out and I_C at each clock cycle.

Differential Equation	Discrete Form	Calculated Quantity
$I_C=C_L{\displaystyle \frac{d{V}_{out}}{dt}}$	$I_C\left(n\right)=C_L{\displaystyle \frac{V_{out}\left(n+1\right)-V_{out}\left(n\right)}{\Delta T}}$	$V_{out}\left(n+1\right)$
${\displaystyle \frac{V_g}{R_g}}+C_M{\displaystyle \frac{d\left(V_g-V_M\right)}{dt}}=g_m\left(V_{out}-V_{ref}\right)$	${\displaystyle \frac{V_g\left(n\right)}{R_g}}+C_M{\displaystyle \frac{\left[V_g\left(n+1\right)-V_M\left(n+1\right)\right]-\left[V_g\left(n\right)-V_M\left(n\right)\right]}{\Delta T}}=g_m\left[V_{out}\left(n+1\right)-V_{ref}\right]$	$V_g\left(n+1\right)-V_M\left(n+1\right)$
$C_M{\displaystyle \frac{d\left(V_g-V_M\right)}{dt}}={\displaystyle \frac{V_M-V_{out}}{R_M}}$	$C_M{\displaystyle \frac{\left[V_g\left(n+1\right)-V_M\left(n+1\right)\right]-\left[V_g\left(n\right)-V_M\left(n\right)\right]}{\Delta T}}={\displaystyle \frac{V_M\left(n+1\right)-V_{out}\left(n+1\right)}{R_M}}$	$V_M\left(n+1\right)$$,V_g\left(n+1\right)$
${\displaystyle \frac{V_M-V_{out}}{R_M}}+I_A+I_D=I_C+{\displaystyle \frac{V_{out}}{R_L}}$	${\displaystyle \frac{V_M\left(n+1\right)-V_{out}\left(n+1\right)}{R_M}}+I_A\left(n+1\right)+I_D=I_C\left(n+1\right)+{\displaystyle \frac{V_{out}\left(n+1\right)}{R_L}}$	$I_C\left(n+1\right)$

. In this paper, R_g = 10 MΩ, g_m = 200 μS, C_M = 4.4 pF. The current of M_A is given by

$$\begin{array}{l}{V}_g\left(n+1\right)>0.3:I_A\left(n+1\right)=2.857{\left[{\displaystyle \frac{1.1-V_g\left(n+1\right)}{0.8}}\right]}^2\mathrm{mA}\\ V_g\left(n+1\right)=0.3:I_A\left(n+1\right)=5\times {\displaystyle \frac{0.4}{0.7}}\approx 2.857\mathrm{mA}\\ V_g\left(n+1\right)<0.3:I_A\left(n+1\right)=5\times {\displaystyle \frac{0.7-V_g\left(n+1\right)}{0.7}}\mathrm{mA}\end{array}$$

(8)

According to Figure 11 and Equation (8), the adjusting process of the initial/last-state-correlated SAR with ALDO at R_M = 100 KΩ is shown in Figure 12, when the load resistance value changes from R_L1 = 100 Ω to R_L2 = 3.5 Ω. The number of turn-on power transistors N is adjusted as follows: 2→32→63→47→55→59→57→58→57. From Figure 12, the initial/last-state-correlated SAR control hybrid LDO with ALDO eliminates the output voltage ripple.

To analyze the reverse overshoot, the adjusting process at R_M = 100 KΩ is shown in Figure 13a when the load resistance value changes from R_L1 = 100 Ω to R_L3 = 35 Ω. N is adjusted as follows: 2→32→0→16→8→4→6→5.

To enhance the dynamic response and suppress oscillation of the output voltage during the operation of ALDO, R_M changes from 100 KΩ to 1 MΩ, and the corresponding adjusting process is shown in Figure 13b. The value of the compensating resistor R_M, which is crucial for achieving a fast dynamic response, varies with different loads. Therefore, R_M is specifically designed based on the driving signals of DLDO, which can approximately reflect the load range. A detailed discussion to solve this issue is presented in Section 4, Part C.

According to Figure 7, Figure 8, Figure 12 and Figure 13, overshoots and response times of conventional SAR and proposed SAR controls are shown in

Table 6. Overshoots and response times of conventional SAR and proposed SAR controls.

Control Methods	Conventional SAR		Proposed SAR
Load step (Ω)	100→3.5	100→35	100→3.5	100→35
Overshoot/Reverse Overshoot (mV)	54	88	75	23
Response time (Tclk)	27	35	24	16

. The proposed initial/last-state-correlated SAR control is capable of effectively reducing the reverse overshoot and response time at the small load step. Overshoots and response times of the proposed SAR control and conventional SAR control at the large load step are closed.

4. Design Difficulties of Optimized Trajectory Implementation in Hybrid LDO

To implement the initial/last-state-correlated SAR control hybrid LDO, there are some design difficulties according to Section 3 and Section 4:

• The waiting cycle number and threshold width need to be precisely calculated to attain the specific stable state.
• The current switching logic needs to be designed to smooth the output voltage response.
• The compensation resistance RM needs to be accurately derived under different load conditions to achieve adaptive miller compensation.

4.1. Waiting Cycle Number and Threshold Width

For DLDO, the output voltage exists a series of stable states, as given by

$$V_N=N{I}_0{R}_L$$

(9)

By the proposed SAR control adjustment, the output voltage is expected to attain the specific stable state, which is closest to, but not exceeding, the reference voltage, namely that N_specific is the truncation of V_ref/(I₀R_L). When the indication signals satisfy Q = 2′b01/10, the controller waits several cycles to judge whether the output voltage achieves the specific stable state. The judgment criterion is the relationship between the output voltage and threshold voltages. Therefore, the suitable waiting cycle number and threshold width is important to finish the judgment as fast as possible.

During the waiting cycles, tracks of V_out at different stable states are shown in Figure 14. In Figure 14, V₄ is the specific stable state, and V₁, V₂, V₃, V₅, and V₆ are other stable states. Track I, II, III, and IV are converged to V₂, V₃, V₄, and V₅, respectively.

• Threshold width: After the proposed SAR control, the output voltage can achieve into the hysteresis region. Considering output current capacity of the ALDO, the hysteresis region can only contain a specific stable state. However, with the ending position setting logic, the stable state N = Nspecific + 1 can be adjusted to the specific stable state. Therefore, the threshold region can contain less than three stable states, and the threshold width satisfies Vw < 2I0RL, MIM.
• Waiting cycle number: In Figure 14, the output voltage of Track II and Track III can converge to V3 and V4, with ALDO capable of adjusting the output voltage to the reference voltage. For all other tracks, Track I and Track IV are closest to Track II and Track III. Therefore, Track I and Track IV are most difficult to distinguish from Track II and Track III. For Track I and Track II, the output voltage of Track II needs to achieve V2 so as to distinguish Track I and Track II.

At the jth- (j = 0, 1, 2, 3, 4, 5) bit current adjustment, the output voltage of track II is solved as

$$V_{out}\left(t\right)=\left(V_0-V_3\right)e^{-{\displaystyle \frac{t}{R_L{C}_L}}}+V_3$$

(10)

where V₀ is the initial voltage at the waiting period.

According to Equation (10), the waiting time satisfies

$$V_{out}\left(t_w\right)=\left(V_0-V_3\right)e^{-{\displaystyle \frac{t_w}{R_L{C}_L}}}+V_3=V_2$$

(11)

Taking V₃ = V₂ − I₀R_L and V₃ = V₀ + 2^jI₀R_L into Equation (11), the waiting time is solved as

$$t_w=j\ln \left(2\right)R_L{C}_L$$

(12)

If all bits require the waiting period to distinguish between different tracks, the total of waiting time in the 6-bit hybrid LDO is given by

$$t_{w,\max }=15\ln \left(2\right)R_L{C}_L$$

(13)

4.2. Current Switching Logic

According to Figure 14, there are three cases of stable states contained at the hysteresis region: zero, one, and two stable states. When one or two stable states are at the hysteresis region, after the waiting time t_w, if P = 0, DLDO holds and ALDO works; if P = 1, DLDO continues to adjust based on Q [0]. When zero stable state is at the hysteresis region, DLDO will wait to adjust the last bit, then DLDO stops and ALDO starts. Therefore, if the output voltage is at the hysteresis region after the waiting time t_w, DLDO stops and ALDO starts in advance, which saves the adjusting time of other remnant bits.

When DLDO holds and ALDO works, DLDO and ALDO are adjusted based on the following principles to smooth the current switching: (1) Q = 01: DLDO holds the last state, and the gate voltage of ALDO is set to V_DD; (2) Q = 10: last state of the DLDO subtracts 1, and the gate voltage of ALDO is set to 0. Therefore, the current switching logic of DLDO and ALDO is shown in Figure 15.

4.3. R_M Design in the Adaptive Miller Compensation According to the Load Range

The transistor schematic and small signal model of ALDO are shown in Figure 16a,b, where g_N1 and g_A are transconductances of M_N1 and M_A, r_oA is the small signal resistor of M_A, r_dig is the small signal resistor of power transistors in the DLDO, g_mP5, r_oP5, r_oP4, and r_oB5 are transconductance, small signal resistors of M_P5, M_P4, and M_B5, respectively. Because g_A, r_oA, and r_dig change with the load current, it is necessary to apply adaptive Miller compensation at the different load range. In the hybrid LDO, driving signals of DLDO effectively reflect the load range. Therefore, driving signals can be used to control the resistance value R_M of adaptive Miller compensation.

According to Figure 16b, the loop gain T(s) is derived as

$$\begin{array}{l}T={\displaystyle \frac{v_o}{v_i}}=-g_{N1}{r}_g{g}_{mA}{r}_{eq}\times {\displaystyle \frac{1+s{C}_M\left(R_M-\frac{1}{g_{mA}}\right)}{1+s\left[r_{eq}{C}_L+\left(r_g+R_M\right)C_M+\left(1+g_{mA}{r}_g\right)r_{eq}{C}_M\right]+s^2{r}_{eq}{C}_L\left(r_g+R_M\right)C_M}}\\ {\displaystyle \frac{1}{r_{eq}}}={\displaystyle \frac{1}{r_{oA}}}+{\displaystyle \frac{1}{R_L}}+{\displaystyle \frac{1}{r_{dig}}}\end{array}$$

(14)

Furthermore, DC gain A_v0, zero ω_z, poles ω_p1, ω_p2, and the phase margin PM of T are given by (ω_p1 << ω_p2, R_M <<r_g)

$$\begin{array}{l}{A}_{v0}=g_{N1}{r}_g{g}_{mA}{r}_{eq}\\ {\omega }_z={\displaystyle \frac{1}{\left(R_M-\frac{1}{g_{mA}}\right)C_M}}\\ {\omega }_{p1}={\displaystyle \frac{1}{r_{eq}{C}_L+\left(r_g+R_M\right)C_M+\left(1+g_{mA}{r}_g\right)r_{eq}{C}_M}}\\ {\omega }_{p2}={\displaystyle \frac{1}{\left(r_g+R_M\right)C_M}}+{\displaystyle \frac{1}{r_{eq}{C}_L}}+{\displaystyle \frac{1+g_{mA}{r}_g}{\left(r_g+R_M\right)C_L}}\\ PM={180}^{°}+\arctan \left({\displaystyle \frac{{\omega }_c}{{\omega }_z}}\right)-\arctan \left({\displaystyle \frac{{\omega }_c}{{\omega }_{p1}}}\right)-\arctan \left({\displaystyle \frac{{\omega }_c}{{\omega }_{p2}}}\right)\end{array}$$

(15)

Based on Equation (15), the phase margin of ALDO without the compensation at the all-load current is shown in Figure 17a. From Figure 17a, the minimum values of phase margin occur at I_load = NI₀, and the phase margin at the small load current is below 45°. To increase the phase margin, the capacitance Miller compensation is adopted in the ALDO, with the phase margin shown in Figure 17b. However, the capacitance Miller compensation introduces a left-half-plane zero in the ALDO, resulting in an insignificant increase in the phase margin. Therefore, adaptive Miller compensation is used in the ALDO, with the phase margin shown in Figure 17c. The phase margin at the all-load current with adaptive Miller compensation at over 60°.

When the load current approaches NI0, the output current of ALDO is small. The gain of ALDO has a small effect on the output voltage accuracy. The static error is given by

$$\Delta V_{out}=V_{ref}-V_{out}={\displaystyle \frac{V_{ref}}{1+A_{v0}}}{\displaystyle \frac{I_L-N{I}_0}{I_L}}$$

(16)

According to Equation (16), the static error is shown in Figure 18. The static error of output voltage is less than 0.5 mV at the all-load range.

5. Layout and Experiment

A 6-bit initial/last-state-correlated SAR control hybrid LDO is designed with HHGrace 180 nm BCD process, which occupies a 1.11 × 0.567 mm² die area. The layout of the chip is shown in Figure 19. The layout principally comprises power switches, driving modules, an initial/last-state-correlated SAR controller, and an amplifier with adaptive Miller compensation.

Figure 20 shows the relationship between the output voltage and the load current in the 6-bit initial/last-state-correlated SAR control hybrid LDO. The experiment result shows that static error of the output voltage is less than 12 mV at the 10 MHz and 100 MHz clock.

When testing the dynamic response of the output voltage under rapid load changes, a GaN transistor is employed to periodically switch between two load resistors. In Figure 21 and Figure 22, the load step signal is the gate control signal of the GaN transistor.

Figure 21 shows the output voltage response at the small load step. Figure 21a,b shows the output voltage response at the small load step and the large load current. When the load steps from 193 mA to 110 mA and from 110 mA to 193 mA, the output overshoot voltages are measured as 24 mV and 42 mV, and the response time are 6.3 μs and 10 μs, respectively. Figure 21c,d shows the output voltage response at the small load step and the small load current. When the load steps from 96 mA to 13 mA and from 13 mA to 96 mA, the output overshoot voltages are measured as 28 mV and 64 mV, and the response time are 7 μs and 15.2 μs, respectively.

Figure 22 shows the output voltage response at the large load step. When the load steps from 26 mA to 178 mA and from 178 mA to 26 mA, the output overshoot voltages are measured as 28 mV and 76 mV, and the response time are 18.8 μs and 17 μs, respectively.

Table 7. Performance comparison with reported works.

Literature	This Paper	JSSC, 2018 [13]	JSSC, 2021 [5]	ISSCC, 2020 [9]	ISSCC, 2019 [15]
Process	180 nm BCD	65 nm CMOS	65 nm CMOS	28 nm CMOS	65 nm CMOS
Area (mm2)	0.63	0.023	0.36	0.049	0.048
Output Capacitance (nF)	0.1	0.4	0.25	0.00411	100
vin (V)	1.2	0.5–1	1.2	0.5–1	0.5–1
vout (V)	1	0.3–0.45	0.6–1.15	0.45–0.95	0.4–0.95
Power (mW)	1–200	0.03–0.9	<575	72–45	<0.257
Current Peak Efficiency	99.9%	99.8%	99.98%	99.99%	99.99%
Clock Frequency (MHz)	1–100	1–240	100	120	×
Load Regulation (mV/mA)	<0.06	<5.6	0.03	×	<10
Linear Regulation (mV/V)	1.6	2.3	×	×	×
Overshoot/Current step (mV/mA)	0.51	37.7	0.122	0.26	283.3
Transient time/Current step (μs/mA)	0.113	0.014	0.00049	0.0000033	35.2

shows the performance comparison of initial/last-state-correlated SAR control hybrid LDO and other hybrid LDO. At 0.1 nF output capacitor, the overshoot voltage of initial/last-state-correlated SAR control hybrid LDO achieves 76 mV@152 mA, which is better than the SAR search and linear search.

6. Conclusions

This study proposed an initial/last-state-correlated SAR control strategy for hybrid LDOs, addressing the critical issues of reverse overshoot and discontinuous current switching in conventional SAR-controlled designs. The core innovations include the following: (1) Pre-setting the initial state via a finite state machine (FSM) to regulate the starting output current based on the pre-load state, which avoids the large reverse overshoot caused by excessive first-cycle current injection in a traditional SAR control. (2) Adjusting the last state and ALDO gate voltage to ensure smooth current switching between the DLDO and ALDO parts, eliminating the output voltage ripple of CLASS-D control. Experimental results show that the 6-bit hybrid LDO achieves only 76 mV output overshoot and 18.8 μs transient response under a 152 mA load change with 0.1 nF output capacitance, demonstrating superior dynamic performance. This study also discussed design challenges such as waiting cycles, threshold width, current switching logic, and adaptive Miller compensation, providing a novel framework for high-integration power management ICs. Future work may focus on optimizing compensation networks and extending the strategy to multi-power domain systems.