A Multi-Stage WPDC Optimized Separately for Even and Odd Modes
Round 1
Reviewer 1 Report
Comments and Suggestions for Authors1. there is a need to explain the imptovement value for practical system or environment.
2. for the test bed or test environment, it is necessary to describe or give the diagram for the testing process.
Author Response
Thank you for your valuable feedback！ For the detailed responses, please refer to the attached file.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors- The authors need to discuss the de-embedding procedures used for the effect of the pads on the measurements.
- Please elaborate more on the effects of the process used on the measurement results? If we design with a newer process how the results will be affected.
Author Response
Thank you for your valuable feedback. For the detailed responses, please refer to the attached file. Thank you!
Author Response File: Author Response.pdf
Reviewer 3 Report
Comments and Suggestions for AuthorsThis paper presents a multi-stage lumped element Wilkinson Power Divider/Combiner (WPDC) that utilizes separate impedance matching for even-mode and odd-mode operation.
The paper results are confusing in a sense, that it is unclear what exactly the authors propose.
The first part of the paper analyzes WPD even and odd mode operation comparing an L-type WPD to a PI-type one. According to Fig 5, the power divider is still of PI type even though the authors claim that it is L tye, as the shunt to ground capacitor C1 for each barnch, aka for the even mode, is moved in between the output ports and becomes C2, aka the odd mode. The capacitor C2 is also different in value.
Then the authors analyze the proposed WPD parameters without declaring what they are aiming at (ex. the center frequency, bandwidth, isolation and input matching values). Moreover, for a 3 port component, no isolation between the output ports is provided.
As for a multistage WPD in Figure 5 - is it proposed by the authors or is it a known topology? Does there have to be a shunt resistor at C4, and further on?
Lastly, Figure 6 shows a two stage WPD which has two C4 capacitors in series - why is that? Why can't a single capacitor with a value of C4/2 be used?
Line 116 - In the equations (1) and (2), Z0 represents the characteristic impedance at the port, while ω0 corresponds to the designed center frequency. - please define which port is analyzed (P1 or P2/3 according to Figure 1).
All in all, the paper requires more precise definition of what exactly has been proposed and how it differs from existing solutions.
Author Response
Thank you very much for your valuable suggestions! For the detailed responses, please refer to the attached file. Thank you!
Author Response File: Author Response.pdf
Reviewer 4 Report
Comments and Suggestions for AuthorsPlease, refer to the attached document. Thanks!
Comments for author File: Comments.pdf
Author Response
Thank you very much for your valuable suggestions! For the detailed responses, please refer to the attached file. Thank you!
Author Response File: Author Response.pdf
Round 2
Reviewer 3 Report
Comments and Suggestions for AuthorsThank you for the clarification
Reviewer 4 Report
Comments and Suggestions for AuthorsPlease, refer to the attached document. Thanks!
Comments for author File: Comments.pdf
