Efficiency-Enhanced Hybrid Dickson Converter with Quasi-Complete Soft Charging for Direct Large-Ratio Step-Down Applications

Abstract

This article presents an efficient non-isolated DC-DC hybrid converter for direct large-ratio step-down applications such as data centers. The converter topology employs a three-level-assisted Dickson switched capacitor network and interleaved dual inductors, significantly mitigating voltage swings at the switching nodes. As a result, the conduction duration of rectifying switches is substantially extended. This configuration is suitable for both odd- and even-order converters, achieving self-balancing of the flying capacitor voltages and inductor currents. To address uneven interleaved inductor currents, a duty-cycle-matching-based current distribution method is proposed to ensure equal current sharing and facilitate loss transfer between inductors. Additionally, an intrinsic charge-ratio-based method for capacitance optimization is introduced to achieve quasi-complete soft charging of the flying capacitors. This method eliminates surge currents during reconfiguration of the capacitor network, reduces losses, and enhances the capacitor utilization. Operating at 300 kHz, the prototype achieves high-ratio voltage conversion from 48 V to 0.5–2.0 V, with a maximum output current of 30 A. It attains a peak efficiency of 91.96% and a power density of 944.88 W/in³. Quasi-complete soft charging of the flying capacitors results in an approximate 2.94% improvement in the conversion efficiency.

1. Introduction

With the rapid progression of big data, cloud computing, and artificial intelligence, the power consumption in data centers is experiencing explosive growth. According to the International Energy Agency, the energy consumption of data centers was approximately 460 TWh in 2022 and is projected to reach 800 TWh by 2026 [1]. To reduce significant ohmic losses in the power bus, the 48 V distributed power supply architecture has progressively replaced the traditional 12 V system [2,3]. However, converting the nominal 48 V bus voltage into the ∼1 V core voltage required by CPUs and GPUs presents a major challenge for the design of point-of-load (PoL) converters due to the large voltage conversion ratio. Additionally, with the surge in the demand for computational power, the operating current in digital systems has escalated to tens or even hundreds of amperes. Consequently, for the converters utilized in data centers to support low-voltage rails and high-output currents, maintaining a high conversion efficiency and effectively handling large-ratio voltage conversion are critical performance requirements [4,5].

The traditional Buck converter experiences extremely narrow switch-on times due to a large step-down ratio. In 48 V-to-1 V conversion with a duty cycle of ∼0.02 and a frequency of hundreds of kHz, the power switches’ ON time becomes comparable to their turn-on delay, making precise control of the output voltage difficult. Moreover, the short ON time also results in a large root mean square (RMS) current and increased loss. A two-stage conversion architecture addresses the significantly increased step-down ratio by retaining the original 12 V conversion module and introducing a mature 48 V-to-12 V pre-conversion unit in series [6,7,8]. This configuration allows for the rapid integration of existing modules to meet the application requirements. However, the overall conversion efficiency is limited because of the cascaded power transmission. Additionally, stacked structures, such as the single-stage sigma converter, integrate a fixed-ratio DC-DC converter with a Buck converter, both of which share the same input voltage [9,10,11]. The entire variation in the input voltage is absorbed by the Buck converter, while the output voltage is regulated by adjusting the duty cycle. The sigma converter achieves a peak efficiency of 94% in 48 V-to-1 V conversion [9]. However, this converter requires two separate power conversion circuits operating at different frequencies, which increases the system complexity.

In recent years, hybrid converters combining switched-capacitor (SC) and switched-inductor techniques have garnered significant interest among researchers. These converters employ flying capacitors and magnetic components to achieve continuously adjustable large-ratio voltage conversion. This approach reduces the voltage stress on the switching devices and takes full advantage of the high energy density of multilayer ceramic capacitors (MLCCs) [12]. Additionally, hybrid converters utilize the current suppression effect of magnetic components to prevent large surge currents through the flying capacitors, ensuring soft charging [13]. Compared to traditional switched-inductor converters (such as Buck converters), hybrid converters significantly lower the volt-second product of the magnetic components, thereby considerably reducing the inductance and size [14]. Among these hybrid converters, flying capacitor multilevel (FCML) converters stand out by employing multiple symmetrically distributed flying capacitors. This design effectively reduces the voltage swing at the output node of the capacitor network, achieving a high voltage conversion ratio [15,16,17]. However, FCML converters encounter a charge balancing issue with the flying capacitors, necessitating dedicated control methods, as described in [15], which increases the complexity of system control. Due to its superior V-A rating for the switch, the Dickson topology offers the best switch utilization compared to that of similar topologies [14,18,19], allowing the converter to use low voltage-rated switches with better figures of merit [20]. Consequently, the Dickson topology has attracted widespread attention, and numerous research publications have emerged. Related derivative topologies include the hybrid Dickson (HD) converter [21,22], the dual-inductor hybrid Dickson (DIH) converter [23,24,25,26], and the symmetrical dual-inductor hybrid Dickson (SDIH) converter [27,28,29]. Critical insights into the limitations of the existing topologies can be systematically derived from prior studies [21,22,23,24,25,26,27,28,29]. Specifically, the cited works collectively reveal two fundamental challenges: (i) conduction path inefficiencies and intrinsic balancing constraints in HD converters, and (ii) inadequate duty cycle extension ratios in DIH and SDIH implementations. The N-order HD converter can achieve an N/2-fold duty cycle extension. However, the output current flows through the series freewheeling switches, which results in significant conduction losses. Moreover, not all flying capacitors can be self-balanced, so additional control is needed in practical applications. Compared to an HD converter, the N-order DIH and SDIH converters double the ON time. The SDIH converter, due to its symmetrical structure with two input paths, provides stronger power conversion capabilities but also doubles the number of switches and flying capacitors.

The split-phase control proposed in [21] enables complete soft charging of the flying capacitors, allowing for larger voltage ripples and thus enhancing their utilization. Additionally, complete soft charging of the capacitors helps prevent spike currents during the dynamic reconfiguration of the switched-capacitor network, thereby eliminating the associated losses. This split-phase method has been applied to a DIH converter [24] and an SDIH converter [29]. However, the precise phase-shift timing depends on factors such as the inductance, switching frequency, load current, and output voltage. Therefore, this method necessitates gathering multiple electrical parameters and employing a controller with a high computational performance. Furthermore, in extreme-voltage-conversion-ratio applications (e.g., 60 V to 0.5 V), the theoretical duty cycle of a six-order DIH or SDIH converter is only 0.05, which is clearly not favorable for system control.

To address the aforementioned issues, this article presents a quasi-complete soft charging three-level-assisted hybrid Dickson (QCSC-TLAHD) topology with dual inductors, as illustrated in Figure 1. The primary contributions are as follows:

(1)

The proposed N-order hybrid Dickson converter extends the switch duty cycle by a factor of (2N-1), demonstrating a significant improvement over the N-fold and N/2-fold duty cycle expansions in DIH and HD converters.

(2)

An intrinsic charge-ratio-based capacitance optimization method is proposed to achieve quasi-complete soft charging of the flying capacitors, thereby minimizing the spike currents during capacitor network reconfiguration, optimizing the efficiency, and enhancing the capacitor utilization.

(3)

To address the unequal inductor currents, a duty-cycle-matching-based current equalization method is proposed. By adjusting the PWM duty cycle ratio, the average currents are equalized, ensuring a balanced loss distribution between inductors.

(4)

This topology can be applicable to odd- and even-order converters, overcoming the limitations of DIH converters in [23,24]. Moreover, it ensures self-balancing of the voltages and inductor currents of all flying capacitors.

The rest of this article is structured as follows. Section 2 details the circuit operation and steady-state characteristics of the proposed QCSC-TLAHD converter. Section 3 presents the method for equalizing the inductor currents and offers a comparative analysis of the inductor losses. Section 4 proposes the intrinsic charge-ratio-based capacitance optimization method, extends this method to an N-order converter, and provides guidelines for the capacitor selection. The results of experimental validation of the converter prototype are presented in Section 5. Finally, Section 6 concludes this article.

2. The Proposed Converter

The proposed QCSC-TLAHD topology comprises N + 5 power switches ($S_1-S_{N+5}$), N flying capacitors ($C_{F0}-C_{F,N-1}$), and two output inductors ($L_1$, $L_2$), as depicted in Figure 1. The interconnections of the power devices differ between even- and odd-order QCSC-TLAHD converters. In even-order converters, as shown in Figure 1a, ${\displaystyle \frac{N-2}{2}}$ and ${\displaystyle \frac{N}{2}}$ flying capacitors are connected to $L_1$ and $L_2$, respectively, with $S_{N-1}$ connected to $L_1$, whereas in odd-order converters, each inductor is connected to ${\displaystyle \frac{N-1}{2}}$ flying capacitors, with $S_{N-1}$ connected to $L_2$, as illustrated in Figure 1b. These variations directly result in differing amounts of charge transfer and paths in the capacitor networks of the even- and odd-order converters.

2.1. Principle of Operation

This section explores the operating principle of the proposed topology using a six-order QCSC-TLAHD converter, as shown in Figure 2. The converter consists of 11 power switches ($S_1$–$S_{11}$), 6 flying capacitors ($C_{F0}$–$C_{F5}$), and 2 inductors ($L_1$, $L_2$). During one working period $T_S$, the converter undergoes four operation phases (${\mathrm{\Phi }}_1$–${\mathrm{\Phi }}_4$), with the corresponding equivalent circuits and ideal operational waveforms illustrated in Figure 3. The figures detail the ON-OFF states of the switches, the charging and discharging of the capacitors, and the variations in the current in the inductors. Based on the operating phases, the active components are divided into two groups, with each working with a 180-degree shift: (1) rectifying switches $S_2$, $S_4$, $S_8$, and $S_{10}$ and the freewheeling switch $S_6$ and (2) rectifying switches $S_1$, $S_3$, $S_5$, $S_9$, and $S_{11}$ and the freewheeling switch $S_7$. These switches manage the charging and discharging of the flying capacitors. As shown in Figure 3d, the duty cycles of the drive pulses for switches $S_{1,3,5,9,11}$ and $S_{2,4,8,10}$ are $D_1$ and $D_2$. The drive signals for the freewheeling switches $S_6$ and $S_7$, in turn, are complementary to these two signals, respectively. For simplification, the dead time is ignored. Due to the DC blocking effect of the capacitors, the voltage swings $V_{SW1,2}$ at switch nodes SW1 and SW2 are reduced significantly, effectively addressing the issue of an extremely small duty cycle under a high voltage conversion ratio. Assume the voltages of the flying capacitors $C_{F0}$–$C_{F5}$ are $v_{CF0}$–$v_{CF5}$, with their steady-state DC bias voltages denoted as $V_{CF0}$–$V_{CF5}$. The currents $i_{L1}$ and $i_{L2}$ in inductors $L_1$ and $L_2$ increase and decrease alternately with a 180-degree phase shift. Although the following analysis is based on an even-numbered six-order QCSC-TLAHD converter as an example, the process can be extended to other N-order converters.

During phase ${\mathrm{\Phi }}_1$, depicted in Figure 3a, all even-indexed switches $S_{2,4,6,8,10}$ are activated, establishing three parallel capacitor branches ($(C_{F0}-C_{F1})\Vert (C_{F2}-C_{F3})\Vert (C_{F4}-C_{F5})$), where the operators ‘–’ and ‘‖’ denote series and parallel connections of the capacitors, respectively. Charge flows through these capacitors to the inductor $L_2$, where $C_{F2}$ and $C_{F4}$ discharge. Under the influence of a positive magnetizing voltage, the current $i_{L2}$ experiences an approximately linear increase. Meanwhile, with $S_6$ in the ON state, $L_1$ undergoes a linear decrease in current due to the reverse voltage $-V_O$ applied across it, where $V_O$ represents the output voltage. Under the inductor’s current suppression effect, the currents traversing $C_{F0-5}$ deviate from those observed in traditional SC converters. The charging and discharging process for the flying capacitors is regulated by currents proportional to $i_{L2}$, thus enabling gentle operation. However, during the instantaneous state transition of the power switches, surge currents may occur, stemming from terminal voltage imbalances across the reconstructed parallel capacitor branches. These deviations cause charge redistribution phenomena, resulting in instantaneous hard charging and discharging of the capacitors with additional losses. Further elaboration on this phenomenon will be provided in Section 4.

After ${\mathrm{\Phi }}_1$ lasting for $D_2{T}_S$, the converter switches to ${\mathrm{\Phi }}_2$, as illustrated in Figure 3c, for a duration of $\left(0.5-D_2\right)T_S$. During this phase, all power switches, except for $S_6$ and $S_7$, are deactivated, maintaining the charge on the flying capacitors. With the activation of $S_6$ and $S_7$, the reverse magnetizing voltage $-V_O$ is applied to inductors $L_1$ and $L_2$, initiating the demagnetization process and resulting in linear current decay.

Following half of the operating period comprising ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_2$, the converter enters ${\mathrm{\Phi }}_3$ (lasting for $D_1{T}_S$), as shown in Figure 3b. The odd-numbered switches $S_{1,3,5,9,11}$ are activated, while $S_6$ is deactivated. A new capacitor network is formed: $((C_{F0}\Vert C_{F1})-C_{F2})\Vert (C_{F3}-C_{F4})\Vert C_{F5}$. The charge through these capacitors is injected into the inductor $L_1$. Subsequently, $L_1$ experiences the magnetization process, causing the current $i_{L1}$ to increase approximately linearly. The charge accumulated in $C_{F0,1,3,5}$ during ${\mathrm{\Phi }}_1$ is released. Upon the completion of ${\mathrm{\Phi }}_3$, only $S_6$ and $S_7$ conduct again, and the converter transitions into ${\mathrm{\Phi }}_4$, resembling ${\mathrm{\Phi }}_2$, with a duration of $\left(0.5-D_1\right)T_S$.

2.2. Steady-State Characteristics

Under steady-state conditions, assume a small voltage ripple across the flying capacitors. As shown in Figure 3a,b, according to the Kirchhoff’s voltage law (KVL), the relationship among the average voltages $V_{CF0-5}$ across the flying capacitors and the voltage swings $V_{SW1,2}$ on switching nodes SW1 and SW2 can be described by

$$\left\{\begin{array}{c}{V}_{IN}-V_{CF0}-V_{CF1}=V_{CF2}-V_{CF3}=V_{CF4}-V_{CF5}=V_{SW2}\hfill \\ V_{CF1}-V_{CF2}=V_{CF3}-V_{CF4}=V_{CF5}=V_{SW1}\hfill \\ V_{CF0}=V_{CF1}\hfill \end{array}\right.,$$

(1)

where $V_{IN}$ is the input voltage. The inductors $L_1$ and $L_2$ follow the volt-second balance principle, i.e., $\left(V_{SW1}-V_O\right)D_1{T}_S=V_O\left(1-D_1\right)T_S$, $\left(V_{SW2}-V_O\right)D_2{T}_S=V_O\left(1-D_2\right)T_S$, which can be simplified as

$$\left\{\begin{array}{c}{V}_{SW1}={\displaystyle \frac{V_O}{D_1}}\hfill \\ V_{SW2}={\displaystyle \frac{V_O}{D_2}}\hfill \end{array}\right..$$

(2)

When the converter operates for the same duration in ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, i.e., $D_1=D_2=D$, substituting this condition into (2) yields $V_{SW1}=V_{SW2}$. Using this result in (1) subsequently derives

$$\left\{\begin{array}{c}{V}_{CF0}=V_{CF1}={\displaystyle \frac{5V_{IN}}{11}}\hfill \\ V_{CF2}={\displaystyle \frac{4V_{IN}}{11}}\hfill \\ V_{CF3}={\displaystyle \frac{3V_{IN}}{11}}\hfill \\ V_{CF4}={\displaystyle \frac{2V_{IN}}{11}}\hfill \\ V_{CF5}=V_{SW1}=V_{SW2}={\displaystyle \frac{V_{IN}}{11}}\hfill \end{array}\right..$$

(3)

Substituting the equal $V_{SW1}$ and $V_{SW2}$, along with the duty cycle D, back into (2) results in the output voltage $V_O$ as follows:

$$V_O={\displaystyle \frac{D{V}_{IN}}{11}}.$$

(4)

From (3), the maximum average voltage of the flying capacitors is $V_{CF0}=V_{CF1}={\displaystyle \frac{5V_{IN}}{11}}$, which is much lower than that of DIH converters, where the voltage is close to $V_{IN}$ [24,25]. This low working voltage contributes to miniaturization of the capacitor volume and enables the use of low-equivalent-series-resistance (ESR) MLCCs as flying capacitors in the converter. The voltage swings $V_{SW1}$ and $V_{SW2}$ are compressed to only 1/11 of $V_{IN}$. The reduction in the node voltage facilitates the expansion of the converter duty cycle, with an 11-fold extension in the six-order converter as (4). Furthermore, a reduced voltage swing enables the use of a smaller inductance due to the diminished volt-second product, effectively decreasing the inductor volume and optimizing the power density. Additionally, as the duty cycle increases, the effect of interleaved inductors in reducing ripples in the output current is strengthened, which further reduces the required inductance and size [30].

Assume the charge from $V_{IN}$ within one operating cycle is q, corresponding to the input charge in ${\mathrm{\Phi }}_1$, as shown in Figure 3a. In a steady state, all of the flying capacitors must maintain charge balance between ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$. This means the charge added in one phase must be fully released in the other. Thus, within one period, the transferred charge for $C_{F0,1}$ and $C_{F2-5}$ is q and 2q, respectively. The charge passing through $L_2$ in ${\mathrm{\Phi }}_1$ is 5q, and that through $L_1$ in ${\mathrm{\Phi }}_3$ is 6q. Therefore, the average currents of $L_1$ and $L_2$ can be expressed as

$$I_{L1}={\displaystyle \frac{6q}{D_1{T}_S}},$$

(5)

$$I_{L2}={\displaystyle \frac{5q}{D_2{T}_S}}.$$

(6)

Given that the output current $I_O$ flows entirely through inductors $L_1$ and $L_2$, and assuming $D_1=D_2=D$, the unequal average currents in these two inductors can be represented as follows:

$$I_{L1}={\displaystyle \frac{6}{11}}{I}_O,$$

(7)

$$I_{L2}={\displaystyle \frac{5}{11}}{I}_O.$$

(8)

The derivation process from (1) to (8) is also applicable to an N-order converter, where N can be either odd or even. The average voltages $V_{CF,j}$ across the flying capacitors and the node voltage swings $V_{SW1,2}$ can be derived as

$$V_{CF,j}=\left\{\begin{array}{c}{\displaystyle \frac{N-1}{2N-1}}{V}_{IN},j=0\hfill \\ {\displaystyle \frac{N-j}{2N-1}}{V}_{IN},j\in \left[1,N-1\right]\hfill \end{array}\right.,$$

(9)

$$V_{SW1}=V_{SW2}={\displaystyle \frac{V_{IN}}{2N-1}}.$$

(10)

The voltage conversion ratio M can be expressed as

$$M={\displaystyle \frac{V_O}{V_{IN}}}={\displaystyle \frac{D}{2N-1}}.$$

(11)

According to (11), the proposed converter achieves a duty cycle extension by a factor of $\left(2N-1\right)$. Figure 4 illustrates that the Buck converter exhibits a significantly small duty cycle under large-ratio voltage conversion. For the same ratio M, the duty cycle of the QCSC-TLAHD converter is almost twice that of the DIH converter [24]. This feature allows for precise output voltage control.

When the inductors $L_1$ and $L_2$ in Figure 1 operate in freewheeling mode (in ${\mathrm{\Phi }}_{2,4}$), they experience a reverse magnetizing voltage of $-V_O$. In a steady state, the variation in the inductor current during this duration constitutes the current ripple. By applying the induced voltage formula combined with (11), the current ripples $\Delta I_{L1}$ and $\Delta I_{L2}$ can be determined as

$$\begin{array}{c}\hfill \Delta I_{L1}=\Delta I_{L2}={\displaystyle \frac{V_O\left(1-D\right)T_S}{L}}={\displaystyle \frac{V_O\left(1-\left(2N-1\right)M\right)T_S}{L}},\end{array}$$

(12)

where L is the inductance of $L_1$ and $L_2$.

In phases ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, different capacitor networks are constructed, and $L_1$ and $L_2$ conduct different amounts of charge. When N is even, there are ${\displaystyle \frac{N}{2}}$ parallel capacitor branches in both phases ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, through which the charges of $Nq$ and $\left(N-1\right)q$ are transferred to $L_1$ and $L_2$, respectively. For odd N, in phase ${\mathrm{\Phi }}_1$, $Nq$ charge flows into $L_2$ via ${\displaystyle \frac{N+1}{2}}$ parallel capacitor branches, while in ${\mathrm{\Phi }}_3$, $\left(N-1\right)q$ charge is transferred to $L_1$ through ${\displaystyle \frac{N-1}{2}}$ parallel paths. Therefore, the average currents of inductors $L_1$ and $L_2$ can be described as

$$I_{L,k}{|}_{N=Even}=\left\{\begin{array}{c}{\displaystyle \frac{Nq}{D_1{T}_S}},k=1\hfill \\ {\displaystyle \frac{(N-1)q}{D_{2}T}},k=2\hfill \end{array}\right.,$$

(13)

$$I_{L,k}{|}_{N=Odd}=\left\{\begin{array}{c}{\displaystyle \frac{(N-1)q}{D_1{T}_S}},k=1\hfill \\ {\displaystyle \frac{Nq}{D_2{T}_S}},k=2\hfill \end{array}\right..$$

(14)

When $D_1=D_2=D$, the average currents can be derived as

$$I_{L,k}{|}_{N=Even}=\left\{\begin{array}{c}{\displaystyle \frac{N}{2N-1}}{I}_O,k=1\hfill \\ {\displaystyle \frac{N-1}{2N-1}}{I}_O,k=2\hfill \end{array}\right.,$$

(15)

$$I_{L,k}{|}_{N=Odd}=\left\{\begin{array}{c}{\displaystyle \frac{N-1}{2N-1}}{I}_O,k=1\hfill \\ {\displaystyle \frac{N}{2N-1}}{I}_O,k=2\hfill \end{array}\right..$$

(16)

From (9), (15), and (16), it can be observed that in the steady state, the converter achieves self-balancing of the flying capacitors without additional control circuits or methods, and the average currents of the inductors automatically converge to a specific proportion of the output current.

3. Equalization of the Inductor Current

In the proposed hybrid converter, inductors $L_1$ and $L_2$ collectively carry the output current $I_O$. According to Equations (15) and (16), while the inductor currents can automatically adjust to match the output current, $I_{L1}$ and $I_{L2}$ exhibit inequality. As the order N decreases, the disparity between $I_{L1}$ and $I_{L2}$ becomes more pronounced. For example, in six-, five-, and four-order QCSC-TLAHD converters, $I_{L1}$ surpasses $I_{L2}$ by approximately 20%, −20%, and 33.3%, respectively. This imbalance in the inductor currents poses challenges in the device selection and leads to additional losses. Therefore, it is necessary to ensure that the inductor currents are equalized.

3.1. A Duty-Cycle-Matching-Based Current Equalization Method

The analysis from (15) and (16) indicates that the average current distribution in inductors $L_1$ and $L_2$ varies with the order of the converter. Specifically, in even-order converters, $I_{L1}$ exceeds $I_{L2}$, while the opposite is true for odd-order ones. From (13) and (14), it is observed that adjusting the ratio between $D_1$ and $D_2$ (duty cycle matching) can effectively promote the equality of $I_{L1}$ and $I_{L2}$. For even-order converters, setting ${\displaystyle \frac{D_1}{D_2}}={\displaystyle \frac{N}{N-1}}$, and for odd-order ones, setting ${\displaystyle \frac{D_1}{D_2}}={\displaystyle \frac{N-1}{N}}$, results in $I_{L1}=I_{L2}={\displaystyle \frac{I_O}{2}}$.

Under steady-state conditions, inductors $L_1$ and $L_2$ adhere to the volt-second balance principle, with $V_{SW1}$ and $V_{SW2}$ satisfying (2). During ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, according to KVL, the relationship among the capacitor’s average voltages $V_{CF0}-V_{CF,N-1}$ and the node swings $V_{SW1,2}$ resembles (1). Various parameters of the converter in cases of duty cycle mismatching ($D_1$=$D_2$) and matching are presented in

Table 1. Converter parameters before and after duty cycle matching.

Parameter		D1 = D2		Duty Cycle Matching
		Even-Order	Odd-Order	Even-Order	Odd-Order
$D_1$		$\left(2N-1\right)M$		$2NM$	$2\left(N-1\right)M$
$D_2$				$2\left(N-1\right)M$	$2NM$
$V_{CF,j}$	$j=0$	${\displaystyle \frac{N-1}{2N-1}{V}_{IN}}$		${\displaystyle \left(\frac{1}{4}+\frac{N-2}{4\left(N-1\right)}\right)V_{IN}}$	${\displaystyle \left(\frac{1}{4}+\frac{N-1}{4N}\right)V_{IN}}$
	$j=Odd$	${\displaystyle \frac{N-j}{2N-1}{V}_{IN}}$		${\displaystyle \left(\frac{N-j+1}{4N}+\frac{N-j-1}{4\left(N-1\right)}\right)V_{IN}}$	${\displaystyle \left(\frac{N-j}{4N}+\frac{N-j}{4\left(N-1\right)}\right)V_{IN}}$
	$j=Even$			${\displaystyle \left(\frac{N-j}{4N}+\frac{N-j}{4\left(N-1\right)}\right)V_{IN}}$	${\displaystyle \left(\frac{N-j+1}{4N}+\frac{N-j-1}{4\left(N-1\right)}\right)V_{IN}}$
$V_{SW1}$		${\displaystyle \frac{V_{IN}}{2N-1}}$		${\displaystyle \frac{V_{IN}}{2N}}$	${\displaystyle \frac{V_{IN}}{2\left(N-1\right)}}$
$V_{SW2}$				${\displaystyle \frac{V_{IN}}{2\left(N-1\right)}}$	${\displaystyle \frac{V_{IN}}{2N}}$
$I_{L1}$		${\displaystyle \frac{N}{2N-1}{I}_O}$	${\displaystyle \frac{N-1}{2N-1}{I}_O}$	${\displaystyle \frac{I_O}{2}}$
$I_{L2}$		${\displaystyle \frac{N-1}{2N-1}{I}_O}$	${\displaystyle \frac{N}{2N-1}{I}_O}$
$\Delta I_{L1}$		${\displaystyle \frac{V_O\left(1-\left(2N-1\right)M\right)T_S}{L}}$		${\displaystyle \frac{V_O\left(1-2NM\right)T_S}{L}}$	${\displaystyle \frac{V_O\left(1-\left(2N-2\right)M\right)T_S}{L}}$
$\Delta I_{L2}$				${\displaystyle \frac{V_O\left(1-\left(2N-2\right)M\right)T_S}{L}}$	${\displaystyle \frac{V_O\left(1-2NM\right)T_S}{L}}$

, with the derivation process referenced in Section 2.2. Given that power switches with duty cycles $D_1$ and $D_2$ are directly interconnected within the electrical structure, it is imperative to satisfy the constraint $D_1+D_2<1$. Otherwise, concurrent conduction of the switches may ensue, leading to component damage.

From Table 1, it is evident that to equalize the average inductor current, even-order converters require $D_1=2NM$ and $D_2=2\left(N-1\right)M$, while odd-order configurations necessitate $D_1=2\left(N-1\right)M$ and $D_2=2NM$, with $D_1$ and $D_2$ exhibiting symmetry. In microcontrollers with high-precision PWM outputs, a proportional relationship between $D_1$ and $D_2$ corresponding to the converter order N is readily achievable. Similarly, other parameters of even- and odd-order converters, such as the average voltages $V_{CF,j}$ of the flying capacitors, the node voltage swings $V_{SW1,2}$, and the ripples in the inductor current $\Delta I_{L1,2}$, also demonstrate apparent symmetry once the duty cycles are matched.

Figure 5 depicts simulated waveforms of the inductor currents for the six-order QCSC-TLAHD converter operating at 300 kHz and 48 V-to-1 V with a 30 A load. When $D_1=D_2$, it is evident that $I_{L1}>I_{L2}$. After duty cycle matching, $I_{L1}$ and $I_{L2}$ are approximately equal, demonstrating that matched duty cycles result in an adjusted current distribution in $L_{1,2}$. Additionally, in Figure 5b, the rising slope of $i_{L2}$ is greater than that of $i_{L1}$, confirming that $V_{SW2}>V_{SW1}$ after duty cycle matching, which is consistent with the expressions in Table 1.

3.2. An Analysis of the Inductor Loss

Inductor losses primarily consist of DC loss, AC loss, and core loss. The average inductor currents $I_{L1}$ and $I_{L2}$ can be derived from Table 1. Thus, the inductor DC losses before and after duty cycle matching can, respectively, be expressed as

$$\begin{array}{c}\hfill P_{L,DC,unmatched}=\left({\left({\displaystyle \frac{N}{2N-1}}\right)}^2+{\left({\displaystyle \frac{N-1}{2N-1}}\right)}^2\right)I_O^2{R}_{L,DC},\end{array}$$

(17)

$$\begin{array}{c}\hfill P_{L,DC,matched}={\left({\displaystyle \frac{I_O}{2}}\right)}^2{R}_{L,DC}+{\left({\displaystyle \frac{I_O}{2}}\right)}^2{R}_{L,DC}={\displaystyle \frac{1}{2}}{I}_O^2{R}_{L,DC},\end{array}$$

(18)

where $R_{L,DC}$ is the DC equivalent resistance (DCR) of the inductor, which can easily be obtained from the datasheet.

The AC loss of an inductor is proportional to its current ripple. According to the definition of the RMS value for a periodic waveform (a triangular wave current), the AC RMS current of the inductors can be calculated using calculus as

$$I_{L,AC,rms}={\displaystyle \frac{\Delta I_L}{2\sqrt{3}}},$$

(19)

where $\Delta I_L$ is the inductor current ripple. Combining the ripples $\Delta I_{L1}$ and $\Delta I_{L2}$ from Table 1 with Equation (19), the inductor’s AC losses before and after duty cycle matching can, respectively, be signified by

$$\begin{array}{c}\hfill P_{L,AC,unmatched}={\displaystyle \frac{{\left(1-\left(2N-1\right)M\right)}^2}{6}}{\displaystyle \frac{V_O^2{T}_S^2{R}_{L,AC}}{L^2}},\end{array}$$

(20)

$$\begin{array}{c}\hfill P_{L,AC,matched}={\displaystyle \frac{{\left(1-2\left(N-1\right)M\right)}^2+{\left(1-2NM\right)}^2}{12}}{\displaystyle \frac{V_O^2{T}_S^2{R}_{L,AC}}{L^2}},\end{array}$$

(21)

where $R_{L,AC}$ represents the winding AC resistance, and L denotes the inductance of $L_1$ and $L_2$. Several methods for calculating this resistance are detailed in [31]. However, the necessary parameters are not supplied by the device manufacturers, making it difficult to directly quantify the AC loss.

In the typical 48 V-to-1 V conversion application (M = 1/48), by comparing Equations (17) and (18) as well as (20) and (21), the trends in the inductor’s DC and AC losses before and after duty cycle matching can be determined, as shown in Figure 6. As the order N decreases, the optimization effect of inductor current equalization on the DC loss becomes more apparent. For five- and six-order converters, the reduction in the DC loss can reach 1.22% and 0.82%, respectively. Figure 6 also shows that the increase in the AC loss after duty cycle matching for the six-order converter is only about 0.073%, which can be ignored. Theoretically, the core loss can be calculated using Steinmetz’s formula. However, inductor manufacturers often do not provide parameters for the magnetic core material. Taking IHLP-3232DZ-01 0.47 µH as an example, the inductor losses of a six-order QCSC-TLAHD converter with 48 V to 1 V, $I_O$ = 30 A, and a 300 kHz frequency are calculated using VISHAY’s calculation tool [32]. The results are shown in

Table 2. Inductor losses calculation results.

	D1 = D2		D1,2 Matching
Inductor	$L_1$	$L_2$	$L_1$	$L_2$
Pcore (W)	0.109	0.109	0.117	0.102
PDC (W)	0.757	0.527	0.636	0.636
PAC (W)	0.137	0.137	0.145	0.130
Ptotal (W)	1.003	0.773	0.898	0.868
Temp. rise (℃)	22.7	17.5	20.3	19.7

: the core and AC losses each increase by 1 mW, while the DC loss decreases by 12 mW, leading to a total loss reduction of 10 mW.

Although duty cycle matching makes a limited contribution to overall efficiency improvements, it balances the losses between $L_1$ and $L_2$ through inter-inductor loss transfer, which is beneficial for a unified magnetic component selection. Furthermore, it helps equalize the temperature rise of the interleaved inductors.

4. Quasi-Complete Soft Charging of Flying Capacitors

Figure 3 illustrates the charging and discharging processes of the flying capacitors in the proposed six-order QCSC-TLAHD converter. In phases ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, two distinct capacitor networks are alternately established. During the reconfiguration of capacitor networks, voltage differences among parallel branches cause transient surge currents through low-impedance paths. This leads to short-term hard charging and discharging of the capacitors, which dissipates additional energy in the charge transfer paths, thereby reducing the conversion efficiency. Achieving complete soft charging for all flying capacitors helps eliminate burst currents, thus removing the portion of output impedance known as the slow switch limit (SSL) [33,34]. This not only avoids the need to deliberately increase the capacitance or raise the operating frequency to reduce the equivalent output impedance but also allows for larger voltage ripples across the capacitors, thereby improving their utilization.

4.1. Intrinsic Charge-Ratio-Based Capacitance Optimization

To achieve complete soft charging of the capacitors, an intrinsic charge-ratio-based capacitance optimization method is proposed. The intrinsic charge ratio, determined by the topology and independent of capacitance, refers to the proportion of the charge dynamically transferred across each flying capacitor. This approach necessitates that each flying capacitor transfers charge in accordance with the intrinsic charge ratio during ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, while ensuring uniform variation in the voltage across all capacitor branches. This prevents scenarios in which the capacitors either transfer excessive or insufficient charge. If not, dynamic charge rebalancing must occur during capacitor network reconfiguration, resulting in transient surge currents.

In Figure 3a, during ${\mathrm{\Phi }}_1$, the transferred charges for $C_{F0}-C_{F5}$ are q, q, $-2q$, $2q$, $-2q$, and $2q$, respectively. In Figure 3b, during ${\mathrm{\Phi }}_3$, the charges are $-q$, $-q$, $2q$, $-2q$, $2q$, and $-2q$. Here, the positive and negative signs indicate the accumulation and release of charges in the flying capacitors. Thus, the intrinsic charge ratio for $C_{F0}-C_{F5}$ is (1: 1: 2: 2: 2: 2). During ${\mathrm{\Phi }}_1$, three parallel capacitor branches ($C_{F0}-C_{F1}$, $C_{F2}-C_{F3}$, and $C_{F4}-C_{F5}$) collectively supply charge to $L_2$. As shown in Figure 3a, relative to node SW2, the voltage changes across the branches are ${\displaystyle \frac{q}{C_{F0}}}+{\displaystyle \frac{q}{C_{F1}}}$, $-{\displaystyle \frac{-2q}{C_{F2}}}+{\displaystyle \frac{2q}{C_{F3}}}$, and $-{\displaystyle \frac{-2q}{C_{F4}}}+{\displaystyle \frac{2q}{C_{F5}}}$. If Equation (22) holds, each flying capacitor will transfer charge according to the intrinsic ratio during ${\mathrm{\Phi }}_1$, resulting in identical voltage variations across each branch.

$${\displaystyle \frac{q}{C_{F0}}}+{\displaystyle \frac{q}{C_{F1}}}=-{\displaystyle \frac{-2q}{C_{F2}}}+{\displaystyle \frac{2q}{C_{F3}}}=-{\displaystyle \frac{-2q}{C_{F4}}}+{\displaystyle \frac{2q}{C_{F5}}}$$

(22)

Conversely, if (22) is not met, for instance, when ${\displaystyle \frac{q}{C_{F0}}}+{\displaystyle \frac{q}{C_{F1}}}=-{\displaystyle \frac{-2q}{C_{F2}}}+{\displaystyle \frac{2q}{C_{F3}}}<-{\displaystyle \frac{-2q}{C_{F4}}}+{\displaystyle \frac{2q}{C_{F5}}}$, the charge transferred by the branch ($C_{F4}$–$C_{F5}$) will be less than $2q$ during ${\mathrm{\Phi }}_1$ due to the same voltage variation across the parallel capacitor branches. The untransferred portion of the charge in $C_{F4}$ and $C_{F5}$ will rapidly move in the next operating phase, ${\mathrm{\Phi }}_3$. Rearranging Equation (22) yields

$${\displaystyle \frac{C_{F0}{C}_{F1}}{C_{F0}+C_{F1}}}={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F2}{C}_{F3}}{C_{F2}+C_{F3}}}={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F4}{C}_{F5}}{C_{F4}+C_{F5}}}.$$

(23)

As shown in Figure 3b, during ${\mathrm{\Phi }}_3$, each of the three capacitor branches transfers a charge of $2q$. Similarly, when (24) is met, the charge of all flying capacitors can be transferred in accordance with the ratio, avoiding sharp currents caused by charge redistribution at the start of ${\mathrm{\Phi }}_1$. Thus, all flying capacitors charge and discharge softly.

$${\displaystyle \frac{\left(C_{F0}+C_{F1}\right)C_{F2}}{C_{F0}+C_{F1}+C_{F2}}}={\displaystyle \frac{C_{F3}{C}_{F4}}{C_{F3}+C_{F4}}}=C_{F5}$$

(24)

Additionally, $C_{F0}$ and $C_{F1}$ operate in series during phase ${\mathrm{\Phi }}_1$ and in parallel during ${\mathrm{\Phi }}_3$. In ${\mathrm{\Phi }}_1$, if $C_{F0}\ne C_{F1}$, adding the same amount of charge to each will result in different voltage increments. Upon transitioning to the parallel state in ${\mathrm{\Phi }}_3$, a surge current will occur due to the voltage difference between $C_{F0}$ and $C_{F1}$. Thus, it is necessary for $C_{F0}$ to equal $C_{F1}$. Assume the capacitance value of $C_{F0}$ and $C_{F1}$ is C, expressed as

$$C_{F0}=C_{F1}=C.$$

(25)

By combining Equations (23), (24), and (25), the optimized values of the flying capacitors can be derived as

$$\left\{\begin{array}{c}{C}_{F0}=C_{F1}=C\hfill \\ C_{F2}=3C\hfill \\ C_{F3}=1.5C\hfill \\ C_{F4}=6C\hfill \\ C_{F5}=1.2C\hfill \end{array}\right..$$

(26)

According to (26), the capacitance values in the six-order QCSC-TLAHD converter can be optimized to theoretically achieve complete soft charging of all capacitors. However, in practical applications, typical deviations and the discrete nature of the capacitance values make achieving the theoretical capacitance ratio challenging. Additionally, factors such as the switch on-resistance and the capacitor ESR further complicate the attainment of complete soft charging for the flying capacitors. Nevertheless, effective reductions in the burst currents can be achieved when the capacitance ratio approximately matches that in (26), facilitating quasi-complete soft charging. It is evident that throughout the entire derivation process of (22)–(26), the duty cycles $D_1$ and $D_2$ are not involved. This is because they do not alter the intrinsic charge ratio of the flying capacitors. Therefore, both before and after duty cycle matching, the converter remains suitable for the derivation process, enabling quasi-complete soft charging of the flying capacitors.

Assume

$$\Delta V_C={\displaystyle \frac{q}{C}}.$$

(27)

According to Equations (26) and (27), the voltage ripples of $C_{F0}$–$C_{F5}$ are $\Delta V_C$, $\Delta V_C$, ${\displaystyle \frac{2}{3}}\Delta V_C$, ${\displaystyle \frac{4}{3}}\Delta V_C$, ${\displaystyle \frac{1}{3}}\Delta V_C$, and ${\displaystyle \frac{5}{3}}\Delta V_C$ under quasi-complete soft charging operations, as shown in Figure 3d. The average voltages across the flying capacitors can be obtained from Table 1, and then

Table 3. The flying capacitor voltages $v_{CF,j}$ and node voltages $V_{SW1,2}$ in the six-order QCSC-TLAHD converter.

Phase	Parameter	D1 = D2			Duty Cycle Matching
		Initial	Final	$\Delta$	Initial	Final	$\Delta$
${\mathrm{\Phi }}_1$	${\displaystyle v_{CF0,1}}$	${\displaystyle \frac{5V_{IN}}{11}-\frac{\Delta V_C}{2}}$	${\displaystyle \frac{5V_{IN}}{11}+\frac{\Delta V_C}{2}}$	${\displaystyle \Delta V_C}$	${\displaystyle \frac{9V_{IN}}{20}-\frac{\Delta V_C}{2}}$	${\displaystyle \frac{9V_{IN}}{20}+\frac{\Delta V_C}{2}}$	${\displaystyle \Delta V_C}$
	$v_{CF2}$	${\displaystyle \frac{4V_{IN}}{11}+\frac{\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{11}-\frac{\Delta V_C}{3}}$	${\displaystyle -\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{30}+\frac{\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{30}-\frac{\Delta V_C}{3}}$	${\displaystyle -\frac{2\Delta V_C}{3}}$
	$v_{CF3}$	${\displaystyle \frac{3V_{IN}}{11}-\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{3V_{IN}}{11}+\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{4\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{15}-\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{15}+\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{4\Delta V_C}{3}}$
	$v_{CF4}$	${\displaystyle \frac{2V_{IN}}{11}+\frac{\Delta V_C}{6}}$	${\displaystyle \frac{4V_{IN}}{11}-\frac{\Delta V_C}{6}}$	${\displaystyle -\frac{\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{60}+\frac{\Delta V_C}{6}}$	${\displaystyle \frac{11V_{IN}}{60}-\frac{\Delta V_C}{6}}$	${\displaystyle -\frac{\Delta V_C}{3}}$
	$v_{CF5}$	${\displaystyle \frac{V_{IN}}{11}-\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{11}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{5\Delta V_C}{3}}$	${\displaystyle \frac{V_{IN}}{12}-\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{12}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{5\Delta V_C}{3}}$
	$V_{SW2}$	${\displaystyle \frac{V_{IN}}{11}+\Delta V_C}$	${\displaystyle \frac{V_{IN}}{11}-\Delta V_C}$	${\displaystyle -2\Delta V_C}$	${\displaystyle \frac{V_{IN}}{10}+\Delta V_C}$	${\displaystyle \frac{V_{IN}}{10}-\Delta V_C}$	${\displaystyle -2\Delta V_C}$
${\mathrm{\Phi }}_3$	$v_{CF0,1}$	${\displaystyle \frac{5V_{IN}}{11}+\frac{\Delta V_C}{2}}$	${\displaystyle \frac{5V_{IN}}{11}-\frac{\Delta V_C}{2}}$	${\displaystyle -\Delta V_C}$	${\displaystyle \frac{9V_{IN}}{20}+\frac{\Delta V_C}{2}}$	${\displaystyle \frac{9V_{IN}}{20}-\frac{\Delta V_C}{2}}$	${\displaystyle -\Delta V_C}$
	$v_{CF2}$	${\displaystyle \frac{4V_{IN}}{11}-\frac{\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{11}+\frac{\Delta V_C}{3}}$	${\displaystyle \frac{2\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{30}-\frac{\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{30}+\frac{\Delta V_C}{3}}$	${\displaystyle \frac{2\Delta V_C}{3}}$
	$v_{CF3}$	${\displaystyle \frac{3V_{IN}}{11}+\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{3V_{IN}}{11}-\frac{2\Delta V_C}{3}}$	${\displaystyle -\frac{4\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{15}+\frac{2\Delta V_C}{3}}$	${\displaystyle \frac{4V_{IN}}{15}-\frac{2\Delta V_C}{3}}$	${\displaystyle -\frac{4\Delta V_C}{3}}$
	$v_{CF4}$	${\displaystyle \frac{2V_{IN}}{11}-\frac{\Delta V_C}{6}}$	${\displaystyle \frac{4V_{IN}}{11}+\frac{\Delta V_C}{6}}$	${\displaystyle \frac{\Delta V_C}{3}}$	${\displaystyle \frac{11V_{IN}}{60}-\frac{\Delta V_C}{6}}$	${\displaystyle \frac{11V_{IN}}{60}+\frac{\Delta V_C}{6}}$	${\displaystyle \frac{\Delta V_C}{3}}$
	$v_{CF5}$	${\displaystyle \frac{V_{IN}}{11}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{11}-\frac{5\Delta V_C}{6}}$	${\displaystyle -\frac{5\Delta V_C}{3}}$	${\displaystyle \frac{V_{IN}}{12}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{12}-\frac{5\Delta V_C}{6}}$	${\displaystyle -\frac{5\Delta V_C}{3}}$
	$V_{SW1}$	${\displaystyle \frac{V_{IN}}{11}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{11}-\frac{5\Delta V_C}{6}}$	${\displaystyle -\frac{5\Delta V_C}{3}}$	${\displaystyle \frac{V_{IN}}{12}+\frac{5\Delta V_C}{6}}$	${\displaystyle \frac{V_{IN}}{12}-\frac{5\Delta V_C}{6}}$	${\displaystyle -\frac{5\Delta V_C}{3}}$

presents the flying capacitor voltages and node voltages.

Figure 7 illustrates the simulated waveforms of the flying capacitor voltages $v_{CF,j}\left(t\right)$, currents $i_{CF,j}\left(t\right)$, and node voltages $v_{SW1,2}\left(t\right)$ for a converter operating with 48 V to 1 V, a 30 A output current, and a 300 kHz switching frequency. In Figure 7a, $D_1$ equals $D_2$, and the capacitance of all of the flying capacitors is 2 µF. In Figure 7b, duty cycle matching is performed, and the optimized values of $C_{F0}$–$C_{F5}$ are 1 µF, 1 µF, 3 µF, 1.5 µF, 6 µF, and 1.2 µF, respectively. As shown in Figure 7, the simulations reveal that the surge currents are significantly reduced following capacitance optimization. Specifically, before optimization, the surge currents could reach approximately 170 A, whereas after optimization, they consistently remained below 20 A. This substantial reduction in the surge currents indicates that the flying capacitors have entered a quasi-complete soft charging state, thereby minimizing the losses caused by the charge redistribution during switching transitions. This optimization contributes to improving the conversion efficiency. Figure 7a demonstrates that without capacitance optimization, abrupt changes in voltage occur for the flying capacitors during switch transitions, leading to spike currents and resulting in hard charging of the capacitors. Figure 7b shows that after capacitance optimization, quasi-complete soft charging of the flying capacitors can be achieved.

4.2. Capacitance Optimization for N-Order QCSC-TLAHD Converters

The intrinsic charge-ratio-based optimization method for flying capacitors can be extended to N-order QCSC-TLAHD converters. Due to the distinct switched capacitor networks and charge transfer paths in even- and odd-order converters, separate discussions are necessary.

In even-order converters, the flying capacitors, except for $C_{F0}$ and $C_{F1}$, which transfer a charge of q, are responsible for a charge transfer of $2q$, with ${\displaystyle \frac{N}{2}}$ parallel capacitor branches during phases ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$. Similar to (23) and (24), to achieve complete soft charging of the flying capacitors $C_{F0}$-$C_{F,N-1}$ in N-order converters, Equation (28) must be satisfied.

$$\left\{\begin{array}{c}{\displaystyle \frac{C_{F0}{C}_{F1}}{C_{F0}+C_{F1}}}={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F2}{C}_{F3}}{C_{F2}+C_{F3}}}=...={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F,N-2}{C}_{F,N-1}}{C_{F,N-2}+C_{F,N-1}}}\hfill \\ {\displaystyle \frac{\left(C_{F0}+C_{F1}\right)C_{F2}}{C_{F0}+C_{F1}+C_{F2}}}={\displaystyle \frac{C_{F3}{C}_{F4}}{C_{F3}+C_{F4}}}=...={\displaystyle \frac{C_{F,N-3}{C}_{F,N-2}}{C_{F,N-3}+C_{F,N-2}}}=C_{F,N-1}\hfill \end{array}\right.$$

(28)

Substituting (25) into (28) yields the optimized capacitance for flying capacitors as

$$\begin{array}{c}\hfill C_{F,j|N=Even}=\left\{\begin{array}{c}{\displaystyle \frac{2N}{N-j}}C,j=\left\{\begin{array}{cccc}2,& 4,& ...& N-2\end{array}\right\}\hfill \\ {\displaystyle \frac{2N}{N+j-1}}C,j=\left\{\begin{array}{cccc}3,& 5,& ...& N-1\end{array}\right\}\hfill \end{array}\right..\end{array}$$

(29)

In odd-order converters, $C_{F0}$ and $C_{F1}$ transfer a charge of q, while other capacitors are responsible for a charge transfer of $2q$. Different from even-order converters, odd-order ones have ${\displaystyle \frac{N+1}{2}}$ and ${\displaystyle \frac{N-1}{2}}$ parallel capacitor branches during phases ${\mathrm{\Phi }}_1$ and ${\mathrm{\Phi }}_3$, respectively. To achieve complete soft charging of the flying capacitors, Equation (26) must be met.

$$\left\{\begin{array}{c}{\displaystyle \frac{C_{F0}{C}_{F1}}{C_{F0}+C_{F1}}}={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F2}{C}_{F3}}{C_{F2}+C_{F3}}}=...={\displaystyle \frac{1}{2}}{\displaystyle \frac{C_{F,N-3}{C}_{F,N-2}}{C_{F,N-3}+C_{F,N-2}}}={\displaystyle \frac{C_{F,N-1}}{2}}\hfill \\ {\displaystyle \frac{\left(C_{F0}+C_{F1}\right)C_{F2}}{C_{F0}+C_{F1}+C_{F2}}}={\displaystyle \frac{C_{F3}{C}_{F4}}{C_{F3}+C_{F4}}}=...={\displaystyle \frac{C_{F,N-2}{C}_{F,N-1}}{C_{F,N-2}+C_{F,N-1}}}\hfill \end{array}\right.$$

(30)

Substituting (25) into (30) yields the capacitance as

$$\begin{array}{c}\hfill C_{F,j|N=Odd}=\left\{\begin{array}{c}{\displaystyle \frac{2\left(N-1\right)}{N+j-1}}C,j=\left\{\begin{array}{cccc}2,& 4,& ...& N-1\end{array}\right\}\hfill \\ {\displaystyle \frac{2\left(N-1\right)}{N-j}}C,j=\left\{\begin{array}{cccc}3,& 5,& ...& N-2\end{array}\right\}\hfill \end{array}\right..\end{array}$$

(31)

As derived in (29) and (31), it is evident that both even- and odd-order ($N>2$) converters have optimal capacitance solutions for quasi-complete soft charging of the flying capacitors.

4.3. Considerations

Achieving quasi-complete soft charging of flying capacitors can enhance their utilization, allowing them to withstand higher voltage ripples. However, in practical applications, factors such as the switching frequency, input and output voltages, and power transmission must be considered to set the appropriate boundary conditions for the capacitors, ensuring the converter’s normal operation.

At a specific operating frequency, as the power rises, the charge q from $V_{IN}$ during ${\mathrm{\Phi }}_1$ escalates, resulting in higher voltage ripples on the flying capacitors. This directly steepens the switch node voltages $v_{SW1,2}$, with the minimum values approaching zero, as shown in the simulation results in Figure 7b. When $v_{SW2}$ during ${\mathrm{\Phi }}_1$ or $v_{SW1}$ during ${\mathrm{\Phi }}_3$ reaches zero, the inductor current flows through the body diode of the corresponding freewheeling switch, assuming a negligible drop in voltage across the diode. This indicates that the flying capacitors have reached their maximum charge transfer capacity, and the converter has achieved peak power transmission.

In even-order converters, as shown in Table 1, the average voltages $V_{CF,j}$ across flying capacitors after equalization of the inductor current are described as

$$\begin{array}{c}\hfill V_{CF,j|N=Even}=\left\{\begin{array}{c}\left({\displaystyle \frac{1}{4}}+{\displaystyle \frac{N-2}{4\left(N-1\right)}}\right)V_{IN},j=0\hfill \\ \left({\displaystyle \frac{N-j+1}{4N}}+{\displaystyle \frac{N-j-1}{4\left(N-1\right)}}\right)V_{IN},j=\left\{\begin{array}{ccccc}1,& 3,& 5,& ...& N-1\end{array}\right\}\hfill \\ \left({\displaystyle \frac{N-j}{4N}}+{\displaystyle \frac{N-j}{4\left(N-1\right)}}\right)V_{IN},j=\left\{\begin{array}{cccc}2,& 4,& ...& N-2\end{array}\right\}\hfill \end{array}\right..\end{array}$$

(32)

Equation (25) indicates that the capacitance value of $C_{F0}$ and $C_{F1}$ is C. During ${\mathrm{\Phi }}_1$, combining (27), the charge q flows through the capacitor branch $C_{F0}-C_{F1}$, resulting in a voltage increase of ${\displaystyle \frac{q}{C/\phantom{C2}2}}$ ($=2\Delta V_C$). Therefore, the minimum voltage $V_{SW2,MIN}$ at node SW2 can be expressed as

$$\begin{array}{c}\hfill V_{SW2,MIN}=V_{IN}-V_{CF0}-V_{CF1}-\Delta V_C={\displaystyle \frac{V_{IN}}{2\left(N-1\right)}}-\Delta V_C.\end{array}$$

(33)

According to (29), the optimized value of $C_{F2}$ is denoted as ${\displaystyle \frac{2N}{N-2}}C$. The equivalent capacitance of the branch $((C_{F0}\Vert C_{F1})-C_{F2})$ is represented by ${\displaystyle \frac{N}{N-1}}C$ during ${\mathrm{\Phi }}_3$. With the charge of $2q$ passing through this branch, a voltage increment $2{\displaystyle \frac{N-1}{N}}\Delta V_C$ is produced. Integrating this with the average voltages of $C_{F1}$ and $C_{F2}$ from (32), the minimum voltage $V_{SW1,MIN}$ at node SW1 can be described as

$$\begin{array}{c}\hfill V_{SW1,MIN}=V_{CF,1}-V_{CF,2}-{\displaystyle \frac{N-1}{N}}\Delta V_C={\displaystyle \frac{V_{IN}}{2N}}-{\displaystyle \frac{N-1}{N}}\Delta V_C.\end{array}$$

(34)

From the analysis above, it is evident that both $V_{SW1,MIN}$ and $V_{SW2,MIN}$ should be greater than zero to ensure the converter possesses a sufficient energy conversion capability. Thus, from (33) and (34), it is derived as

$$\Delta V_C<{\displaystyle \frac{V_{IN}}{2\left(N-1\right)}}.$$

(35)

Under ideal conditions, the converter’s peak power $P_{MAX}$ can be represented as

$$P_{MAX}=V_{IN}{\displaystyle \frac{q}{T_S}}.$$

(36)

Combining Equations (27), (35), and (36), it can be deduced that $C>2\left(N-1\right){\displaystyle \frac{P_{MAX}{T}_S}{V_{IN}^2}}$. Considering the input voltage fluctuates, it must be ensured that

$$C{|}_{N=Even}>2\left(N-1\right){\displaystyle \frac{P_{MAX}{T}_S}{V_{IN,MIN}^2}},$$

(37)

where $V_{IN,MIN}$ denotes the minimum input voltage.

For odd-order converters, the derivation follows the same procedure as (32)–(37). The capacitance C must satisfy the constraint given by (34).

$$C{|}_{N=Odd}>2N{\displaystyle \frac{P_{MAX}{T}_S}{V_{IN,MIN}^2}}$$

(38)

5. The Prototype and Experimental Verification

To verify the feasibility of the proposed topology, a prototype of the six-order QCSC-TLAHD converter was implemented to convert 48 V into 0.5–2.0 V. The prototype and experimental platform are illustrated in Figure 8a and Figure 8b, respectively. To validate the principle of duty cycle matching to equalize the average inductor current, it is essential to flexibly control the ratio of $D_1$ and $D_2$ and generate high-frequency drive pulses. In this study, the TMS320F28335PGFA microcontroller from Texas Instruments, featuring high-precision PWM, serves as the controller. Table 1 specifies the ratio of $D_1$ to $D_2$ as 6:5. To achieve quasi-complete soft charging, the capacitance optimization is guided by (26), while the selection of the capacitors for other-order converters can be determined using (25), (29), and (31). The list of key components is presented in

Table 4. Key components and parameters.

Component	Design Selection
$C_{F0}$–$C_{F5}$	3 × 0.22 µF, 3 × 0.22 µF, 4 × 0.47 µF/0.1 µF, 2 × 0.47 µF, 8 × 0.47 µF/2 × 0.1 µF, 0.47 µF/0.22 µF/0.1 µF, Murata, C0G
$C_O$	6 × 47 µF, 6.3 V, Murata, X7R
$C_{IN}$	6 × 10 µF, 100 V, TDK, X7R
$S_1$–$S_5$	BSC026NE2LS5, Infineon
$S_6$, $S_7$	BSC009NE2LS5I, Infineon
$S_8$	BSC066N06NS, Infineon
$S_9$–$S_{11}$	BSC059N04LS6, Infineon
$L_1$, $L_2$	IHLP3232DZERR47M01, VISHAY
Microcontroller	TMS320F28335PGFA, TI
High-side driver	8 × LTC4440-5, ADI
Low-side driver	3 × UCC27517DBVR, TI

.

Figure 9 illustrates that the converter can achieve equalized average inductor currents across various voltage conversion ratios and load conditions. This confirms the effectiveness of the duty-cycle-matching-based current equalization method discussed in Section 3.1. After duty cycle matching, the average currents of inductors $L_1$ and $L_2$ are approximately equal, and the slope of $i_{L2}$ is greater than that of $i_{L1}$, consistent with the simulation results in Figure 5b. This phenomenon arises from the fact that, after duty cycle matching, inductor $L_2$ experiences a higher excitation voltage ($V_{SW2}>V_{SW1}$). This observation aligns with the expressions for the node voltage swings provided in Table 1 for even-order converters.

Figure 10 presents the voltage waveforms of the flying capacitors $C_{F0}$–$C_{F5}$ and the current waveforms of the inductors $L_1$ and $L_2$ during the conversion from 48 V into 1 V with an output current of 20 A in the converter. Without capacitance optimization for $C_{F0}$–$C_{F5}$ (each being 4 × 0.47 µF, 11.28 µF in total), the voltage ripples are depicted in Figure 10a. The voltage transients in the dashed box indicate hard charging of the flying capacitors. From Figure 10b, the optimized flying capacitors, as listed in Table 4, achieve quasi-complete soft charging. The voltage ripple ratios of $C_{F0}$–$C_{F5}$ are consistent with those in Figure 3d and Table 3. In addition, the flying capacitors can withstand larger voltage ripples, enhancing their utilization. Figure 10c shows that in steady-state operation, the average voltages of $C_{F0}$–$C_{F5}$ are approximately 21.6 V, 21.6 V, 17.6 V, 12.8 V, 8.8 V, and 4 V, respectively. These data are consistent with the theoretical values in Table 1 (${\displaystyle \frac{9V_{IN}}{20}}$, ${\displaystyle \frac{9V_{IN}}{20}}$, ${\displaystyle \frac{11V_{IN}}{30}}$, ${\displaystyle \frac{4V_{IN}}{15}}$, ${\displaystyle \frac{11V_{IN}}{60}}$, ${\displaystyle \frac{V_{IN}}{12}}$), indicating self-balancing of the flying capacitors. The theoretical analysis of voltage balancing in the flying capacitor in Section 2.2 confirms that the balancing is not sensitive to specific capacitor values. The use of low-ESR C0G capacitors minimizes the impact of ESR, ensuring that voltage balancing remains unaffected. During dead time, all power switches are turned off, preventing any influence on the capacitor voltage balancing. Additionally, temperature variations have a negligible effect on the capacitors’ stability, as the C0G capacitors feature a low temperature coefficient, ensuring their stable performance across a wide temperature range.

Figure 11 shows that under specific operating frequency and input–output voltage conditions, as the power consumption increases, the minimum values of the node voltage swings $V_{SW1}$ and $V_{SW2}$ progressively reduce towards zero. As discussed in Section 4.3, when the minimum values approach zero, the converter reaches its maximum power conversion capacity.

Under natural convection, temperature measurements are taken using an infrared thermometer for the converter operating at 300 kHz with 48 V to 1 V and an output current of 30 A. Figure 12a indicates that the highest temperature in the measured area is approximately 74.0 °C. Two distinct hotspots are observed at the positions of the freewheeling switches $S_6$ and $S_7$, which carry a significantly higher current than all other power switches, as shown in Figure 12b. The power loss breakdown of the converter is shown in Figure 12b. The power switch losses, including the conduction loss, switching loss, and drive loss, can be analyzed according to the method outlined in [35]. The calculation method for ESR loss in flying capacitors is provided in [36]. Inductor-related losses can be calculated using the integrated power inductor calculation tool offered by VISHAY [32]. To ensure the safe operation of the power switches and minimize conduction losses in the body diode, a dead time of 50 ns is implemented. The gate drivers are powered by a 15 V auxiliary supply, which guarantees reliable conduction of the high-side switches (accounting for the drop in voltage of the bootstrap diode) and ensures the low-side switches operate within their specified voltage range. The loss analysis reveals that freewheeling switches $S_6$ and $S_7$ contribute approximately 13.6% of the total loss, making them the most lossy active devices. This also explains why $S_6$ and $S_7$ become hotspots in Figure 12a. Additionally, the inductors’ losses are the largest, accounting for approximately 42.9%, making them a key focus for improving the conversion efficiency.

Figure 13 depicts the measured efficiency curves of the converter, which converts from 48 V to 1 V, at different operating frequencies after duty cycle matching and capacitance optimization. As the frequency decreases, the conversion efficiency increases. This improvement is primarily attributed to quasi-complete soft charging of the flying capacitors, which facilitates the elimination of SSL resistance. As a result, reducing the frequency does not induce a significant spike current loss and also results in reduced switching losses in the transistors, consequently leading to increased efficiency. However, the decreased frequency results in an extended switching period, as noted in (37), which in turn decreases the converter’s power capacity, leading to a reduction in power density. The prototype discussed in this article operates at a frequency of 300 kHz.

For the converter operating at 300 kHz with a step-down ratio of 48 V to 1 V, Figure 14a presents the measured efficiency curves under three scenarios: (1) duty cycle matching with capacitance optimization; (2) $D_1=D_2$ with capacitance optimization; and (3) $D_1=D_2$, $C_{F0-5}$ = 4 × 0.47 µF. The results indicate that under a high load current ($I_O>13$ A), quasi-complete soft charging of the flying capacitors contributes significantly to efficiency enhancements. Specifically, at a 30 A output, the efficiency demonstrates an improvement of approximately 2.94% after capacitance optimization. Additionally, the measured efficiencies of the converter before and after duty cycle matching are essentially the same, consistent with the analysis in Section 3.2. This indicates that equalizing the average inductor currents has a limited impact on efficiency optimization. Figure 14b shows that at 36 V to 1 V and $I_O$ = 22 A, the efficiency optimization reaches up to 5.07%. This phenomenon arises because under the low-input-voltage conditions, the converter operates with a higher duty cycle, necessitating the flying capacitors to transfer more charge for the same output current. Non-optimized flying capacitors experience increased charge transfer during rebalancing, resulting in higher spike current losses. In summary, achieving quasi-complete soft charging of the flying capacitors is crucial for optimizing the converter efficiency.

Figure 15 presents the measured efficiency curves of the converter operating at 300 kHz for various voltage conversions: 60 V to 2 V, 48 V to 2 V, 48 V to 1 V, and 48 V to 0.5 V. Figure 15 also demonstrates that under 48 V-to-1 V conversion, the measured power efficiency of the converter is marginally lower than the simulated values at high-load operation, with this discrepancy predominantly arising from unmodeled parasitic losses in the PCB trace resistance. In the typical 48 V-to-1 V application, the converter achieves a peak efficiency of 91.96% at $I_O$ = 11 A. Moreover, the volume of the prototype’s components is quantified as 0.0635 in³. The converter attains a power density of up to 944.88 W/in³.

Table 5. Comparisons among different converters suitable for large-ratio step-down applications.

	TPE 2020 [22]	TPE 2023 [29]	JESTPE 2021 [25]	TIA 2023 [36]	ECCE 2021 [26]	This Work
Topology	HD	SDIH	DIH	DPHD	DIH	QCSC-TLAHD
M (${\displaystyle \frac{V_O}{V_{IN}}}$)	${\displaystyle \frac{2D}{N}}$	${\displaystyle \frac{D}{N}}$	${\displaystyle \frac{D}{N}}$	${\displaystyle \frac{2D}{\left(N+2\right)D+\left(N-2\right)}}$ (Even) ${\displaystyle \frac{2D}{\left(N+1\right)D+\left(N-1\right)}}$ (Odd)	${\displaystyle \frac{D}{N}}$	${\displaystyle \frac{D}{2N-1}}$
VIN/VO	48 V/3.3V	48 V/1–3 V	48 V/1–2 V	36–65 V/1–2 V	48 V/1–3 V	48 V/0.5–2 V
Max. IO	10.9 A	116 A	20 A	32 A	70 A	30 A
Type/Num. of Switches	MOS/32	MOS/14	GaN/9	MOS/10	MOS/8	MOS/11
fSW	250 kHz	750 kHz	150 kHz	250 kHz	750 kHz	300 kHz
Capacitor	12	10	6	6	5	6
Inductor	4 × 3.3 µH	2 × 150 nH	2 × 2.2 µH	260 nH	2 × 1 µH	2 × 470 nH
Component Volume (a)	N/A	0.073 in3	N/A	0.135 in3	0.168 in3	0.0635 in3
Power Density (a)	N/A	1588 W/in3	N/A	481 W/in3	892 W/in3	944.88 W/in3
Peak Efficiency	N/A	83.5% @48/1 V	92.4% @48/1 V	90.6% @48/1 V, 13 A	87.5% @48/1 V	91.96% @48V/1 V, 11 A

^(a) Considering only the component volume in the power stage.

compares the performance of the proposed QCSC-TLAHD converter prototype with several state-of-the-art high-conversion-ratio DC-DC converters. As shown in the table, the QCSC-TLAHD converter achieves the highest duty cycle extension factor ($2N-1$), enabling a higher switch duty cycle, which makes it particularly suitable for high-conversion-ratio step-down applications. The duty cycle extension factor of ($2N-1$), as presented in the third row of Table 5, is derived from (11) and represents the theoretical extension of the duty cycle enabled by the proposed QCSC-TLAHD converter. This factor highlights the converter’s capability to accommodate larger duty cycles, making it particularly advantageous for high-step-down-voltage conversions. The generalized expression in Table 5 facilitates comparison with other topologies, demonstrating that the proposed topology offers a superior duty cycle extension capability. While the peak conversion efficiency of the proposed converter is slightly lower than the 92.4% achieved using the DIH converter in [25], the latter benefits from the use of higher-cost GaN switches. Furthermore, only the volumes of power components such as switches, inductors, capacitors, and drivers are considered in order to compare the volume (power density) performance of the proposed converter with that of other studies. The proposed converter achieves a power density that is second only to that reported in [29]. Although the SDIH converter demonstrates a higher power density, this is achieved at the cost of s significantly lower conversion efficiency. In summary, the comparison in Table 5 highlights that the QCSC-TLAHD converter strikes a favorable balance between power density and conversion efficiency.

6. Conclusions

This article presents a quasi-complete soft charging three-level-assisted hybrid Dickson converter topology suitable for high-step-down-ratio applications. This topology achieves self-balancing of the flying capacitor voltages and average interleaved inductor currents, with both even- and odd-order ($N>2$) converters facilitating a ($2N-1$)-fold duty cycle expansion. A duty-cycle-matching-based current equalization approach is proposed to ensure equal average inductor currents. Furthermore, an intrinsic charge-ratio-based capacitance optimization method is introduced, enabling quasi-complete soft charging of all flying capacitors, thereby optimizing the conversion efficiency and enhancing the capacitor utilization. Finally, a prototype capable of supporting up to a 30 A load current validates the converter’s operational principles, with voltage conversion from 48 V down to 0.5–2.0 V. The experimental results confirm the equalization of the average inductor currents and quasi-complete soft charging of all flying capacitors. A 2.94% improvement in the conversion efficiency is observed at 48 V to 1 V and a 30 A load, with the peak efficiency reaching 91.96% at 11 A. The prototype attains a power density of up to 944.88 W/in³. Therefore, this converter is a competitive candidate for PoL regulators in large-ratio voltage conversion applications, such as data centers.