Losses and Efficiency Evaluation of the Shunt Active Filter for Renewable Energy Generation

Abstract

The Shunt Active Filter (SAF) is an effective solution for mitigating electrical perturbations in power networks. SAFs usually consist of a voltage source inverter (VSI) with lossy transistors and bulky inductors. In this context, this article proposes analytical models to evaluate the losses and efficiency of a SAF. The models include conduction and switching losses in the transistors and diodes and are valid for both IGBT and SiC MOSFET transistors. The methodology consists of analysing the current waveform to separate the portion flowing through the transistor or diode. IGBT and SiC MOSFET are compared in two cases: firstly, the classic SAF operation with harmonic and reactive power compensation and, secondly, in the case of power injection by a photovoltaic panel or batteries, in addition to the classic SAF operation. The results are validated with real manufacturer data. A step-by-step comparison shows a good accuracy of the model. Therefore, the developed methodology is useful for a SAF designer to select relevant components for the converter and to estimate the efficiency of the system accurately and quickly.

1. Introduction

The Shunt Active Filter (SAF) is an advanced solution to compensate the grid side of electrical perturbations, like harmonics, reactive power, unbalance, etc., caused by linear and non-linear loads (power electronics-based devices, appliances including energy-saving lighting, etc.) [1]. In this context, “conventional” SAFs [2] are based on a two-level voltage source inverter (VSI) with silicon components, associated with a first-order coupling/output filter, i.e., conventional series inductance with simplified control. This structure is industrially and traditionally limited by a DC voltage of 800 V and a switching frequency of 16 kHz because of the use of silicon IGBTs. It requires consequently a heavy, bulky, expensive, and difficult-to-size output inductor of 2 to 5 mH [3]. It is worth noting that the output inductance must validate two criteria: prevent the propagation of switching frequency components from the VSI to the grid side and avoid degradation of the overall structure dynamics [1,3]. This can be ensured by an LCL-type filter [4,5]. This solution aims to keep the conventional VSI with 800 Vdc and 16 kHz, while taking advantage of the benefits offered by the LCL output/coupling filter.

On the other hand, to combat climate change and validate the United Nations’ Sustainable Development Goals 2030, renewable energy sources (RES)s, particularly photovoltaic and wind farms, have been proposed as advanced alternative solutions to fossil energy production. These modern solutions are economical, safe, reliable, and ecological.

In this context, VSI-grid-connected photovoltaic (PV) or wind turbine (WT) systems are proposed for renewable energy production [6,7]. RES systems have almost the same topology as SAFs but generate only active and reactive powers into the network.

In this article, a VSI-based SAF for Renewable Energy Generation (SAF-REG) is studied. The DC renewable energy source can consist of photovoltaic panels or batteries. In this case, as illustrated in Figure 1, the photovoltaic modules are installed on the DC bus side. In addition to perturbation compensation, including harmonic filtering, the extended SAF-REG detects, calculates, and injects the maximum power of the PV modules/generators to the network through a small and economic L-series output/coupling filter. A non-linear load, representing for example an industrial rectifier, is connected on a distribution grid, represented by a perfect three-phase voltage source. Currents I_grid and I_load are measured to control the filtering effect of the SAF. I_DC is measured to control the power injection. The control circuit and algorithm are not detailed in this article, as many references deal with this subject [8,9,10,11].

The goal of this article is to evaluate the efficiency of the voltage source inverter (VSI) used for this SAF-REG function. Many research works [12,13,14] propose models to evaluate losses in VSI. As the current waveforms are considered sinusoidal, it is not applicable for a SAF system. The question of the energy efficiency of SAFs is addressed by very few studies in the literature. References [15,16] compare the efficiency of different active filter structures. They present analytical loss models but do not take into account the particularities of SAF waveforms. In [17], a switching loss analysis is performed in the particular case of a multilevel SAF.

This article is organized as follows. The specifications of this study are given in Section 2. Considering the current waveforms analysed in Section 3, new models are developed and adapted to the study case in Section 4, namely the Shunt Active Filter (SAF) and the SAF with power generation. This study considers conventional Silicon IGBT (C-VSI) and fast-switching Silicon Carbide MOSFET (VSI-SiC) in Section 5. The developed models are compliant with both transistor technologies and are validated by comparison with loss measurements computed in the PLECS software (4.6.9 version), including real manufacturer data. Finally, different industrial switching frequencies and DC voltages are tested in Section 6 to detect the maximum values that allow us to achieve maximum efficiency while ensuring high dynamics and then high-quality performance of the SAF-REG.

2. Electrical Structure Specifications

The electrical specifications applied to the SAF structure are given in

Table 1. Main input data of the studied SAF.

Symbol	Parameter	Unit	Value
Vdc	DC voltage	V	800
Vs	RMS phase-to-neutral PCC voltage	V	230
Vfund	Fundamental/grid frequency	Hz	50
Vsw	Switching frequency	kHz	16 and 100
Iload	RMS current in the non-linear load	A	61
ISAF	RMS current in the SAF	A	72
Igrid	RMS current from or to the grid	A	+61 without power injection −11 with power injection

. The current and voltage RMS values are fixed in addition to the two values of comparison for the switching frequency.

The non-linear load consumes 61 A per phase. Without power injection from the SAF, the grid provides 61 A. With power injection from the SAF, extra power up to 72 A can be added, which feeds the non-linear load. As a consequence, the grid receives an extra 11 A from the SAF. These are the maximal operating values. The value of 800 Vdc was chosen based on the experimental setup already published and referenced as [5] in the manuscript. In [5], the nominal DC voltage was 840 V. This value is normalized to 800 V in the proposed manuscript. Other references use DC voltage values down to 650 V, which is the minimum value to ensure a connection with a 230/400 V 3-phase AC grid. The influence of the DC voltage is investigated in the sixth section of this article.

In accordance with Figure 1, the VSI structure used is a two-level three-phase full bridge with diode D in parallel with transistor K and is given in Figure 2.

Two technologies of transistors are considered in this study: an IGBT for the conventional structure (C-VSI) and a SiC MOSFET (SiC-VSI). For the IGBT, the reference is IKQ50N120CH3, with a voltage rating of 1200 V, a current rating of 65 A at 100 °C, and a unit price of USD 10. For the SiC MOSFET, the reference is C3M0021120K, with an identical voltage rating of 1200 V, a higher current rating of 74 A at 100 °C, and a unit price three times higher of USD 30.

3. Current Waveforms

In a VSI, considering the correct switched current waveform is crucial in order to compute the losses, as it varies all along a low-frequency period in a classic VSI, and as the current variation is all the more singular in the case of harmonic compensation.

In the first case, only the harmonics compensation is considered and therefore the resulting currents waveforms are shown in Figure 3. The modulating signal, which represents the identified harmonics current (I_SAFref) in green is then compared with a triangular carrier to generate a PWM signal; see Figure 1. Note that the load current (I_load) corresponds to a non-linear load: a 42 kVA diode full-bridge rectifier with R//C load on the DC side. In addition, the real harmonics current to be produced/injected (I_SAFref) by the SAF is obtained by subtracting the fundamental current (I_grid) from the load current (I_load).

The load current is the current absorbed by a three-phase rectifier on a R-C load, with some filtering inductance on the AC side. Each diode conducts during a third of a period, with a double arch current waveform. The exact waveform equation depends on the values of L and C. On one phase leg, the opposite diode conducts during another third of the period. Then, the phase current is the addition of both diode currents. According to the diode polarity, it results in a positive double arch during a third of the period and a negative double arch during another third of the period. During the last third, no diode conducts in the leg, which is why the current is null.

The SAF current (I_SAF) is compared, as represented in Figure 4, between the simulation injected current and the model reference. The small difference comes from the delay caused by the inductance/output filter, which prevents the injected current from varying quickly.

In a second case, active compensation with a power injection is considered. The SAF current is then different and is plotted in Figure 5. In this case, a sinusoidal current at the fundamental frequency is added to the harmonic compensation. This current is obtained by the addition of the current from Figure 4 with a sinusoidal current in phase with the grid. The small difference comes from the delay caused by the inductance.

4. SAF Loss Computation

Silicon Carbide (SiC) MOSFET C3M0021120K and IGBT IKQ50N120CH3 are compared, always with the same SiC diode C4D40120H. The methodology to compute losses in power components is depicted in the following lines, first only in the SAF condition (no power injection) and then in the SAF-REG condition (with power injection). Numerical values are computed and compared to a PLECS simulation in Section 5.

The comparison between the PLECS waveform and the mathematical waveform is proposed in Figure 4 and Figure 5. In both cases, the blue curves represent real measurements from a real SAF converter. These curves are saved and used to feed the PLECS simulation. The red curves represent the mathematical model, used for the analytical loss computation. The difference between the PLECS and the mathematical waveforms come from the influence of the SAF inductance, which introduce a small phase-shift and eliminates current discontinuities.

4.1. VSI Loss Computation in the SAF-Only Condition

It is first possible to compute the RMS current injected into a switch as MOSFET K in addition to a diode D with (1).

$$I_{\mathrm{K}+\mathrm{D} RMS}=\sqrt{{\displaystyle \frac{1}{2\pi }}{\int }_0^{2\pi }\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta }$$

(1)

with α(θ) as the duty cycle varying from 0 to 1 in a sinusoidal way, and with I_SAF(θ) as the mathematical piecewise SAF current waveform from Figure 5. This current waveform is displayed as applied in PLECS in Figure 6 for a switching frequency of 16 kHz, with power injection.

It is assumed that the positive current flows through the transistor and the negative current through the diode. This assumption is perfectly correct for the IGBT because it is a bipolar component. In the case of the MOSFET, the assumption does not take into account the current that may flow in the reverse direction of the transistor [12].

To obtain the injected current in one transistor K, the integral is separated in five parts, according to the moment when the current is positive. By reason of symmetry, the RMS and average currents in the transistor are expressed in (2) and (3). Angles θ_i are calculated at the intersection between the fundamental and the polluting load current.

$$I_{\mathrm{K}RMS}=\sqrt{\begin{array}{c}{\displaystyle \frac{1}{2\pi }}(2{\int }_{{\theta }_0}^{{\theta }_1}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \\ +2{\int }_{{\theta }_2}^{{\theta }_3}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \\ +{\int }_{{\theta }_8}^{{\theta }_9}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta )\end{array}}$$

(2)

$$I_{\mathrm{K} average}=\begin{array}{c}{\displaystyle \frac{1}{2\pi }}(2{\int }_{{\theta }_0}^{{\theta }_1}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta \\ +2{\int }_{{\theta }_2}^{{\theta }_3}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta \\ +{\int }_{{\theta }_8}^{{\theta }_9}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta )\end{array}$$

(3)

Computing the RMS and average current makes it possible to evaluate the conduction losses in a MOSFET and in an IGBT. The general formulation of conduction losses is given in (4). Formulas (5) and (6) are then obtained considering only a resistive impedance R_{DS on} for the MOSFET and a resistance R_K0 with a voltage drop V_K0 for an IGBT.

$$P_{K conduction}={\displaystyle \frac{1}{\mathrm{T}}}\int v_K\left(t\right).i_K\left(t\right)dt$$

(4)

$$P_{MOSFET conduction}=R_{DS on}.{I_{K rms}}^2$$

(5)

$$P_{IGBT conduction}=R_{\mathrm{K}0}.{I_{K rms}}^2+V_{\mathrm{K}0}.I_{K average}$$

(6)

The switching losses are computed considering the variation in switching energy function of the current, given by the MOSFET or IGBT datasheet. A quadratic interpolation is considered (7) from Figure 7, with Ct as a temperature coefficient chosen at 175 °C.

$$Etot\left(I\right)=Eon\left(I\right)+Eoff\left(I\right)=\left(a.I^2+b.I+c\right).Ct$$

(7)

Then, the switching losses are computed by integration of the switching energy when the current is positive and is multiplied by the switching frequency (8). The method of switching loss computation, developed in (8) and (9), is valid for both MOSFET and IGBT.

$$P_{K switching}=\begin{array}{c}{\displaystyle \frac{V_{DC}}{V_{ref}}}{\displaystyle \frac{F_{dec}}{2\pi }}[2{\int }_{{\theta }_0}^{{\theta }_1}{E}_{total}\left(I_{SAF}\left(\theta \right)\right)d\theta \\ +2{\int }_{{\theta }_1}^{{\theta }_2}{E}_{total}\left(I_{SAF}\left(\theta \right)\right)d\theta \\ +{\int }_{{\theta }_8}^{{\theta }_9}{E}_{total}\left(I_{SAF}\left(\theta \right)\right)d\theta ]\end{array}$$

(8)

The current in one diode is computed in a similar way. The integral is separated in five parts, according to the moment when the switched current is negative and then positive in the diode (Equations (9) and (10)).

$$I_{\mathrm{D} RMS}=\sqrt{\begin{array}{c}{\displaystyle \frac{1}{2\pi }}(2{\int }_{{\theta }_1}^{{\theta }_2}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \\ +{\int }_{{\theta }_3}^{{\theta }_4}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \\ +2{\int }_{{\theta }_7}^{{\theta }_8}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta )\end{array}}$$

(9)

$$I_{\mathrm{D} average}=\begin{array}{c}{\displaystyle \frac{1}{2\pi }}(2{\int }_{{\theta }_1}^{{\theta }_2}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta \\ +{\int }_{{\theta }_3}^{{\theta }_4}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta \\ +2{\int }_{{\theta }_7}^{{\theta }_8}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta )\end{array}$$

(10)

As the impedance of the diode in the ON state is similar to the IGBT impedance, i.e., resistance and a voltage drop, diode conduction losses are expressed in the same way (11). Recovery losses in the diode are neglected, which is a common assumption when working with SiC Schottky diodes. Finally, the total losses of the converter are expressed in (12).

$$P_D=V_{D0}.I_{D average}+R_{D0}.{I_{D RMS}}^2$$

(11)

$$P_{total}=6.(P_{K cond}+P_{K switching}+P_D)$$

(12)

4.2. VSI Loss Computation in the SAF-REG Condition

The same methodology is applied in the case of power injection from the photovoltaic system or the batteries. The only difference compared to the previous case lies in the bounds of the integrals for calculating currents and switching losses. Equations (13)–(16) summarize the different expressions.

$$I_{\mathrm{K} RMS PVG}=\sqrt{\begin{array}{c}{\displaystyle \frac{1}{2\pi }}{\int }_{{\theta }_1}^{{\theta }_6}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \end{array}}$$

(13)

$$I_{\mathrm{D} RMS PVG}=\sqrt{\begin{array}{c}{\displaystyle \frac{1}{2\pi }}\left({\int }_{{\theta }_0}^{{\theta }_1}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta +{\int }_{{\theta }_6}^{{\theta }_{10}}\alpha \left(\theta \right){I_{SAF}\left(\theta \right)}^{2}d\theta \right)\end{array}}$$

(14)

$$I_{\mathrm{D} average}=\begin{array}{c}{\displaystyle \frac{1}{2\pi }}\left({\int }_{{\theta }_0}^{{\theta }_1}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta +{\int }_{{\theta }_6}^{{\theta }_{10}}\alpha \left(\theta \right)I_{SAF}\left(\theta \right)d\theta \right)\end{array}$$

(15)

$$P_{K switching}=\begin{array}{c}{\displaystyle \frac{V_{DC}}{V_{ref}}}{\displaystyle \frac{F_{dec}}{2\pi }}{\int }_{{\theta }_1}^{{\theta }_6}{E}_{total}\left(I_{SAF}\left(\theta \right)\right)d\theta \end{array}$$

(16)

4.3. Design Considerations

The waveform presented in Figure 4, in the case of no power injection, with five cycles per period, is unusual. Then, the classic design approaches to choose the best semiconductor devices is not relevant. In fact, the five cycles lead to a repeated junction temperature variation in the devices, which may damage the components.

In the other case, with power injection, a 50 Hz component is injected in addition to the harmonic compensation. The five cycles are still present, but their effect is mitigated by the 50 Hz component, as can be seen in Figure 5. Therefore, the impact of the harmonic on the junction temperature variation becomes negligible.

In conclusion, a designer should take into account the worst case in the design process when choosing the right devices. In this work, the worst case is presented in Figure 5, when the SAF converter provides harmonic compensation as well as a 50 Hz current. The devices are chosen to handle a more than 100 A peak. In the case of no power injection (Figure 4), the transistors are then oversized, and no overheating or excessive thermal cycling is of concern.

5. Efficiency Comparison Between IGBT and SiC MOSFET

The numerical values are computed and compared to a PLECS simulation in Section 5.

The PLECS schematic used for the simulation is available in Figure 8. The blue rectangle represents the thermal heatsink of the system. It has been verified that the temperature remains between 25 °C and 100 °C according to the different thermal resistances taken into account in the simulation. IGBTs and diodes are modelled in PLECS with data from their manufacturer. Some data examples are provided in Figure 9 for IGBT IKQ50N120CH3. Static and switching energies are given for different temperatures, voltages, and currents. Static characteristics are used to compute conduction losses, while switching energies give the switching losses. The junction temperature of each device depends on the losses of each device, on the ambient temperature, and on the heatsink characteristics. Probes are added to directly measure the instantaneous conduction and switching losses. An average operator is added to obtain the mean value during a grid period.

This framework takes into account many more phenomena than those modelled, such as the variation in junction temperature of components as a function of losses, which influences the static and dynamic characteristics of switches, the impact of dead times, gate resistance, reverse conduction in MOSFETs, non-linearities in characteristics, or thermal impedance with the external environment.

Consequently, as experimental measurements cannot isolate each contribution (conduction, switching, transistor, and diode), the developed models will only be validated with the PLECS framework, which includes data from real measurements carried out by the manufacturer.

In the case of only harmonics compensation, the analytical and simulation results are given in

Table 2. Power losses comparison of SiC-MOSFET and IGBT for the harmonic filtering case.

Parameter	Model	Simulation	Error [%]
SAF current	15.8 A	15.9 A	0.3
RMS current in transistor + diode	11.1 A	11.1 A	0.1
RMS current in transistor	8.38 A	8.27 A	1.3
Average current in transistor	3.59 A	3.81 A	5.8
RMS current in diode	7.32 A	7.48 A	2.1
Average current in diode	2.35 A	3.00 A	22
Diode conduction losses	3.22 W	3.61 W	11
Diode recovery losses	neglected	neglected	-
MOSFET solution at 100 kHz
MOSFET conduction losses	2.11 W	2.22 W	5.0
MOSFET switching losses	21.0 W	19.8 W	6.0
MOSFET total losses	23.1 W	22.0 W	5.0
Converter losses	158 W	154 W	2.5
MOSFET solution at 16 kHz
MOSFET conduction losses	1.53 W	1.60 W	5.0
MOSFET switching losses	3.43 W	3.59 W	4.5
MOSFET total losses	4.96 W	5.19 W	4.4
Converter losses	48.2 W	51.8 W	6.9
IGBT solution at 16 kHz
IGBT conduction losses	5.10 W	4.51 W	13
IGBT switching losses	26.3 W	25.2 W	4.3
IGBT total losses	31.4 W	29.7 W	5.7
Converter losses	207 W	200 W	3.5

. The IGBT and MOSFET solutions are compared for switching frequencies of 16 kHz and 100 kHz. The IGBT solution at 100 kHz is not considered because it is too inefficient. In fact, IGBTs are not meant to handle such high switching frequencies, generating too much switching loss and overheating the transistor. Converter efficiency is not displayed in this case as no power is transferred, only harmonics are injected. Therefore, the notion of efficiency is meaningless.

The error between the developed models and the simulation measurements, considering real components, is almost always under 7%. The only significant difference comes from the evaluation of the average current in the diode because of the difference in current waveforms depicted in Figure 4 and because the non-linear behaviour of the diode is simplified in the model. Then, as the overall computed losses are close to the measured losses, the developed models are validated in this case.

In term of analysis, the losses from the VSI-SiC are unsurprisingly lower than those from the C-VSI [20,21,22] at 16 kHz as well as 100 kHz for two reasons. First, the SiC MOSFET consists of wide band gap transistors that exhibit significantly lower switching energies compared to IGBT transistors. Second, as the switched current is very low compared to the current calibre of the transistors, the forward voltage drop from the IGBT has a strong impact.

In the case of compensation with power injection, the results are given in

Table 3. Power loss comparison of SiC-MOSFET and IGBT for the power generation case.

Parameter	Model	Simulation	Error [%]
SAF current	72.2 A	72.1 A	0.1
RMS current in transistor + diode	50.3 A	51.2 A	1.8
RMS current in transistor	46.0 A	46.2 A	0.4
Average current in transistor	25.8 A	26.1 A	1.1
RMS current in diode	20.5 A	22.2 A	7.7
Average current in diode	6.05 A	7.20 A	16
Diode conduction losses	13.6 W	13.8 W	14
Diode recovery losses	neglected	Neglected	-
MOSFET solution at 100 kHz
MOSFET conduction losses	75.6 W	77.7 W	2.7
MOSFET switching losses	135 W	133 W	1.5
MOSFET total losses	211 W	211 W	0.1
Converter losses	1339 W	1347 W	0.6
Efficiency	97.1%	97.1%	-
MOSFET solution at 16 kHz
MOSFET conduction losses	63.5 W	62.7 W	1.3
MOSFET switching losses	21.6 W	18.0 W	20
MOSFET total losses	85.1 W	80.7 W	5.4
Converter losses	587 W	570 W	3.0
Efficiency	98.7%	98.8%	-
IGBT solution at 16 kHz
IGBT conduction losses	78.7	76.2	3.3
IGBT switching losses	165	166	0.6
IGBT total losses	244	242	0.8
Converter losses	1539	1537	0.1
Efficiency	96.6%	96.6%	-

.

The efficiency is computed with Equation (17), thanks to the converter losses calculated or measured by PLECS.

$$efficiency={\displaystyle \frac{P_{\mathrm{O}\mathrm{U}\mathrm{T} \mathrm{S}\mathrm{A}\mathrm{F}}}{P_{\mathrm{O}\mathrm{U}\mathrm{T} \mathrm{S}\mathrm{A}\mathrm{F}}+\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{v}\mathrm{e}\mathrm{r}\mathrm{t}\mathrm{e}\mathrm{r} \mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}\mathrm{e}\mathrm{s}}}$$

(17)

The difference in conduction losses between 16 kHz and 100 kHz comes from the difference in junction temperature induced by the switching losses, not taken into account in the model, which increases the value of R_{DS ON}.

The SiC MOSFET solution is unsurprisingly better in terms of efficiency for 16 kHz, and even at 100 kHz, as observed in [20,21,22], which deal with only fundamental current injections without harmonic filtering. The 100 kHz solution makes it possible to drastically decrease the size, cost, and losses of the choke inductance/output filter.

6. Efficiency Comparison for Different DC Voltages

Increasing the DC voltage is a conventional solution in order to increase, among other things, the overall SAF dynamics and consequently harmonic filtering. Thus, different DC voltage scenarios are imagined in this section. As the DC voltage increases, the voltage rating of the transistor is adapted. A conventional rule considers that the voltage rating should be higher than 1.5 times the DC voltage, for reliability reasons. Then, a new MOSFET reference has to be used: the C2M0045170P with a voltage rating of 1700 V; a current rating of 48 A at 100 °C; and a unit price three times higher than previously, USD 90. The different cases are as follows:

• Vdc = 800 V, with MOSFET SiC 1200 V rating (reference case);
• Vdc = 1000 V, with MOSFET SiC 1700 V rating;
• Vdc = 1200 V, with MOSFET SiC 1700 V rating.

The converter efficiency is computed in

Table 4. SiC-MOSFET power loss calculations under different DC voltages for the harmonic filtering case.

Parameter	Model	Simulation	Error [%]
800 Vdc solution
MOSFET conduction losses	2.11 W	2.22 W	5.0
MOSFET switching losses	21.0 W	19.8 W	6.0
MOSFET total losses	23.1 W	22.0 W	5.0
converter losses	158 W	154 W	2.5
1000 Vdc solution
MOSFET conduction losses	2.91 W	2.62 W	11
MOSFET switching losses	27.2 W	28.7 W	5.2
MOSFET total losses	30.1 W	31.3 W	3.8
Converter losses	204 W	211 W	3.1
1200 Vdc solution
MOSFET conduction losses	2.85 W	2.54 W	13
MOSFET switching losses	32.9 W	34.1 W	3.5
MOSFET total losses	35.8 W	36.6 W	2.2
Converter losses	239 W	243 W	1.7

and

Table 5. SiC-MOSFET power loss calculations under different DC voltages for the generation case.

Parameter	Model	Simulation	Error [%]
800 Vdc solution
MOSFET conduction losses	75.6 W	77.7 W	2.7
MOSFET switching losses	135 W	133 W	1.5
MOSFET total losses	211 W	211 W	0.1
Converter losses	1339 W	1347 W	0.6
Efficiency	97.1%	97.1%	-
1000 Vdc solution
MOSFET conduction losses	146 W	142 W	2.8
MOSFET switching losses	116 W	120 W	3.3
MOSFET total losses	262 W	262 W	0.0
Converter losses	1.66 kW	1.66 kW	0.0
Efficiency	96.3%	96.3%	-
1200 Vdc solution
MOSFET conduction losses	138 W	137 W	0.7
MOSFET switching losses	139 W	146 W	4.8
MOSFET total losses	277 W	283 W	2.1
Converter losses	1.75 kW	1.79 kW	2.2
Efficiency	96.2%	96.1%	-

for different DC voltages (800 V, 1000 V, and 1200 V), with and without power injection.

The results reveal that efficiency decreases when the DC voltage increases. The first explanation is that increasing the voltage above 800 V forces the designer to use 1700 V components, which have worse properties in addition to an extra cost. The second explanation is based on the switching loss increase, proportional to the DC voltage.

7. Conclusions

A new method for calculating losses and efficiency is developed in this article in the specific case of SAFs. Two cases are developed: the classic case of harmonic compensation of a non-linear load, and the case where power is injected in addition to harmonics. The method developed is the same in both cases, only the integral limits are modified. The models are applicable for any type of switch, in particular MOSFET and IGBT. The point-by-point comparison with manufacturer data allows the developed models to be validated and the limits and points for improvement to be discussed.

The results obtained allow a designer to quickly compare different ranges of components for the design of their SAF. Very few other analytical studies of the state of the art allows for this comparison yet is crucial as we know that energy efficiency represents a real challenge in the design of SAFs.