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Journal: Electronics, 2024
Volume: 13
Number: 1284

Article: Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model
Authors: by Yihe Yu, Wanyuan Pan, Chengcheng Tang, Ningyuan Yin and Zhiyi Yu
Link: https://www.mdpi.com/2079-9292/13/7/1284

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