A 0.59 nW/kHz Clock Circuit with High-Precision Clock Calibration for Passive Internet of Things Chips

Abstract

The high precision and low power consumption of the clock generator are critical in passive RFID transponders and passive IoT chips, but fluctuations in PVT can cause considerable degradation in the precision of the chip’s internal clocks. This paper proposes a high-precision clock circuit with a single-shot calibration method to addresses this issue in a low-power clock solution. Based on the reference timespan in the preamble of the down-link RF envelope, a TDIF (Time-digital to current-frequency) calibration method was implemented with both a streamlined procedure and customized circuits. By computing the difference between the time counts and applying it to an ultra-low-power, current-starved oscillator, the current change ratio can be linearly controlled. Compared to the traditional integer frequency division scheme used by passive tags for a 160 k bits up-link data rate, the required frequency for the clock generator was reduced from 960 kHz to 320 kHz, the calibration error was reduced from ±10% to ±3% for ±25% frequency deviation, the calibration time was 133.3 μs for a single shot in this work, and the power consumption was 158 nW after the calibration was completed. This leads to an excellent power efficiency of 0.59 nW/kHz and meets the requirements of low power, low cost, and PVT robustness in the RF-powered passive IoT chips. By appropriately increasing the number of calibration digits and the duration, this calibration approach could also be used for other ultra-low-power passive IoT chips that require higher-precision clocking without the use of off-chip crystals.

1. Introduction

With the continuous development of Internet of Things (IoT) technology, battery-less, crystal-less, passive IoT technology has increasingly become a research focus due to its unique advantages of low power consumption, a low cost, and PVT robustness in RF-powered passive IoT chips [1,2,3,4]. The clock generator is a crucial component in the signal front-end for passive IoT chips. It is responsible for decoding the downlink data, encoding the uplink data, and clocking the command handler in the baseband processor [5,6]. The design of the clock generator poses a significant challenge due to the stringent frequency accuracy requirements that are necessary for the uplink data in the protocol. The accuracy of the clock signal is critical to the overall proper operation of the chip, as shown in Figure 1. However, on-chip clock generators are susceptible to manufacturing process variations and ambient temperature variations, especially under low-power design constraints [7,8,9,10], resulting in relatively large deviations in clock frequency. The current solution is to increase the communication rate’s tolerance through communication system protocol design, at the cost of a reduced communication performance. Another alternative is to use a high-precision off-chip clock source such as a crystal [11,12,13,14]. Therefore, a simple and effective method to improve the accuracy of the internal clock while maintaining low power consumption and eliminating the need for an external reference crystal has become the focus of current research on passive IoT devices [15,16,17]. Passive UHF RFID transponders generate their clock using an on-chip oscillator, eliminating the need for an external crystal [18,19]. However, the method of digital automatic frequency division results in a higher oscillator frequency and, consequently, a higher power consumption.

To overcome the problem of significant frequency deviations in the internal clock, some scholars have proposed a process deviation detection method to realize frequency calibration [20], which is based on the linear relationship between the process deviation and the device subthreshold leakage, and generates a control voltage feedback to control the oscillation frequency of the clock generator by detecting the device’s subthreshold leakage. However, the improved clock structure has low reliability, low accuracy, and high power consumption. Other researchers have proposed a calibration method based on successive approximation to calibrate the oscillator multiple times [21]. This is achieved by using multi-precision time intervals as a reference to manage the magnitude of charge and discharge currents. However, this solution requires the use of an additional off-chip reference, although it achieves superior clock accuracy. All of the above methods struggle to simultaneously satisfy the applications in the field of passive IoT applications with low power consumption, high precision, and good integration.

This paper proposes a method to calibrate the on-chip clock using demodulation commands that are compatible with the ISO/IEC 18000-6C protocol [22]. This method compensates for the effects of PVT variations on the clock during downlink communication without requiring additional time intervals. Furthermore, no additional pins are required for the calibration process. At the same time, the approach has the advantages of low power consumption, high accuracy, and high integration, and does not require any external reference.

2. Traditional Methods

In conventional passive UHF RFID, digital automatic frequency division is commonly used for clock calibration. By adjusting the frequency division factor, the clock can meet system requirements even when the main clock deviates. However, to ensure that the frequency deviation range includes process deviation, a higher main clock frequency is usually required. This results in increased power consumption. The backscatter-link frequency $f_{BLF}=DR/TRcal$, where DR is the link frequency division ratio, has a fix value of 64/3 for the 160 kHz uplink data rate. A transponder measures the length of the TRcal, calculates the BLF, and adjusts its tag to reader link rate to equal $f_{BLF}$.

For the uplink data rate at the frequency $f_{BLF}$, the RFID protocol requires a clock accuracy of ±α with a process deviation of ±β. Here, we assume that the maximum value of β is 25% and α is no more than 10% for the 160 kHz uplink data rate. For the conventional clock calibration scheme in RFID transponders, the length of TRcal in the downlink command is counted with the on-chip oscillator, and the division factor (DF) is generated to achieve the automatic frequency division of the $f_{OSC}$ into $f_{BLF}$, which ensures that the accuracy of $f_{BLF}$ meets the required standards [23].

$$N=TRcal\times f_{OSC}$$

(1)

$$f_{BLF}=\frac{DR}{TRcal}=DR\times \frac{f_{OSC}}{N}=\frac{f_{OSC}}{DF}$$

(2)

where $DF=N/DR$; $N$ is the counting results.

Although the fractional frequency division improves the precision, it increases the power consumption and circuit complexity. Traditional RFID systems, therefore, use integer frequency division to avoid these problems.

To achieve ±α accuracy, the division factor (DF) of the oscillator must satisfy the following formula to ensure continuous coverage of the frequency:

$$f_{BLF}\times (1+\alpha )\times DF\ge f_{BLF}\times (1-\alpha )\times (DF+1)$$

(3)

Formula (3) can be used to derive the following formula:

$$DF\ge 0.5\times (\frac{1}{\alpha }-1)$$

(4)

In this passive RFID verification system, the backscatter link frequency is set to $f_{BLF}$ = 160 kHz and the required error is no more than ±10% [22]. Therefore, DF > 4.5, rounded to DF_min = 5. Assume that the maximum initial oscillator frequency deviation, before calibration, is ±25% due to PVT variations. Therefore,

$$f_{OSC}\times (1-\beta )\ge {DF}_{min}\times f_{BLF}\times (1-\alpha )$$

(5)

$$f_{OSC}\times (1-25\%)\ge {DF}_{min}\times 160 \mathrm{kHz}\times (1-\alpha )$$

(6)

$$f_{OSC}\ge 960 \mathrm{kHz}$$

(7)

Hence, a frequency of at least 960 kHz ensures a maximum negative deviation of −25% in the oscillator frequency. In addition, the self-tuning of the integer division factor DF controls the final deviation of $f_{BLF}$ within ±10%.

Figure 2 shows a simplified visualization of the theory analysis, where the white strip represents the disallowed frequency range beyond the ±10% deviations, the shallow green strip represents the frequency that allows one division ratio, and the dark green strip represents the frequency that allows two division ratios. When DF ≥ 5, the green strips are continuous, showing that the frequency f_OSC can meet the requirement of maximum ±10% deviation using different division ratios, so that the $f_{BLF}$ can meet the requirement of a maximum ±10% deviation by adjusting the division factor. However, frequency gaps occurred when DF ≤ 4, showing that the requirement of maximum ±10% deviation cannot be met by adjusting the division factor to cover all frequency scopes. Therefore, the minimum frequency that is required is 160 kHz × 5 = 720 kHz, and the minimum frequency required for designing the on-chip oscillator, taking into account the ±25% PVT deviation, is 960 kHz.

When a higher accuracy of $f_{BLF}$ is required in low-power passive IoT chips, the value of DF increases, as shown in Formula (4). Therefore, the required oscillator frequency also rapidly increases. Since the frequency has an approximately linear relationship with the power consumption, the maximum frequency is limited by the low power consumption of the passive chip, and so is the calibration accuracy in the division factor adjustment approach.

3. Proposed Design

3.1. TDIF Single-Shot Calibration Method

The use of digital automatic frequency division may not be the optimal choice due to its requirement for higher-frequency clocks, which leads to increased power consumption. Therefore, calibrating the original clock generator, which can significantly reduce the high-frequency demand without dividing the original frequency, provides the possibility of lower power consumption.

Conventional clock calibration methods, such as SAR calibration, automatically adjust the oscillator parameters (such as capacitance, current, and bias voltage) to approximate the standard time duration [24,25]. This is achieved by quantizing the same input reference time length or signal reference multiple times, and then processing the results using a complex digital circuit module to realize the calibration as an SAR procedure in some ADCs. Although this method can improve the clock’s accuracy, it also increases the circuit complexity and power consumption, making it unsuitable for passive RFID and passive IoT transponders. Furthermore, the multiple quantization results in a somewhat long calibration time.

In this paper, a fully linearised TDIF single-shot calibration is proposed. “T” refers to the standard duration, such as TRcal. “D” refers to the quantized value of the oscillation frequency compared to the standard duration, which is affected by the PVT deviation. “I” refers to the tuning current, corresponding to the results of the quantization, and “F” refers to the frequency of the oscillator controlled by the tuning current. Firstly, the method starts by obtaining T₀→D₀, using TRcal as the reference time length and then linearly quantizing it with the frequency of an on-chip oscillator. The resulting difference is δD, which refers to the positive or negative offset value. Next, the offset value is then linearly mapped to the tuning current array to obtain δD→δI. Finally, the frequency is adjusted by changing the current of the linear oscillator to achieve δI→δf. The method allows a fast calibration in a single shot, achieving a calibration of the frequency deviation ranging from a maximum of ±25% under the influence of PVT to within ±3%, with low power consumption and high speed.

The three sets of parameters, δf and δD, δD and δI, and δI and δf, are linearly related. A compensation calibration was carried out based on the circuit synchronization calculations. The circuit has the advantage of performing the offset calculation and calibration synchronously. The whole calibration system shows a linear relationship between the parameter changes. The implementation procedure requires an emphasis on the efficient design and implementation of the calibration circuit, including the following aspects: (1) the offset generation methods and implemented circuits; (2) the mapping methods of the tuning currents; (3) the low-power implementation of the linear oscillator.

The calibration system uses the linear relationships δN = T₀×δf and δf = δI/CV to determine the frequency corresponding to the unit quantization value ${\delta f}_{OSC}$, which is the first key parameter to be determined. Thus:

$${\delta f}_{OSC}=\frac{1}{T_0}=7.5 \mathrm{k}\mathrm{H}\mathrm{z}$$

(8)

A clock frequency of 320 kHz is used to generate the 50% duty cycle of 160 kHz $f_{BLF}$. The maximum error of T₀→D₀ in the quantization is 1/TRcal, due to a rounding error. The theoretical value of calibration accuracy is calculated by dividing the single-bit calibration amount by the total amount, and dividing the frequency corresponding to the single-bit calibration current by the oscillator frequency. Thus:

$$e=\frac{{\delta f}_{OSC}}{320k}\times 100\%=\pm 2.3\%$$

(9)

For a TRcal length of 133.3 us, the frequency shift corresponding to one unit bit of current is approximately 7.5 kHz, resulting in a calibration accuracy of approximately ±2.3%.

3.2. Circuits Scheme of Clock Generator

The block diagram of the proposed the clock calibration circuit is shown in Figure 3. The clock calibration circuit consists of a calibration module for frequency offset linear quantization, a current array, and an oscillator. At the start of passive communication, the on-chip oscillator generates an initial frequency, f_OSC, which is influenced by the PVT variation. The logic calibration circuit counts and quantizes the TRcal and converts it to a binary value, D₀. This value is then compared with the preset values K₁ and K₂ to obtain δD. The current array converts δD to the corresponding value of the tuning current δI. The oscillator is driven by δI to generate the oscillation frequency ±δf, which is then superimposed on the initial oscillation frequency to provide the final oscillation frequency as f_OSC ± δf. The TRcal is demodulated from the preamble in the communication frame and converted by logic circuits into a 133.3 μs enable signal. From the generation of the TRcal to the minimum adjustable δf, all of the controls and conversions are performed simultaneously, allowing the clock signal to be accurately calibrated to 320 kHz in one shot.

4. Circuit Implementation

4.1. Collaborative Design of Clock Oscillator and Current Array

Figure 4 shows a linear oscillator circuit that generates oscillations through charging and discharging capacitor C. The inverter is connected to the output of the RS flip-flop, which changes the output state of the inverter to ensure the continuous oscillation of the clock circuit. This provides a clock output signal with a frequency given by Formula (10), where V₀ is the flip-flop threshold of the RS flip-flop. The structure is compatible with the CMOS process and has several advantages, including good output waveforms, a low cost, a small area, and the ability to self-start. The oscillator also has favorable temperature characteristics, as no resistor is added. However, the output frequency is significantly affected by the manufacturing process and supply voltage variations. During the rising edge of TRcal, the switches S are set to 0 and switches F are set to 1 through the logic control of the previous stage. This results in the output frequency of the clock oscillator being at a certain intermediate frequency. To ensure accurate calibration, Formula (11) must be satisfied between the pre-calibration clock frequency value, f₁, the target frequency value, f₀, and the current value to be adjusted, δI.

$$f_{osc}=\frac{I_0}{2C_0{V}_0}$$

(10)

$$f_1-f_0=\frac{\delta I}{2C_0{V}_0}$$

(11)

According to Formula (11), δI can be either positive or negative. When δI is positive and the clock frequency is higher than the target value, it is necessary to turn off part of the S logic control array to reduce the charge and discharge currents, thereby reducing δI and ultimately achieving the target frequency f₀. If δI is negative, the switching frequency is lower than the target value. In this case, it is necessary to activate part of the F logic control array to increase the charge and discharge currents by δI and eventually increase the clock frequency to the target frequency f₀. When δI is 0, the clock frequency is around the target frequency and the state of the logic control array remains unchanged.

4.2. Calibration Module

The structure of the logic calibration circuit is shown in Figure 5a. The conversion of the TRcal timespan to the counter value D₀ is handled by counter 1, and two 6-bit binary integers, K₁ and K₂, K₁ < K₂, are introduced to compute the difference between the current counter results and the target value, referred to as δD. Two latches form the value judgement switches to enable counter 2 and counter 3, quantizing the difference between D₀ and K₁ and D₀ and K₂, which is then mapped to switch K₁ and switch K₂. The initial settings of F_0~4 = 11111 and S_0~4 = 00000 are realized by the AND2 and OR3 logic gates while the TRcal signal is enabled. Additionally, they delay the change in S and F to avoid the immediate change from occurring in δD→δI→δf during the calibration process. This change in the oscillator’s frequency during the calibration process will cause the calibration to fail. In addition, the OR3 gates in the additive array also take on the role of holding F_0~4 = 11111 while the subtractive array is enabled. The target clock frequency is 320 kHz, so K₁ and K₂ can be calculated by combining Formulas (12) and (13), as shown below.

$$\frac{K_2}{133.3\mathsf{\mu }\mathrm{s}}=320 \mathrm{kHz}$$

(12)

K₂ is an integer, so the corrected value is 43. To ensure the continuation of the 5-bit logic control array, the following is obtained:

$$K_1=K_2-2^5$$

(13)

The calibration sequence is shown in Figure 5b. After resetting the circuit on power-up, the passive transponder chip receives the TRcal preamble, the logic gate sets the switch F0~4 to 11111, turning off the addition current mirror array, and the switch S0~4 is set to 00000, turning on the subtraction current mirror array shown in Figure 4. During the effective time period of TRcal, counter 1 starts with the real-time counting of the current oscillator clock cycles D₀ and generates the switch to enable signals K₁ and K₂. At the end of the TRcal timespan, if D₀ ≤ K₁, this indicates that the oscillator’s initial frequency is below the lower limit of the frequency calibration range. If K₁ < D₀ < K₂, this indicates that the clock frequency is slower than the target frequency, and the K₁ switch then enables counter 2 to count the clock cycles in real time. The count result is δD, which is equal to D₀-K₁, and the circuit outputs a 5-bit logic control array. The added number of current mirror units is 25-δD, which is used to increase the output current of the current mirror array and increase the frequency to the target. When D₀ ≥ K₂, switch K₂ is turned on and immediately resets F0~4 = 11111. The K₂ switch enables counter 3 to count the clock cycles in real time. δD is generated, which, here, is equal to D₀-K₂. The circuit outputs a 5-bit logic control array. The reduced number of current mirror units is δD, which is used to reduce the output current of the current mirror array and ultimately reduce the frequency to the target.

In the circuit design, the frequency step corresponding to the 1-bit control current in the logic control array is not constant at different process corners. This inconsistency can easily cause the calibrated clock frequency to become dispersed under different process corners. This paper combines the clock calibration and process corner for a comprehensive simulation. It compares and analyses the effect of clock calibration under different process corners. The proportional magnitude of I₀, I_S, and I_F in the clock oscillator is then adjusted. This allows for the 1-bit control current values of the logic control arrays at different process corners to go through a calibration process to keep the clock frequency values within the allowed tolerance for the target frequency.

The clock calibration process is performed at the beginning of each communication between the reader and the node chips of passive IoTs, and the effect of PVT fluctuations on the accuracy of the calibrated clock frequency is offset in the leading calibration of the one-shot process. Compared to traditional calibration schemes, this has the advantages of integration, a low cost, and an increased calibration speed.

5. Simulation and Test Result

5.1. Simulation Result

This paper presents the design and simulation of a clock calibration circuit using Cadence Virtuoso IC617 software and based on the TSMC 0.18 μm CMOS process. Figure 6a,b show the simulation results of the clock calibration circuit at different temperatures and operating voltages. It is clear that the frequency deviation before calibration was significant. However, after calibration, the frequency deviation was within 3% over a temperature range of −40–120 °C and an operating voltage range of 0.7–1.5 V. Figure 6c shows the simulation results of the entire clock calibration circuit under different process corners. The frequency is at its highest before TRcal occurs, as all current mirror arrays are activated before the rising edge of TRcal. When TRcal occurs, F₀-F₄ in the additional current mirror arrays are deactivated and the frequency returns to normal, although there is still a deviation of about ±25% at different process corners, and the calibration circuits start working on the rising edge of TRcal. At the end of the TRcal duration, the clock frequency is set to approximately 320 kHz. The frequency range of the clock circuit is between 315.6 kHz and 323.5 kHz, with a frequency calibration error of less than ±3%. Figure 6d shows the linearity of the oscillator frequency with the bias current at the TT corner. The red curve represents the variation of frequency with current, while the blue curve represents its slope. It can be seen that the slope of the curve changes very little, satisfying the oscillator linearity requirements of this design. Figure 6e shows the power consumption simulation of the clock circuit operating at 0.7 V voltage at the TT process corner. The pre-calibration power consumption is 270 nW. During calibration, it is 220 nW. After calibration, the average power consumption of the circuit is 158 nW, with an energy-efficiency ratio of 0.59 nW/kHz. The power consumption of the clock calibration circuit is only higher before the clock calibration is completed. For the normal working time after the clock calibration, the power consumption of the whole circuit remains at a low level, meeting the design requirement of low power consumption for the passive transponder or node chip.

5.2. Test Result

The circuit was fabricated using TSMC’s 0.18 μm CMOS process. The micrograph of the passive RFID transponder chip is shown in Figure 7, integrated with the clock generation and calibration modules. The entire clock module layout had the dimensions of 114 μm × 112.5 μm. The core of the chip was powered by RF energy from the reader, and a Keithley 2410 source meter powered all of the chip’s test PADs in order to separate the power load of the test PAD I/O buffers used to drive the oscilloscope.

The measured output waveforms of the clock module are shown in Figure 8. Prior to the preamble from the reader, the clock circuit was not calibrated and the frequency was 646.2 kHz with F_0~4 = 00000&S_0~4 = 00000. During calibration, the clock frequency dropped to 337.4 kHz with F_0~4 = 11111&S_0~4 = 00000, showing a frequency deviation of +5.4% for these lots, and at the end of calibration, the calibrated output value was F_0~4 = 11111& S_0~4 = 00010, reaching 321.1 kHz with a frequency calibration error of less than +0.34%. Therefore, the test results agreed with the simulation data. The total calibration time was only 133.3 μs, equal to the length of TRcal. The low-power clock module was integrated into a passive RFID transponder chip and met the timing and accuracy requirements of the ISO/IEC18000-6c protocol, enabling the transponder to communicate with the reader.

The clock circuit was tested at different temperatures and supply voltages, and the statistical results are shown in Figure 9. Figure 9a shows the test results of the clock calibration circuit at different temperatures, and Figure 9b shows the test results of the clock calibration circuit at different supply voltages. The oscillator is minimally affected by temperature, but significantly affected by power supply voltage. After calibrating with the TDIF calibration circuit, the frequency is close to 320 kHz, and the error is no more than 3%.

Table 1. Performance summary and comparison with other papers.

Reference	[20]	[21]	[26]	[27]	This Work
Process (nm)	180	180	180	180	180
Operating voltage (V)	1.8	0.7–1.2	1.8	0.7	0.7–1.6
Frequency	2.02 MHz	32.7 kHz	32.55 kHz	320 kHz	320 kHz
Temperature range	-	−20 °C~100 °C	-	−50 °C~120 °C	−40 °C~120 °C
Precision	±2.81%	±1.525%	-	±4%	±3%
Power consumption	12 μW	54 nW@0.7 V	472 nW	360 nW@0.7 V	158 nW@0.7 V
Energy efficiency (nW/kHz)	5.9	1.65	8.1	1.125	0.59

shows a performance comparison between the proposed circuit and previous works on clock generation and calibration. The energy-efficiency of the clock is provided in the comparison table to show the advantage of the current approach, which is defined as follows:

$$Energy efficiency=\frac{P}{f}$$

(14)

where P and f are the power consumption and the frequency after calibration, respectively.

6. Conclusions

This paper proposes the use of a high-precision clock circuit with single-shot calibration method for passive RFID transponders and passive IOT chips. It exhibits an excellent energy-efficiency ratio of 0.59 nW/kHz, while meeting the requirements of a small chip area, high precision, and PVT robustness in the passive IoT transponder applications. The measurement results show that the clock calibration process takes 133 μs from start to finish, with a single shot calibration to 320 kHz implemented in passive RFID with the ISO 18000-6c protocol. The calibrated clock has a frequency accuracy within ±3% and an energy-efficiency ratio of 0.59 nW/kHz, and occupies an area of only 114 μm × 112.5 μm. This calibration method can achieve higher accuracy at the cost of calibration time and bits while maintaining a low power consumption and high PVT robustness, and can be used in other passive IoT scenarios, such as passive BLE transponder chips.