# A New Zero-Voltage Zero-Current Switching Converter with Minimum Duty Cycle Loss

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Circuits and Operation Principles

#### 2.1. Circuit Configuration

_{in}represents the input capacitor, with Q

_{1}and Q

_{2}forming the leading legs and Q

_{3}and Q

_{4}constituting the lagging legs. C

_{1}and C

_{2}denote the parasite capacitors associated with Q

_{1}and Q

_{2}. The body diodes of Q

_{1}–Q

_{4}are represented by D

_{1}–D

_{4}. The primary current of the main circuit is denoted as i

_{p}, and v

_{p}signifies the primary voltage. T

_{1}, the main transformer, possesses a turns ratio denoted as k

_{T1}. The auxiliary circuit comprises Q

_{S1}~Q

_{S4}and T

_{2}, where T

_{2}, the reset transformer, is characterized by a turns ratio of k

_{T2}. Q

_{S1}–Q

_{S4}collectively form the auxiliary bridges, and D

_{S1}–D

_{S4}represent their respective body diodes. C

_{S1}–C

_{S4}are the body capacitors. The primary voltage of T

_{2}is labeled as vres’, while vres designates the secondary side voltage of the reset transformer. L

_{lk}stands for the leakage inductance of T

_{1}, and L

_{o}represents the output inductor. To streamline the illustration, only pertinent portions of parasitic capacitances and diodes are featured in the figures. D

_{O1}and D

_{O2}signify the rectifier diodes.

_{1}and T

_{2}are ideal transformers with a specified turns ratio. The leakage inductance is constant. The magnetizing current of T

_{1}and T

_{2}is low enough to ignore. The parasitic components of Q

_{1}, Q

_{2}, Q

_{3}, and Q

_{4}are of the same value, and i

_{Lo}in this circuit can be regarded as a constant current source.

_{S1}to Q

_{S4}. These modes are named the normal mode and duty cycle enhanced mode. Figure 2 shows the core waveform of the steady state in the duty cycle enhanced mode, and the waveform of the normal mode is depicted in Figure 3. Figure 4 shows the equivalent circuits during the first half-switching cycle in each mode. Figure 4a–g represent the stages in the normal mode over one half-switching period, and Figure 4a–i give the stages in the duty cycle enhanced mode. In each mode, the operation procedure can be divided into two half periods over one switching cycle, and only one half period is analyzed for simplicity.

#### 2.2. Normal Mode

_{res}, and the ZCS of the lagging-leg switches can be guaranteed.

_{0}): Before t

_{0}, Q

_{1}, and Q

_{4}are on, T

_{1}transfers power from the primary side to the secondary side and the load. Q

_{S2}and Q

_{S4}are also on, the secondary side of T

_{2}free-wheels the primary current, and v

_{res}is zero.

_{p}is decided by i

_{o}. This stage ends when Q

_{1}turns off.

_{0}–t

_{1}): At t

_{0}, Q

_{1}turns off with ZVS due to C

_{1}. Then, C

_{1}charges and C

_{2}discharges during this stage. At the end of this stage, the voltage of C

_{2}returns to zero and the voltage of C

_{1}becomes V

_{in}. The charge and discharge of C

_{1}and C

_{2}are due to the high value of L

_{o}. This mode finishes when the voltage of Q

_{2}is zero. In this mode, v

_{p}decreases with the following rate:

_{1}–t

_{2}): In this stage, the voltage of Q

_{2}is zero and the circuit is still on with the help of the body diode. i

_{p}flows through D

_{2}and Q

_{4}, and the primary circuit turns into the free-wheeling mode. i

_{p}and i

_{T2}stay unchanged.

_{2}–t

_{3}): i

_{p}is resetting in this stage, and Q

_{4}, D

_{S3}, and Q

_{2}are on. At t

_{2}, Q

_{2}is on with ZVS, and Q

_{S4}is off simultaneously. Because of C

_{S4}, the voltage of Q

_{S4}cannot change sharply, and the switching-off loss is low. A partial current of Q

_{S4}turns to D

_{S3}.

_{res}is applied to L

_{lk}, and i

_{p}decreases linearly. When i

_{p}is lower than I

_{o}k

_{T}

_{1}, I

_{Lo}goes through D

_{O1}and D

_{O2}, and the secondary side is shorted.

_{p}can reset fast, entering the free-wheeling periods, and as shown in Figure 2, the circulating current can also decrease and is much lower than that of the conventional PSFB converter. In addition, Q

_{3}and Q

_{4}obtain a wide load range of ZVZCS.

_{3}–t

_{4}): At t

_{3}, when i

_{p}is zero, the current of the auxiliary circuit also decreases to zero. The body diode of Q

_{S3}turns off and the reset voltage v

_{res}becomes zero.

_{4}–t

_{5}): During the last stage, the current of the primary side is zero. Q

_{4}turns off with ZCS at t

_{4}.

_{5}–t

_{7}): Because L

_{lk}limits the varying rating of i

_{p}, Q

_{3}realizes a quasi-ZCS turning on at t

_{7}.

#### 2.3. Duty Cycle Enhanced Mode

_{5}–t

_{6}): Q

_{S3}turns on at t

_{7}and the current of the primary side i

_{p}flows through Q

_{2}and Q

_{4}and starts to increase in the opposite direction. The reset voltage overlays with v

_{p}, thus accelerating the reverse growth of i

_{p}, and the transformation of power can restart quickly. Because of the reduction in time of the freewheeling of the secondary side, the duty cycle loss can be largely reduced.

_{6}–t

_{7}): Q

_{3}is on at t

_{6}, and Q

_{S3}is off. The primary side transfers power to the load, and D

_{o1}is off because of the reverse voltage. Current in the auxiliary circuit flows through Q

_{S3}and D

_{S4}, and v

_{res}is zero. After t

_{7}, the circuit works in the next half stage.

## 3. Performance Analysis and Comparison

#### 3.1. Duty Cycle Loss

_{p}cannot change immediately owing to L

_{lk}. Details of the duty cycle compensation in the proposed converter are given in Figure 5. The duty cycle loss is

_{eff}is the actual value.

#### 3.2. Condition of Soft-Switching

#### 3.2.1. ZVZCS of Q_{1} to Q_{4}

_{1}and Q

_{2}ensure ZVS turning on over a wide load range. The condition of ZVS is

_{1}and Q

_{2}are turned off, C

_{1}and C

_{2}will restrain the rising speed of the voltage. Therefore, these switches operate with quasi ZVS turn-off.

_{3}and Q

_{4}can achieve ZCS because i

_{p}decreases to zero before they are off. The rising speed of i

_{p}is restrained by L

_{lk}and v

_{res}. The condition of ZCS is

_{res}appears only in the free-wheeling modes, and it does not place much electrical stress on the main components [17,18].

_{3}and Q

_{4}are on, these switches can realize quasi-ZCS since i

_{p}cannot change immediately.

#### 3.2.2. ZVZCS of Auxiliary Switches

_{S1}and Q

_{S3}are the same, and the situations of Q

_{S2}and Q

_{S4}are identical.

_{S1}and Q

_{S3}are off permanently. Q

_{S2}and Q

_{S4}turn off with quasi-ZVS and turn on with ZCS. Hence, the switching loss is very low. In the duty cycle enhanced mode, Q

_{S2}and Q

_{S4}turn off and on with quasi-ZVS. Q

_{S1}and Q

_{S3}are on with quasi-ZCS and off with quasi-ZVS. Therefore, the power of Q

_{S1}to Q

_{S4}is a little higher than that of the normal mode.

#### 3.3. Comparison

#### 3.3.1. Consideration

_{o}is 28 V, and P

_{o}is 10 or 100 kW. The value of L

_{lk}is 10 µH, and the duty cycle is 1.

#### 3.3.2. Performance Comparison

_{2}, which may be the only choice in high-power applications. Therefore, it is challenging to apply the proposed converter in high-power industrial applications.

_{o}reaches 50 kW, the duty cycle loss of the ZVS circuit is over 0.5 and the primary side will not have power transmission to the secondary side. When P

_{o}is higher than 40 kW, the ZVS converter cannot work normally and the duty cycle loss is beyond the reasonable range. When P

_{o}is higher than 90 kW, the conventional ZVZCS converters have the same situation.

_{lk}causes serious duty cycle loss under high-power and low-input-voltage conditions. Therefore, the turns ratio must be lowered to compensate for the duty cycle loss. However, in the proposed converter, the duty cycle loss can be effectively reduced with the help of the reset voltage v

_{res}provided by the auxiliary transformer. Thus, the turns ratio of T

_{1}in the proposed converter can be optimized, and the expected performance of the proposed converter is high.

_{pro}is the duty cycle loss of the proposed converter, ΔD

_{ZVZCS}is the duty cycle loss of the converter in Figure 6a, and ΔD

_{ZVS}is the duty loss in Figure 6b.

_{D}= 1.5 V and V

_{Lo}= 0.5 V are the voltage drops on the rectifier inductor. Furthemore, the turns ratios under 10 kW are

_{pro}is the turns ratio of T

_{1}in the proposed circuit, n

_{ZVZCS}is the turns ratio of the conventional ZVZCS PSFB converter in Figure 6a, and n

_{ZVS}is the turns ratio of the conventional ZVS PSFB converter in Figure 6b.

_{o}is under 50 kW, it is obvious that the ZVS converter loses more duty cycle than the conventional ZVZCS converter and the proposed converter. When P

_{o}is higher than 50 kW, the proposed converter has more advantages in duty cycle loss. As shown in Figure 8, this has a great influence on the optimization of the transformer. Compared with the conventional ZVZCS PSFB converter, the optimization of the turns ratio can reach 40%. Moreover, the decrease in the power loss of the primary side can be seen in Figure 9.

_{p}can break the power range limitation of the existing ZVZCS converters. Therefore, the proposed converter is well-suited to high-power applications.

## 4. Experiments’ Results

_{res}is 168 V after t

_{1}, and i

_{p}decreases. The circle with dashed lines is the reset time in Figure 10a. With the turns ratio of T2 changing, the circuit can have different reset voltages and can operate in good conditions when the load changes even in high-power applications, which means no existing power rating limitation. In Figure 10a, v

_{p}has a spike at the beginning of the power transfer stages, which can minimize the duty cycle loss. As the duty cycle enhanced mode is only used in the low-input-voltage mode, this spike does not increase the voltage rating of the rectifier diode. As shown in Figure 10h, there is no voltage spike in the normal mode.

_{1}and Q

_{2}is depicted in Figure 10b, and they can realize ZVS over a wide load range with the help of the output inductor. In this picture, D

_{1}conducts and v

_{Q1(CE)}reduces to zero before t

_{1}; then, v

_{Q1(GE)}reaches the threshold voltage at t

_{2}. Hence, Q

_{1}and Q

_{2}in the proposed circuit turn on with ZVS.

_{3}and Q

_{4}can realize ZCS over a wide load range because i

_{p}is decreased to zero at corresponding switching-off instants. At t

_{1}, when v

_{Q3(GE)}is about 15 V, i

_{Q3}reaches zero. At t

_{1}, v

_{Q3(GE)}is about −10 V, meaning that Q

_{3}is already off with ZCS. In Figure 10c, v

_{Q3}has a current spike at t

_{3}. Figure 4f,g give the equivalent circuits, and the mechanism of the spike is described as follows. In Figure 10f, v

_{Q3}= v

_{B}= v

_{A}= 0, and v

_{Q3}remains at zero in this stage. After Q

_{4}is on, the input voltage charges C

_{3}, which causes a current spike. The energy of the spike will be stored in C

_{o}and will be released at the next instant of switching on. Thus, the power loss is low.

_{2}can be seen in Figure 10d. v

_{res}only appears in the current reset mode and the duty cycle enhanced mode. The current of the secondary side is i

_{p}and that of the primary side of T

_{2}is i

_{p}/k

_{T}

_{2}. The integration of T

_{1}and T

_{2}may reduce the volume and may be investigated in future work.

_{2}uses six small transformers and each of them is 1:1.

## 5. Conclusions

- (1)
- The duty cycle loss can be reduced effectively, and the circuit can be optimized;
- (2)
- The primary switches can realize soft-switching over a wide load range and the additional power loss caused by the auxiliary circuit is low;
- (3)
- The ZVZCS operation has no power rating limitation;
- (4)
- The electrical stress of the components is much lower than that of the conventional ZVZCS PSFB converter.

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 4.**Operating circuits in the first half-switching period: (

**a**) Stage 1; (

**b**) Stage 2; (

**c**) Stage 3; (

**d**) Stage 4; (

**e**) Stage 5; (

**f**) Stage 6; (

**g**) Stage 7; (

**h**) Stage 8 of duty enhanced mode; (

**i**) Stage 9 of duty enhanced mode.

**Figure 6.**Conventional converter for comparison: (

**a**) conventional ZVS converter; (

**b**) conventional ZVZCS converter.

**Figure 7.**Comparison of duty cycle loss: (

**a**) duty cycle loss of ZVS, ZVZCS, and proposed converter (P

_{o}= 10 kW–50 kW); (

**b**) duty cycle loss of ZVZCS and proposed converter (P

_{o}= 60 kW–100 kW).

**Figure 8.**Variable turns ratio: (

**a**) ZVS, ZVZCS, and the proposed converter (P

_{o}= 10 kW–50 kW); (

**b**) ZVZCS and the proposed converter (P

_{o}= 60 kW–100 kW).

**Figure 9.**Comparison of conduction loss: (

**a**) ZVS, ZVZCS, and the proposed converter (P

_{o}= 10 kW–50 kW); (

**b**) ZVZCS and the proposed converter (P

_{o}= 60 kW–100 kW).

**Figure 10.**Experiments’ results: (

**a**) v

_{p}and i

_{p}; (

**b**) v

_{Q1(GE)}, v

_{Q1(CE)}, and i

_{Q1}; (

**c**) v

_{Q3(GE)}, v

_{Q3(CE)}, and i

_{Q3}; (

**d**) i

_{p}and v

_{res’}; (

**e**) v

_{res}, v

_{Do1}and i

_{Do1}, and i

_{Qs2}; (

**f**) v

_{Do1}, i

_{Do1}, v

_{Do2}, and i

_{Do2}; (

**g**) v

_{p}and v

_{Do1}; (

**h**) v

_{p}and v

_{Do1}in normal mode.

Item | Figure 6a | Figure 6b | Proposed Circuit |
---|---|---|---|

Number of components | 11 | 12 | 13 |

Conditions of soft-switching | Narrow range | Power rating limitation | Wide load range |

Duty cycle loss (40 kW) | 0.3 | 0.12 | 0.08 |

Conduction loss (40 kW) | 80 W | 60 W | 58 W |

Item | Parameter |
---|---|

Rated power | 2 kW |

Input | 400–600 V |

Rated output | 28 V/72 A |

Switching frequency | 20 kHz |

IGBTs | FF450R12KT4 MMG150J120UZ6TN |

kT1 | 10:1 |

kT2 | 1:6 |

Magnetic material | Ferrite |

Volume of T1 | 506 cm^{3} |

Volume of T2 | 356 cm^{3} |

Turns of T1 | Primary: 20 Secondary: 2 |

Turns of T2 | Primary: 13 Secondary: 78 |

QS1, QS2, QS3, QS4 | IXFN110N60P3 |

DO1, DO2 | MCK400TS60S |

LO | 10 µH |

CO | 2000 µF |

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## Share and Cite

**MDPI and ACS Style**

Wang, Y.; Shi, Y.; Xu, K.
A New Zero-Voltage Zero-Current Switching Converter with Minimum Duty Cycle Loss. *Electronics* **2024**, *13*, 518.
https://doi.org/10.3390/electronics13030518

**AMA Style**

Wang Y, Shi Y, Xu K.
A New Zero-Voltage Zero-Current Switching Converter with Minimum Duty Cycle Loss. *Electronics*. 2024; 13(3):518.
https://doi.org/10.3390/electronics13030518

**Chicago/Turabian Style**

Wang, Yuting, Yong Shi, and Kexin Xu.
2024. "A New Zero-Voltage Zero-Current Switching Converter with Minimum Duty Cycle Loss" *Electronics* 13, no. 3: 518.
https://doi.org/10.3390/electronics13030518