An Enhanced Verilog-A Model for Graphene Field-Effect Transistors Using Variable Fermi Velocity

Abstract

This paper presents a novel Verilog-A model for the Fermi velocity in Graphene Field-Effect Transistors (GFETs). The Fermi velocity is an important parameter associated with the energy spectrum of the delocalized bonds in graphene which impact the performance of a GFET. Unlike existing GFET models where the Fermi velocity is assumed to have a constant value, the proposed model considers carrier concentrations in the channel and gate dielectrics to create a closed-form solution for the Fermi velocity, a parameter previously demonstrated to vary based on these two factors. The proposed mathematical model is then adapted to Verilog-A for interfacing with computer-aided design (CAD) circuit simulators. To demonstrate the accuracy of the proposed model, the simulation results are compared to measured drain–source currents obtained from various GFET devices (including GFETs measured by authors). The measured results show good agreement with the values predicted using the proposed model (<±1%), demonstrating the superior accuracy of the model compared to other published Verilog-A-based models, especially around the Dirac point.

1. Introduction

Graphene is a material of interest for high-frequency applications due to its high carrier mobility. Graphene Field-Effect Transistors (GFETs) have garnered interest for use in high-frequency circuits due to their ambipolar conduction (i.e., conduction via holes or electrons) [1]. However, the lack of a universally applicable model that can accurately predict device performance has impacted the adoption of this technology in analog integrated circuits. Creating an accurate GFET model has proven to be very challenging due to the lack of closed-form solutions for the ambipolar charge, quantum capacitance, Fermi velocity, and carrier mobility [2,3].

Mathematical models for a GFET have been through many iterations while under development, with many different authors contributing towards creating a complete model. By incorporating the work by Fang et al. [4] on charge carrier concentrations in graphene, Thiele et al. developed the first dual-gated GFET model that incorporates the dependence of charge carrier behavior on the channel voltage, quantum capacitance, and saturation velocity [2,5]. Wang et al. built upon this work to create a compact virtual-source GFET model that considers source resistance, mobility saturation, and simplified 1D electrostatics [6]. Separately, Parrish et al. introduced an accurate quantum capacitance approximation and the concept of symmetric channel charge [7]. Shortly thereafter, the first Verilog-A-based GFET model was created by Rodriguez et al. [8] and enhanced by Landauer et al. by introducing adjustments to previous mathematical models, making them more compatible with closed-form solutions [9]. Furthermore, a novel channel voltage solution method, compatible with Verilog-A, was introduced [9]. Finally, Tian et al. introduced a new mobility model, considering both hole and electron contributions, and created new, simplified mathematical models of the saturation velocity and capacitance weighting factor [3,10]. Despite these numerous improvements, the aforementioned models do not properly represent the Fermi velocity, resulting in inaccuracies in calculating channel conduction. This paper describes an effort to address this issue by improving Tian et al.’s effective mobility model and creating a novel Fermi velocity solution method. This Fermi velocity solution method takes advantage of the computational power of the CAD tools, such as the Keysight’s Advanced Design System (ADS), to concurrently solve for the Fermi velocity at every iteration of the simulation. The remainder of this paper is organized as follows: Section 2 provides an overview of the existing GFET models and their deficiencies. Section 3 describes the development of the novel Fermi velocity model, followed by the implementation and validation steps in Section 4 and the conclusions in Section 5.

2. Evolution of GFET Models

2.1. Fermi Velocity

A critically important parameter in accurate GFET modeling is the Fermi velocity, as it significantly influences the drain current of a GFET. The Fermi velocity is used to describe the energy spectrum of the delocalized π bonds in graphene, which results from its SP² hybridization. Using a tight-binding Hamiltonian analysis, the energy spectrum of the first Brillouin zone for graphene may be calculated using $E(k)=s{v}_f\hslash |k|$, where $v_f$ is the Fermi velocity, $\hslash$ is the reduced Planck’s constant, $s$ is ±1 (+1 for the conduction band and −1 for the valence band), and $k$ is the momentum [4]. Conversely, the Fermi velocity exhibits an inverse relationship to several key GFET parameters, such as the mobility, charge density, and quantum capacitance. A lower Fermi velocity value is preferred, with the ideal value calculated to be 0.85 × 10⁶ m/s, as derived from suspended metallic carbon nanotubes [11]. Traditionally, GFET models utilize a constant Fermi velocity of 1 × 10⁶ m/s. However, the Fermi velocity has been demonstrated to be significantly influenced by the choice of gate dielectric material and doping [11,12]. Therefore, accurate GFET modeling must incorporate substrate effects on the Fermi velocity.

2.2. Revisiting the Dual-Gated GFET Model

One of the most important derivations to result from Thiele et al.’s dual-gated GFET model [5] is the general drain current equation, derived from the drift–diffusion equation and the drift velocity of graphene:

$$I_D={\displaystyle \frac{W{\displaystyle {\int }_0^{VDS}\mu q{\rho }_{sh}dV}}{L+|{\displaystyle {\int }_0^{VDS}\mu \frac{1}{v_{sat}}dV}|}},$$

(1)

where µ is the mobility, $q$ is the elementary charge, ${\rho }_{sh}$ is the charge sheet density, $v_{sat}$ is the saturation velocity, W and L are the width and length of the gates, and VDS denotes the drain–source voltage of the GFET, respectively. The term $q{\rho }_{sh}$ is the total charge within the channel, which is expressed as [9]

$$Q_{tot}=q{\rho }_{sh}=Q_t+q{n}_{pud},$$

(2)

where Q_t is the total charge in the channel and $n_{pud}$ is the number of puddles, a value that adjusts for the trapped charges. The total channel charge, Q_t, may be calculated by finding the channel’s sum of the hole and electron charges, which have each been previously modeled mathematically by Thiele et al. [2,5]:

$$p={\displaystyle \frac{2{(k_{B}T)}^2}{\pi {(\hslash v_F)}^2}}{F}_1({\displaystyle \frac{q{V}_{ch}}{k_{B}T}}),$$

(3)

$$n={\displaystyle \frac{2{(k_{B}T)}^2}{\pi {(\hslash v_F)}^2}}{F}_1(-{\displaystyle \frac{q{V}_{ch}}{k_{B}T}}),$$

(4)

where $k_B$ is Boltzmann’s constant, $T$ is the temperature, $\hslash$ is the reduced Planck’s constant, $v_F$ is the Fermi velocity, $q$ is the elementary charge of an electron, and $V_{ch}$ is the voltage in the transistor’s channel, respectively. F₁(x) is the first-order Fermi–Dirac approximation in accordance with [13,14]. The total channel charge, Q_t, may now be calculated by summing the electron and hole densities and multiplying the result by the charge [2,9]:

$$Q_t={\displaystyle \frac{q\pi {(k_{B}T)}^2}{3{(\hslash v_F)}^2}}+{\displaystyle \frac{q^3{V_{ch}}^2}{\pi {(\hslash v_F)}^2}}$$

(5)

By assuming an even distribution of holes and electrons, $n_{pud}$ may be modeled as [14]:

$$n_{pud}={\displaystyle \frac{{\Delta }^2}{\pi {(\hslash v_F)}^2}},$$

(6)

where ∆ is the spatial inhomogeneity potential, a physical property of graphene.

An equation representing saturation velocity, $v_{sat}$, was developed by Tian et al. in order to achieve continuous transconductance modeling [3,5]:

$$v_{sat}=v_F({\displaystyle \frac{e}{1+f{V}_{ch}^2}}+g),$$

(7)

where $f={(q/5kb)}^2$. The terms e and g were experimentally found to be 0.58 and 0.058, respectively.

Since GFETs exhibit ambipolar conduction, GFET models must represent both hole and electron mobility. Hole and electron mobility have different maximal values; thus, an accurate mobility model must account for both carrier types. Tian et al. created such a model [10]:

$${\mu }_{eff}^{″}=({\displaystyle \frac{14z(a+b{V}_{ch}^2)}{a+b{V}_{ch}^2+n_{pud}}}{\displaystyle \frac{V_{ch}}{\sqrt{1+c{V}_{ch}^2}}}+h){\displaystyle \frac{m}{m+V_{ch}^2}},$$

(8)

where $a=\pi {(k_{B}T)}^2/3{(\hslash v_F)}^2$, $b=q^2/\pi {(\hslash v_F)}^2$, $c={(q/(k_{B}T(\ln 4)))}^2$, $z=({\mu }_p-{\mu }_n)$, and $h=({\mu }_p+{\mu }_n)/2$. The parameter m is considered an empirical fitting parameter.

One important parameter that appears in (5), (7), and (8) is the channel voltage, $V_{ch}$, which is the voltage drop across the quantum capacitance for dual-gated GFETs [15]. A closed-form approximation showing the relationship between $V_{ch}$ and $C_q$ is [9]

$$C_q\approx {\displaystyle \frac{2q^2{k}_{B}T\ln 4}{\pi {(\hslash v_F)}^2}}\sqrt{1+{({\displaystyle \frac{q{V}_{ch}}{k_{B}T\ln 4}})}^2},$$

(9)

To find $V_{ch}$, the capacitance weighting factor, $\alpha$, has been introduced, such that $Q=\alpha C_q{V}_{ch}$ [9]. Tian et al. introduced a Verilog-A-compatible model of α with the following equation [3]:

$${\alpha }^{\prime }(V_{ch})=({\displaystyle \frac{1}{1+c{V}_{ch}^2}}){\alpha }_{\min },$$

(10)

where ${\alpha }_{\min }$ is a fitting value of 0.5, the minimum permissible value for $\alpha$. This equation proves to be symmetrical for both holes and electrons within the graphene channel [7,16]. By performing a conservation of charge analysis across the top and bottom electrodes of $C_q$, the $V_{ch}$ can be expressed as [3]

$$V_{ch}=-{\displaystyle \frac{(V_{GS}-V_{GS0}-V(x))C_t+(V_{BS}-V_{BS0}-V(x))C_b}{C_t+C_b+\alpha (V_{ch})C_q}},$$

(11)

where $V_{BS}$ and $V_{GS}$ are the back gate-to-source and top gate to-source voltages, respectively. $V_{BS0}$ and $V_{GS0}$ are similar to the threshold voltages for the gates, which are inherent properties of the GFET. $C_t$ and $C_b$ are the top and back gate parallel plate capacitances, respectively. Landauer et al. utilized a method previously used by Deng et al. for carbon nanotube FET modeling [17] to solve this challenging equation. By multiplying the entirety of (11) by the denominator of the right-hand side, each side of the equation can be represented by two current sources in series, with each side’s dependent values being the node between the two sources:

$$(C_t+C_b+\alpha (V_{ch})C_q)V_{ch}=-(V_{GS}-V(x))C_t-(V_{BS}-V(x))C_b,$$

(12)

where $V_{GS}^{\prime }=V_{GS}-V_{GS0}$, $V_{BS}^{\prime }=V_{BS}-V_{BS0}$. In this manner, (11) may be represented in Verilog-A by a circuit, which is commonly used in many circuit simulators such as the Keysight’s ADS (https://www.keysight.com/us/en/lib/resources/software-releases/pathwave-advanced-design-system-ads-2021.html (accessed on 29 October 2024)) used in this work.

3. Fermi Velocity Modeling and Improved Mobility

3.1. Fermi Velocity Modeling

The first step in understanding how the Fermi velocity behaves under different conditions is to assess the Dirac cone, which represents the energy spectrum of the basic graphene lattice. Experimental dispersion measurements show that with poor dielectric screening, the sides of the Dirac cone become sub-linear [12]. Materials with larger dielectric constants result in greater dispersion linearity, resulting in a desired, smaller Fermi velocity. In fact, the Fermi velocity has been demonstrated to be inversely proportional to the charge carrier concentration due to its direct relationship with the Fermi momentum, $k_F$ [11,12,18,19]:

$${\displaystyle \frac{v_F}{v_{F0}}}=1+C({\alpha }_s){\alpha }_s\ln {\displaystyle \frac{\Lambda }{k_F}},$$

(13)

where $v_F$ is the effective Fermi velocity; $v_{F0}$ is the maximum Fermi velocity (0.85 × 10⁶ m/s); Λ, the momentum cutoff, is 1.75 Å; and $k_F=\sqrt{\pi n}$ is the Fermi momentum of the charge carriers, respectively. The term ${\alpha }_s$ is the dimensionless fine structure constant or Sommerfield constant, which is given by $\alpha =q^2/(4\pi \hslash v_{F0}{\epsilon }_{eff}{\epsilon }_0)\cdot C({\alpha }_s)=1/[4(1+({\displaystyle \frac{\pi }{2}}){\alpha }_s)]$ and represents the self-screened interaction between carriers, characterized by the random-phase approximation (RPA) within the Dirac model [19]. Traditionally, the effective dielectric constant, ${\epsilon }_{eff}$, has been defined as $(1+{\epsilon }_s)/2$, where ${\epsilon }_s$ is the dielectric constant of the substrate, and 1 represents the dielectric constant of air. This equation is simply an average of the dielectric constants of the air and the substrate for the deposited graphene [11,12,18,19].

3.2. Employing the Novel Fermi Velocity Model

In many applications, the graphene is sandwiched between two dielectric layers; hence, (13) must be modified accordingly. In this case, the effective dielectric constant will be adapted to $\epsilon =({\epsilon }_t+{\epsilon }_b)/2$, where ${\epsilon }_t$ and ${\epsilon }_b$ are the dielectric constants of the top and bottom gate structures, respectively. From (13), the effective Fermi velocity is also dependent on the carrier concentration, which is taken into account by $k_F$. As indicated by previous equations for the hole and electron carrier density, (3) and (4), the carrier concentrations within the GFET channel are influenced by the voltages externally applied to the GFET. However, (13) only considers a positive value for the concentration, intended for electrons. The work conducted by Elias et al. demonstrates that the relationship between the Fermi velocity and the hole concentration mirrors that of the electron concentration [11]. By solving for the Fermi velocity from the absolute value of the difference between (4) and (3), the Fermi velocity due to net carrier concentration may be found, leading to a modified version of (13), which results in a system of equations for the channel concentration:

$$\sqrt{{\displaystyle \frac{2{(k_{B}T)}^2}{n\pi {(\hslash )}^2}}|F_1(-{\displaystyle \frac{q{V}_{ch}}{k_{B}T}})-F_1({\displaystyle \frac{q{V}_{ch}}{k_{B}T}})|}=v_{F0}(1+C({\alpha }_s){\alpha }_s\ln {\displaystyle \frac{\Lambda }{\sqrt{\pi n}}}),$$

(14)

This transcendental equation is difficult to utilize as a closed-form solution. Using a similar Verilog-A-based method to that of Landauer et al. [9], the Fermi velocity in the channel may be obtained (Figure 1). Two problems arise from this method: the channel voltage is required for both the Fermi velocity and charge carrier concentrations, and the model requires that all the charge carriers in the channel be represented by only one Fermi velocity. In reality, each carrier in the channel should have a distinct Fermi velocity that is dependent upon bias voltage, but this would result in even more complex equations. To address this issue, first, the channel voltage is calculated by assuming the ideal Fermi velocity ($v_{F0}$). Secondly, a single Fermi velocity can be found by taking a weighted average of the two Fermi velocities calculated at the source and drain as follows:

$$v_F=v_{Fcd}{\displaystyle \frac{\left|V_{cd}\right|}{\left|V_{cd}\right|+\left|V_{cs}\right|}}+v_{Fcs}{\displaystyle \frac{\left|V_{cs}\right|}{\left|V_{cd}\right|+\left|V_{cs}\right|}},$$

(15)

where $v_{Fcd}$ and $v_{Fcs}$ are the Fermi velocities at the drain and source, and $V_{cd}$ and $V_{cs}$ are the channel voltages at the drain and source of the GFET channel, respectively. A weighted average represents the magnitude of each voltage, which determines the influence of the drain and source voltages over the channel. As shown in Figure 2 [20], the ambipolar behavior of the GFET leads to the channel voltage having opposite polarities during the conduction phase. However, the Dirac point is determined by the magnitude of the channel voltages. A higher-magnitude channel voltage results in the graphene channel’s dominance.

3.3. Simplifying the Effective Mobility for Simulation

The final step before populating (1) is to minimize the discrepancy of the effective mobility in Tian et al.’s model, which increases with the channel voltage (Figure 3) [10]. By considering the limit when the empirical parameter m is taken to infinity, the following expression for effective mobility is obtained:

$${\mu }_{eff}^{‴}=\underset{x\to \infty }{\lim }{\mu }_{eff}^{″}=({\displaystyle \frac{14z(a+b{V}_{ch}^2)}{a+b{V}_{ch}^2+n_{pud}}}{\displaystyle \frac{V_{ch}}{\sqrt{1+c{V}_{ch}^2}}}+h),$$

(16)

As shown in Figure 3, the improved effective mobility exhibits a higher degree of accuracy at high channel voltages, with the relative difference trending towards zero. Since m is simply an empirical fitting parameter, the impact on the accuracy of the model can be minimized. Moreover, using (16) to calculate effective mobility results in one less modeling parameter.

3.4. The Closed-Form Solution for the Drain Current

To arrive at a closed-form solution for the drain current $I_{DS}$, (1) must be transformed to represent the channel voltage instead of the applied voltage. To achieve this, (11) may be integrated in terms of $V_{ch}$, resulting in the following equation:

$${\displaystyle \frac{dV}{d{V}_{ch}}}=1+{\displaystyle \frac{d{\alpha }_{\min }(2+c{V}_{ch}(3+2c{V}_{ch}^2))}{{(q+c{V}_{ch}^2)}^{3/2}}}$$

(17)

where $d=2q^2{k}_{B}T\ln (4)/(C_t+C_b)\pi {(\hslash v_F)}^2$. $I_{DS}$ can then be solved in terms of $V_{ch}$ by substituting (17), (16), (7), (2), and (5) into (1) and performing the required integration. The integration for the I_DS was performed in Mathematica supported by Rubi to aid in the integration process. The final equation for I_DS comprises two terms; the first term represents the numerator, $I_{D{S}_{num}}$, and the second term represents the denominator, $I_{D{S}_{denom}}$.

$$I_{DSnum}=W{\displaystyle {\int }_{Vcs}^{Vcd}q(a+b{V}_{ch}^2)}(1+{\displaystyle \frac{{\alpha }_{\min }d(2+c{V}_{ch}^2(3+2c{V}_{ch}^2))}{{(1+c{V}_{ch}^2)}^{3/2}}})(h+{\displaystyle \frac{14z{V}_{ch}}{\sqrt{1+c{V}_{ch}^2}}})d{V}_{ch}+W{\displaystyle {\int }_0^{V_{DS}}(q{n}_{pud}h)dV}$$

(18)

$$I_{D{S}_{denom}}=L+{|}_{V_{cd}}^{V_{cd}}{\displaystyle \frac{1}{v_F}}({\displaystyle \frac{1+f{V}_{ch}^2}{e+g(1+f{V}_{ch}^2)}})(h+{\displaystyle \frac{14z(a+V_{ch}^2)}{a+b{V}_{ch}^2+n_{pud}}}{\displaystyle \frac{V_{ch}}{\sqrt{1+c{V}_{ch}^2}}}+{\displaystyle \frac{h{\alpha }_{\min }(2+c{V}_{ch}^2(3+2c{V}_{ch}^2))}{{(1+c{V}_{ch}^2)}^{3/2}}})+$$

$${\displaystyle \frac{d{\alpha }_{\min }(2+c{V}_{ch}^2(3+2c{V}_{ch}^2))}{(1+c{V}_{ch}^2)}}{\displaystyle \frac{14z{V}_{ch}(a+b{V}_{ch}^2)}{a+b{V}_{ch}^2+n_{pud}}}d{V}_{ch}|$$

(19)

4. The Implementation and Validation of the Model

The GFET model is implemented in Verilog-A, and Keysight’s ADS integrated Verilog-A compiler is used for the synthesis of the GFET and electrical characterization. We use the same method used in [9] to construct a two series-connected current branch model in Verilog-A by using the channel potential $V_{ch}$ and voltage drop $V(x)$ as the model input parameters (node voltage) to represent the left- and right-hand sides of (12), showing the current through the node of the drain–channel potential and source-channel potential, respectively. The node voltage $V_{ch}$ at the source and drain derived from the current model is then used to calculate the Fermi velocity in (14). A novel biased-varying Fermi velocity model is realized using a similar method by creating two series-connected current branches representing the left- and right-hand sides of (14) and solving for the value of the carrier concentration, n, in the Fermi velocity calculation (Figure 4). A weighted average Fermi velocity v_F is found based on the drain and source Fermi velocities and used to create the final Verilog-A model. Two sources of experimental data were used to validate the proposed enhanced GFET model: (1) published data for a dual-gated GFET from Wang et al. [21] and (2) a back-gated GFET obtained by authors from Graphenea Inc., Cambridge, MA, USA.

4.1. Creating the Enhanced GFET Model

To accurately find the I_DS, two additional series resistors representing the drain and source contact resistances are added on either side of the drain–source current. This way, the channel voltage can be better estimated and used in the model to calculate the I_DS. To simplify the model, the channel voltage is calculated using the ideal Fermi velocity. To achieve better DC convergence performance in solving the two current source methods for the Fermi velocity calculation in Equation (14), the Newton–Raphson method, an effective root-finding algorithm for root approximation in differential equations in Keysight’s ADS DC simulator, is used with large iteration steps when we apply the Verilog-A model in the circuit.

4.2. Fermi Velocity Model

Shown in Figure 5 are the extracted values of the Fermi velocities at the drain and source interfaces obtained from modeling Wang et al.’s device [21] using this work’s model and the parameters given in Wang et al.’s paper. The drain–source, V_DS, values of 0.35 V (Figure 5a) and 1.1 V (Figure 5b) are chosen for this experiment. The blue dots and red dots represent the Fermi velocity of charge carriers at the drain and source, respectively. The fitted lines are b-splines of the data points for ease of viewing. Since the electron–electron interactions within the graphene drastically increase when the device is biased at the Dirac point, the effects of dielectric screening decrease [11,12], resulting in an increase in the Fermi velocity. As demonstrated in Figure 5, the Fermi velocity predicted by our model is in good agreement with the values obtained by Hwang et al. [12]. Moreover, the model exhibits the expected behavior for the Fermi velocity. Nevertheless, the proposed model shows a clear difference in the Fermi velocity at the drain and source of the channel with V_GS basing, predicting the Fermi velocity more accurately across different bias points. However, using a single Fermi velocity value, calculated from (15), in the model limits the accuracy of the model.

As the difference between the drain and source channel voltages increases, the difference between the Fermi velocities at the source and drain increases (Figure 5). The method of Fermi velocity calculation found in (15) results in a weighted average of these two curves, causing an underestimation of the Fermi velocity around the true Dirac point at high channel voltages and at either extreme end of the graphs, which explains the increasing errors around the Dirac point.

4.3. GFET Model Validation

Figure 6a presents the I-V characteristic of the dual-gated GFET from [21] using the proposed model when the top gate–source voltage is varied and the back gate is set to 0 V; the dotted plot shows the measured data from [21], while the solid line shows the simulation results. On the other hand, Figure 6b shows the I–V characteristics of the same device for various back gate–source voltages when the top gate–source voltage is set to 1.41 V. The device parameters used for this model are W = 25 µm, L = 5 µm, ${\epsilon }_t$ = 9, ${\epsilon }_b$ = 4, $t_{oxt}$ = 15 nm, $t_{oxb}$ = 300 nm, $V_{gs0}$ = 1.2 V, $V_{bs0}$ = 11 V, ${\mu }_n$ = 920 ${\mathrm{cm}}^2$/Vs, ${\mu }_p$ = 1330 ${\mathrm{cm}}^2$/Vs, ∆ = 90 m eV, T = 300 K, and $R_d$ = $R_s$ = 4.2 kΩ·µm. When comparing the results produced using our model with the published results of a dual-gated GFET measured by Wang et al. [21], a maximum relative difference of 8% is observed. Similarly, the I–V characteristics of a back-gated GFET provided by Graphenea Inc. are modeled and compared with the measurement results (Figure 7). The dotted curve shows the measurement results, while the red solid curve presents the simulated results obtained using the proposed GFET model. The device parameters used for this model are W = 100 µm, L = 100 µm, ${\epsilon }_t$ = 1, ${\epsilon }_b$ = 9.34, $t_{oxt}$ = 5 nm, $t_{oxb}$ = 300 nm, $V_{gs0}$ = 0 V, $V_{bs0}$ = 3.1 V, ${\mu }_n$ = 570 ${\mathrm{cm}}^2$/Vs, ${\mu }_p$ = 650 ${\mathrm{cm}}^2$/Vs, ∆ = 80 m eV, T = 300 K, and $R_d$ = $R_s$ = 30 kΩ·µm. The back gate voltage,V_BS, increases from 0 V to 4.5 V, while the drain–source voltage, V_DS, is kept near 0.5 V. Compared to the measured results, the modeled I_DS shows a maximum relative difference smaller than ±1%. Despite improved accuracy, the model generally underestimates I_DS, except near the Dirac point, where the model slightly overestimates I_DS. This small error is the consequence of the method used to calculate a singular Fermi velocity value. This model accuracy can be improved by considering the uneven distribution of the fermi velocity from drain to source at such biasing condition and perform more iterations to better estimate the weighted average $v_F$ throughout channel. Nevertheless, the accuracy demonstrated by our model is comparable if not better than those obtained by applying other GFET models. Another consequence of the concessions made to create the proposed Fermi velocity model is using the ideal value of the Fermi velocity to calculate the channel voltage in (12). This assumption resulted in a potential uneven distribution of the Fermi velocity variation from the source to drain. To show the robustness of the proposed model for various channel current and drain–source voltages, the I_DS and V_DS vs. the back gate source voltage was simulated (Figure 8). Figure 8 shows I_DS vs. the back gate–source voltage (V_BS) when V_DS changes from 0.49 V to 0.50 V. The plots show the same trend and behavior as those shown in Figure 6, indicating good accuracy in modeling I_DS for different V_DS, making the model useful for a variety of analog electronic circuit design applications. Due to the lack of access to short-channel GFET devices, model validation is only carried out on long-channel devices. Recognizing the non-idealities affecting the performance of the short-channel GFET devices (e.g., velocity saturation), further improvement, particularly in the weighted average estimation of the Fermi velocity at the drain and source, may be necessary.

5. Conclusions

A novel Verilog-A GFET model which uses a closed-form solution to determine the Fermi velocity is developed and evaluated. A systematic analysis of existing GFET models is performed to identify a methodology to accurately determine the Fermi velocity for various gate–source voltages. Using this information, a mathematical model which relates the Fermi velocity to the graphene carrier concentration, channel voltage, and dielectric constants of the gates is developed. During this process, a weighted averaging method is used to calculate a single value for the Fermi velocity. The accuracy of the model to predict the Fermi velocity as influenced by the top and bottom gate substrates is verified using experimental data from dual-gated and back-gated GFETs. The drain current measurement results differ by less than 8% at a single point and can be within ±1% of the measured values for long-channel devices produced by Graphenea, verifying the accuracy of this model for GFET-based circuit designs.