A 0.5 V Nanowatt Biquadratic Low-Pass Filter with Tunable Quality Factor for Electronic Cochlea Applications

Abstract

A novel implementation of an analogue low-power, second-order, low-pass filter with tunable quality factor (Q) is presented and discussed. The filter feature is a relatively simple, buffer-based, circuit network consisting of eleven transistors operating in a subthreshold region. Q tuning is accomplished by injecting direct current into a network node, which changes the output resistance of the transistors and, as a result, modifies the filter network’s loss, and thus its Q. Q tuning is independent of a filter cut-off frequency (ω₀). The filter, with a nominal ω₀ of 1 kHz, was fabricated using a 0.18 µm CMOS technology, and features a Q range of 2–11, power consumption of up to 52 nW, and a 59 dB dynamic range when using a 0.5 V supply. The ω₀ can be tuned from 0.5 to 2.5 kHz using a traditional method by changing the transistor transconductances, but this process partially affects the quality factor.

1. Introduction

One important functional block that is a part of hearing aids [1,2,3,4,5,6] as well as devices for human voice recognition [7], are tunable filters [8,9,10,11] that emulate characteristics of a human cochlea. Such filters allow pre-processing of acoustic signals based on extracting components of the amplitude spectrum of the received sounds and enabling adaptive adjustment of the sensitivity of the signal path in individual frequency bands. Such properties of the filters enable high dynamics and the intelligibility of received sounds, especially human speech, in the presence of noise and external interference, which has a significant impact on the comfort of using a hearing aid and the correctness of human speech recognition. Nowadays, hearing aids are more often manufactured in the form of implants that are placed in the middle ear of hearing-impaired people. In such a case, the problem of reducing power consumption and the voltage supplying the implant becomes particularly important, as the implant itself contains a small store of electrical energy, and its long-term operation relies on the cyclic recharging of energy [6].

Analogue filter implementations (e.g., as in [12,13,14,15,16,17,18]) show that analogue filters are more advantageous than fully digital ones from a power reduction perspective. On the other hand, examples of analogue filters realized so far show that it is still difficult to achieve sufficient performance, especially regarding low power consumption, to allow cochlear implant operation without energy charging for many hours. As a result, new, more efficient filter implementations with more favourable parameters are still being researched. Experience from previous implementations of filters in CMOS technology has demonstrated that satisfactory results can be achieved using banks of parallel- [12,13,14] or cascade- [15,16,17,18] connected second-order low-pass filters with electronically tunable quality factor (Q).

Cochlear filter banks typically cover the entire acoustic bandwidth, 20 Hz to 20 kHz, which can be limited to the range of 250 Hz–8 kHz when implementing only the speech recognition function [19]. Coverage of the required bandwidth is achieved using the appropriate number of filters in a bank, with octave-distributed cut-off frequencies (ω₀). As the volume of the received sound changes, adaptive adjustment of the acoustic sensitivity is realized by means of changes in the quality factor (Q) of individual filters, which is consistent with the physiology of human hearing [20].

The second-order filter presented in this paper was designed for use in cochlear filter banks. Thus, special attention was paid to voltage and power supply reduction and implementation of effective electronic tuning of the quality factor. MOS transistors operating in the subthreshold region with nano ampere bias currents were used to achieve a significant reduction in power consumption. The following sections of this paper describe the filter circuit, the theoretical analysis of the parameters, and measurement results obtained using a prototype filter fabricated using an X-FAB 180-nm CMOS process.

2. Materials and Methods

2.1. Principle of Operation

A detailed schematic of the proposed filter and its transconductance-C model are shown in Figure 1.

The filter consists of two transconductance stages. The first stage is a differential pair (M₁, M₂) loaded using a current mirror (M₃, M₄) and two extra current sources (M₈, M₉). Due to the low supply voltage (V_DD) of 0.5 V, the bulk-driven differential pair is used. The second stage is a source follower (M₅) loaded using a current source (M₆). The stages are modelled using the transconductors G₁ and G₂ in Figure 1b. Their transconductances, G₁ and G₂, are determined by DC bias current I_BIAS. The extra DC current I_Q, generated by M₈ and M₉, modifies the resistance seen at node A and, as a result, also modifies the filter quality factor. Nodal resistance is modelled using the adjustable resistor R₁ in Figure 1b.

With I_BIAS and I_Q less than 50 nA, all transistors in Figure 1a operate in the subthreshold region. The transistors’ gate transconductance (g_m), back-gate transconductance (g_mbs), and output conductance (g_ds) are proportional to their drain current (I_D) according to the following relationships

$$g_m\cong \frac{I_D}{n{V}_t}, g_{mbs}\cong \frac{n-1}{n}{g}_m=\frac{\left(n-1\right)I_D}{n^2{V}_t},g_{ds}\cong I_D{\lambda }_{DS}$$

(1)

where V_t is the thermal voltage, and n and λ_DS are technology-dependent parameters [21,22].

Thus, the transconductances of the stages are

$$G_1=g_{mbs1}\cong \frac{\left(n-1\right)I_{BIAS}}{2n^2{V}_t},G_2=g_{m5}\cong \frac{I_{BIAS}}{n{V}_t},$$

(2)

and the nodal resistance is

$$R_1=\frac{1}{g_{ds4}+g_{ds9}+g_{ds2}}\cong \frac{1}{{\lambda }_{DS}\left(I_{D4}+I_{D9}+I_{D2}\right)}=\frac{1}{{\lambda }_{DS}\left(I_{BIAS}+2I_Q\right)}$$

(3)

The resistance at node B, R₂, can be neglected because it is connected in parallel to the resistance 1/G₂, which is much smaller than R₂; i.e., 1/G₂ << R₂. With this, the filter transmittance is

$$H\left(s\right)=\frac{V_{out}\left(s\right)}{V_{in}\left(s\right)}=A\cdot \frac{{\omega }_0^2}{s^2+s{\omega }_0/Q+{\omega }_0^2}$$

(4)

where

$$A=1-\frac{1}{G_1{R}_1+1}, {\omega }_0=\sqrt{\frac{\left(G_1+1/R_1\right)G_2}{C_1{C}_2}}, Q=\frac{\sqrt{\left(G_1+1/R_1\right)G_2}\cdot \sqrt{\frac{C_1}{C_2}}\cdot R_1}{1+\frac{C_1}{C_2}{G}_2{R}_1}$$

(5)

To tune the quality factor effectively, the sensitivity of the Q parameter with respect to R₁ must be greater than the sensitivity of the other filter parameters. This is satisfied if C₂ is much greater than C₁, in details C₂ >> C₁G₂R₁ must be met, which is explained in the following section.

2.2. Q Tuning

Thus, assuming that C₂ >> C₁G₂R₁, the quality factor Formula (5) becomes

$$Q\stackrel{C_2>>C_1{G}_2{R}_1}{=}\sqrt{\left(G_1+1/R_1\right)G_2}\cdot \sqrt{\frac{C_1}{C_2}}\cdot R_1={\omega }_0\cdot C_1\cdot R_1$$

(6)

The relative sensitivities of the filter parameters with respect to R₁ are

$$S_{R_1}^A=\frac{1}{G_1{R}_1+1}, S_{R_1}^{{\omega }_0}=-\frac{1}{2\left(G_1{R}_1+1\right)}, S_{R_1}^Q=1-\frac{1}{2\left(G_1{R}_1+1\right)}$$

(7)

where the relative sensitivity is defined as $S_x^y$ = (dy/y)/(dx/x).

As G₁R₁ is much greater than one, G₁R₁ >> 1, and the sensitivity of Q to R₁ is several times greater than other sensitivities; i.e., $S_{R_1}^Q$ >> $\left|S_{R_1}^{{\omega }_0}\right|$ and $S_{R_1}^Q$ >> $S_{R_1}^A$. As a result, the quality factor adjustment only slightly disturbs the cut-off frequency and DC gain.

The condition C₂ >> C₁G₂R₁ at (6) is well satisfied in the developed filter, as C₂ is 60 pF, C₁ is 50 fF, and G₂R₁ ranges from 22 to 150.

2.3. ω₀ Tuning

The cut-off frequency ω₀ given by (5) is proportional to I_BIAS, ω₀ ~ I_BIAS, which results from the facts that conductances G₁, G₂, and 1/R₁ are ~I_BIAS. Using the same facts in (6), it can be deduced that Q should vary moderately when I_BIAS changes. The sensitivities of A, ω₀, and Q with respect to I_BIAS are as follows

$$S_{I_{BIAS}}^A=\frac{2I_Q}{I_{BIAS}\left(\eta +1\right)+2I_Q}\cong 0, S_{I_{BIAS}}^{{\omega }_0}=1-\frac{I_Q}{I_{BIAS}\left(\eta +1\right)+2I_Q}\cong 1, S_{I_{BIAS}}^Q=S_{I_{BIAS}}^{{\omega }_0}-\frac{I_{BIAS}}{I_{BIAS}+2I_Q}$$

(8)

where η = (n − 1)/(2n²V_tλ_DS). When the typical parameters of the process are used (i.e., n ≈ 1.3, λ_DS ≈ 0.01 V⁻¹, and V_t ≈ 25 mV), the η is about 350. Therefore, the sensitivity of ω₀ to I_BIAS is approximately equal to unity and is always greater than the sensitivity of Q to I_BIAS.

2.4. Mismatch

Technological mismatch affects all filter components (and hence, filter parameters) according to general rules, and are not analysed in detail here. However, the mismatch related to components C₁ and R₁ requires some comment.

The small capacitor C₁ is exposed to mismatch because of its small area (the Pelgrom rule) and the increased proportion of parasitic capacitances. Fortunately, the sensitivities of the filter parameters with respect to C₁ do not depend on the value of C₁: these sensitivities are constant and less than one; i.e., $S_{C_1}^{{\omega }_0}$ = −0.5, $S_{C_1}^Q$ = 0.5, and $S_{C_1}^A$ = 0. Thanks to this, the negative impact of a small C₁ on the filter characteristic is reduced.

As $S_{R_1}^Q$≅ 1, deviations in R₁ caused by mismatch directly translate into the spread of the quality factor. The mismatch in R₁ may be relatively high, because R₁ depends on many factors, such as transistor drain currents, channel lengths, λ_DS parameter, etc., which are sensitive to mismatch as well. However, detailed Monte Carlo simulations, taking into account all possible mismatch factors, show that ω₀ spreads from 971 to 1023 Hz and Q varies from 21.15 to 21.9 dB, which means that the 1-sigma deviations in ω₀ and Q are 7.95 Hz and 0.12 dB, respectively; i.e., only 0.8% and 0.5%, respectively, with respect to the mean values 0.99 kHz and 21.5 dB, as shown in Figure 2.

2.5. Noise

Figure 3a depicts the noise model of the filter. Sources v_n1 and v_n2 represent the input-referred noise of the respective amplifiers. The thermal noise of resistor R₁ is assumed to be included in v_n1 because this resistor is a part of amplifier G₁; i.e., R₁ is the output resistance of this amplifier.

Based on Figure 3a, the total filter noise (power spectral density) referred to the filter input is

$$v_{n,in}^2\left(\omega \right)=\frac{v_{n1}^2\left(\omega \right)\cdot {\left|H\left(j\omega \right)\right|}^2+v_{n2}^2\left(\omega \right)\cdot {\left|H\left(j\omega \right)\right|}^2\cdot {\left|\frac{1/R_1+j\omega C_1}{G_1}\right|}^2}{{\left|H\left(j\omega \right)\right|}^2}=v_{n1}^2\left(\omega \right)+v_{n2}^2\left(\omega \right)\cdot \frac{\frac{1}{R_1^2}+{\omega }^2{C}_1^2}{G_1^2}$$

(9)

where $v_{n1}^2\left(\omega \right)$ and $v_{n2}^2\left(\omega \right)$ denote the power spectral density of the respective noise sources.

Figure 3b,c show the amplifier schematics containing all relevant sources of transistor noise (i_n7 noise has been neglected, as it is attenuated by a differential stage). Based on these schematics, $v_{n1}^2\left(\omega \right)$ and $v_{n2}^2\left(\omega \right)$ are

$$v_{n1}^2\left(\omega \right)=\frac{{\displaystyle \sum i_n^2}}{G_1^2}=\frac{i_{n1}^2\left(\omega \right)+i_{n2}^2\left(\omega \right)+i_{n3}^2\left(\omega \right)+i_{n4}^2\left(\omega \right)+i_{n8}^2\left(\omega \right)+i_{n9}^2\left(\omega \right)}{G_1^2}, v_{n2}^2\left(\omega \right)=\frac{{\displaystyle \sum i_n^2}}{G_2^2}=\frac{i_{n5}^2\left(\omega \right)+i_{n6}^2\left(\omega \right)}{G_2^2}$$

(10)

The Q tuning mechanism introduces extra noise, which is related to the finite resistance R₁ in (9) and the additional noise currents i_n8 and i_n9 in (10). The power density of this extra noise can be estimated by calculating the difference in the input-referred noise of the filter with Q tuning, (9), and without one; i.e.,

$$v_{n,in}^2\left(\omega \right)-v_{n,in,without Q tuning}^2\left(\omega \right)=\frac{i_{n8}^2\left(\omega \right)+i_{n9}^2\left(\omega \right)}{G_1^2}+\frac{i_{n5}^2\left(\omega \right)+i_{n6}^2\left(\omega \right)}{G_1^2{R}_1^2{G}_2^2}\cong \frac{i_{n8}^2\left(\omega \right)+i_{n9}^2\left(\omega \right)}{G_1^2}$$

(11)

Formula (11) shows that the additional noise related to the Q-tuning mechanism is mainly due to the noise generated by transistors M₈ and M₉. As the noise of these transistors increases with their bias current I_Q, a filter variant with low Q has more noise compared to a high-Q variant. The simulated worst-case noise of the 1 kHz (I_BIAS = 3 nA) filter in Figure 1a is with a maximal I_Q of 40 nA (Q = 1.9), and is 60 µV_RMS when referred to the filter input and integrated from 100 Hz to 1.5 kHz. Assuming no transistors M₈ and M₉, the filter noise is 40 µV_RMS, which means that the additional Q-tuning circuit increases the filter noise by 50%.

3. Experiments

3.1. The Chip and Measurements

The filter was implemented in the integrated circuit shown in Figure 4a. A white rectangle indicates an area of the filter, which is 128 µm by 258 µm, including metal-insulator-metal (MIM) capacitors. MIM capacitors cover the entire filter; hence, no transistors are visible in the micro photo.

The arrangement of transistors inside the filter cell is illustrated in Figure 4b. The filter cell contains transistors M₁ to M₉; their dimensions, W/L in µm/µm, are as follows: M₁ and M₂, 40/10; M₃ and M₄, 40/5; M₅, 40/10; M₆, 20/10; and M₇, M₈, and M₉, 10/10. Transistors M₁₀ and M₁₁ are outside the cell because they are wide (one hundred parallel-connected 10/10 devices each) to conduct off-chip bias currents. All transistors are thin-oxide low-V_T devices with threshold voltages (V_T) of 0.34 V and −0.39 V for n and p type devices, respectively. Low threshold voltages are necessary due to the 0.5 V supply voltage. As low-V_T transistors have relatively high channel leakage, long 10 µm channels are used, which reduce leakage to much below 0.1 nA at temperatures up to 50 °C.

In the following, measurement results for the filter operating using the supply voltage V_DD = 0.5 V, a gate bias voltage V_B = 150 mV, and input DC level of 360 mV are reported.

Figure 5 illustrates the Q tuning process, along with an I_Q ranging from 40 to 0.1 nA. On successive screens from the analyser, it is seen that Q increases from 6.7 dB (2.16) to 21.4 dB (11.74), and there is no deviation in ω₀ (1 kHz). Thus, this observation addresses (7), and confirms that the sensitivity of Q to R₁ is much greater than that of ω₀ to R₁.

The frequency tuning range was also examined. The consecutive screens in Figure 6 present the measured filter amplitude responses, in which ω₀ increases from 500 Hz to 2.5 kHz, with I_BIAS from 1.4 to 7.7 nA. In this case, the quality factor varies due to changes in transistor conductances: the Q deviation is ±12% or ±2%, assuming a tuning range of 0.5–2.5 kHz or 1–1.5 kHz, respectively. Quality factor deviations can be compensated by appropriate corrections of I_Q. For example, ω₀ and Q are 1 kHz and 21 dB, respectively, at an I_BIAS of 2.9 nA and an I_Q of 0.1 nA. If ω₀ is set to 1.5 kHz using an I_BIAS of 4.5 nA, then I_Q must be corrected to 0.3 nA to maintain the quality factor at the same level.

Figure 7a,b show the filter noise density and total-harmonic-distortion (THD) parameter measured at the filter output, respectively. The total noise, referred to the filter input and integrated from 100 Hz to 2 kHz, is 70 µV_RMS. The 1% output THD occurs with an input 200 Hz sine wave with an amplitude of 67 mV_RMS, which results in a signal-to-noise (S/N) ratio of 59.7 dB.

Measured filter parameters are summarized in

Table 1. Performance comparison of low-frequency filters with tunable Q.

Parameter	This Work	[23] Simulated	[18]	[12]	[13]	[14]
Process	0.18 µm	0.18 µm	0.35 µm	0.35 µm	1.5 µm	0.18 µm
Supply	0.5 V	0.5 V	3.3 V	3.3 V	2.8 V	0.5 V
Power	2.2–52 nW	8.25–10.75 nW	NA	13–20 µW 1	0.1–5.4 µW	0.1–100 nW 2
ω0	0.5–2.5 kHz	1.28 kHz	0.1–20 kHz bank	0.31–8 kHz bank	0.2–6 kHz bank	0.08–20 kHz bank
Q	2–11	2–40	NA	2–19	1–10	1.3–39
S/N	59 dB	68 dB	36–52 3 dB	17–32 dB	57 dB	40–55 dB

¹ Estimated. ² Estimated assuming no PGA. ³ With PGA.

. Power consumption ranges from 2.2 to 52 nW, depending on the Q and ω₀ values. The power and noise performance of the filter presented in this work are better compared to other solutions, except that of [23]. In terms of quality factor range, the realization of this work meets the minimum requirements for cochlear applications (a Q range of 2–11). The best Q range, 1.3–39, was reported in [14].

The frequency tuning range of this work’s filter, 0.5–2.5 kHz, cannot be meaningfully compared, because other references report only the frequency range of an entire bank of filters (e.g., 0.1–20 kHz), and not those of individual filters.

The next section discusses the frequency range of a filter bank assuming use of the filter presented in Figure 1a.

3.2. Filter Bank Design Example (Simulations)

A filter bank is a cascade of filters with different nominal cut-off frequencies. To change the nominal cut-off frequency of the filter in Figure 1a, the circuit must be redesigned by appropriately scaling the bias current, capacitance, and transistor dimensions. Taking into account practical design limits, such as a minimum transistor bias current of 0.5 nA (which implies that I_BIAS ≥ 1 nA) and the upper capacitance limit of 100 pF, the cut-off frequency can be scaled down to 500 Hz, according to

Table 2. Scaling a filter bank—simulations ¹.

ω0 (kHz)	C2 (pF)	IBIAS (nA)	M 2	IQ (nA)		P (nW)
				Q = 11.22 (21 dB)	Q = 5.01 (14 dB)	Q = 11.22 (21 dB)	Q = 5.01 (14 dB)
0.5	60	1.42	1	0.025	1.54	2.155	3.67
1	60	2.93	1	0.136	3.1	4.531	7.495
2	30	6.01	2	0.453	6.2	9.468	15.215
4	15	9.12	2	0.198	5.83	13.878	19.51
8	7.5	9.4	2	0.055	5.95	14.155	20.05

¹ Process: X-FAB 180-nm (xh018). Transistors: thin oxide 1.8 V, low VT. ² Transistor multiplication factor (the number of parallel connected transistors).

.

On the other side, the upper range of the cut-off frequency is limited by two factors: a minimum value of filter capacitance allowed due to mismatch, and a maximum value of I_BIAS related to a power limit. So, based on the worst power case selected from Table 1 (which is [12]), the practical limit of 20 µW per single filter in a bank can be assumed, which is well above the 52 nW achieved in this work. Nevertheless, scaling up I_BIAS involves upscaling the transistors’ widths (according to scaling factor M in Table 2), which results in a larger parasitic capacitance at node A. This parasite limits the cut-off frequency to 8 kHz, which is quite sufficient for speech recognition systems.

4. Discussion

Selecting an appropriate filter structure to build a filter bank is related to the method for tuning the filter quality factor. Depending on the filter structure, the quality factor is adjusted by changing a specific circuit parameter, e.g., the amplifier gain, transconductance, resistance, etc. However, changes in circuit parameters always affect the filter cut-off frequency to a greater or lesser extent. Figure 8 schematically illustrates three different methods of Q tuning: the one proposed in this paper and two others that are applicable to transconductance-C (Gm-C) filter structures. These three methods are briefly discussed and compared.

The filter shown in Figure 8a uses a loop-in voltage attenuator (A) to tune the quality factor [23]. This method is the only one among those illustrated that allows for fully independent control of the quality factor and cut-off frequency. The disadvantage of this scheme is a certain difficulty in implementing the attenuator, which must attenuate only AC signals, not DC signals.

In the classic method illustrated in Figure 8b, the quality factor is tuned independently by means of the additional transconductance G₃ [16,17,18,24]. Independent tuning of the cut-off frequency is possible, but G₁/G₂ and G₃/G₂ ratios must be kept constant. Therefore, the robustness of this filter to the transconductance mismatch is weaker compared to that of the other solutions.

The technique proposed in this paper (Figure 8c) uses the adjustable output resistance of a transconductance amplifier to tune the filter quality factor. This is a compromised solution, because the quality factor can be controlled independently, while frequency tuning causes some deviations in the Q factor. The robustness of filter characteristics to technological mismatch is at a satisfactory level despite the capacitance disparity (C₁ << C₂), as previously mentioned. The proposed quality factor tuning technique’s advantages include relatively simple implementation, because it does not require additional amplifiers, transconductors, etc., but only requires simple DC current sources.

5. Conclusions

The filter presented in this paper can be used to implement low-cost filter banks that emulate the characteristics of the cochlea over the speech frequency range. The proposed filter belongs to the class of buffer-based filters [25] characterized by a DC voltage gain close to unity and an insensitivity to mismatch in the filter passband. Therefore, the proposed filter is suitable for both parallel and cascade banks.