Sofware-Defined Radio Testbed for I/Q Imbalanced Single-Carrier Communication Systems
Abstract
:1. Introduction
- We present an end-to-end hardware testbed for IQI communication systems. This testbed is designed with high adaptability; consequently, not only the IQI parameters are configurable, but also a wide range of system parameters, such as the constellation, frequency, and packet structure. Furthermore, the source code and files associated with this work are publicly available at https://github.com/alvpr/IQI-SDR-Testbed (accessed on 30 June 2024).
- Throughout the receiver implementation, based on the consideration of asymmetric signaling, we encountered design aspects that are often overlooked in previous theoretical works, which typically focus on the final stage of symbol decision. These differences and their implications are discussed.
- We present Over-The-Air (OTA) measurements that closely align with theoretical simulations. Moreover, we compare the performance of an IQI-aware receiver with that of its unaware counterpart, demonstrating the effectiveness of the IQI-aware design. In this manner, this work narrows the gap between the theoretical analysis and practical implementation of IQI mitigation strategies in real-world systems, particularly for the study of asymmetric signaling. The extension of the proposed architecture to Multiple-Input–Multiple-Output (MIMO) is also discussed.
2. System Model
2.1. IQI Formulation
2.2. Receiver
3. System Implementation
3.1. General Considerations
3.2. Packet Design and SER Measurement
3.3. Receiver Design
- Automatic Gain Control (AGC): This block corrects the fading effect caused by the power coefficient and channel realization, . Note that this correction is not related to the power or analogue gain, and its only purpose is to scale the constellation symbols with two goals: first, to ensure the values of the digital samples fall within the expected ranges for the blocks downstream; second, to adjust the symbols to their proper decision regions.To perform its task, the block implements an adaptive filter that multiplies the incoming digital samples by a gain constant. This constant ensures that the variance of the output samples matches the desired value, . The gain constant is updated every 100 s. Changes in the scale due to ADC/DAC conversion are also corrected using this method. Since this block must know , which differs from ; as shown in Equation (9), it is considered CD.
- Time synchronization: This block performs time synchronization and matched filtering of the incoming signal, removing, or at least reducing, Inter-Symbol Interference (ISI). Under the assumption of a flat-fading channel, it can be generally regarded as CI. However, note that symbol equalization for a channel that introduces ISI would be CD.For clock recovery, the Time synchronization block uses a polyphase filter bank with 32 sub-filters, each introducing equally spaced time offsets from 0 to , where corresponds to the time offset of one symbol. The selection of the appropriate filter arm is dynamically controlled by a second-order control loop. This loop bases its decision on the first differential of the signal after it has been delayed by the chosen sub-filter. An output close to zero in the first differential indicates that the clock offset is corrected, which is why this output is used as the error signal for the control loop. After selection, the output from the appropriate filter arm passes through a Root-Raised Cosine (RRC) digital filter to remove ISI. Finally, the signal is downsampled to one sample per symbol, correcting for an oversampling added at the transmitter (Section 4) to aid the clock recovery algorithm. Employing 32 sub-filters ensures that the maximum ISI noise factor remains below the quantization noise of a 16-bit value, as further explained in [32], where the algorithm is described in more detail.
- Phase synchronization: This block is responsible for phase synchronization, essentially de-rotating the complex digital sample whose phase has been mainly shifted by h. Along with the AGC block, it plays a crucial role in ensuring correct symbol decision, and it is CD. The implementation of this block is based on a digital Costas Loop [33].
- Decision: This block performs ML decisions of the incoming symbol. It is clearly a CD block, as detailed in Section 2.
4. Methodology and Obtained Results
5. Discussion
- Measurements with an IQI-aware receiver are consistent with simulations. These matched results validate the receiver implementation. The slight differences observed at higher values of (low ) are attributed to the fact that, at these levels, the perturbations introduced by the hardware channel, , become comparable to o higher than the pre-distortion noise, . This assumption is confirmed by measuring the dispersion of points at the receiver, which provides an accurate estimation of for the whole range of the tested SNRs.
- The performance of an IQI-unaware receiver significantly degrades as the constellation number of points, M, increases. In denser constellations, the impact of an uncompensated IQI becomes more pronounced.
- An exception to the previous point are maximally improper or asymmetric constellations, such as 16-PAM. Results show the robustness of these constellations against IQI, even for unaware receivers. This experimental finding aligns with the theoretical conclusions presented in [9]. Consequently, PAM or, in general, maximally improper constellations, are a compelling option for IQI-unaware scenarios, albeit at the cost of lower power efficiency compared to QAM.
- IQI-unaware measurements exhibit better performance than IQI-unaware software simulations. As explained in Section 3.3, this is due to the receiver attempting to adjust the points to the constellation X before symbol decision, whereas software IQI-unaware simulations are assumed to only correct the product .
6. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
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Pendás-Recondo, Á.; López-Fernández, J.A.; González-Ayestarán, R. Sofware-Defined Radio Testbed for I/Q Imbalanced Single-Carrier Communication Systems. Electronics 2024, 13, 3002. https://doi.org/10.3390/electronics13153002
Pendás-Recondo Á, López-Fernández JA, González-Ayestarán R. Sofware-Defined Radio Testbed for I/Q Imbalanced Single-Carrier Communication Systems. Electronics. 2024; 13(15):3002. https://doi.org/10.3390/electronics13153002
Chicago/Turabian StylePendás-Recondo, Álvaro, Jesús Alberto López-Fernández, and Rafael González-Ayestarán. 2024. "Sofware-Defined Radio Testbed for I/Q Imbalanced Single-Carrier Communication Systems" Electronics 13, no. 15: 3002. https://doi.org/10.3390/electronics13153002
APA StylePendás-Recondo, Á., López-Fernández, J. A., & González-Ayestarán, R. (2024). Sofware-Defined Radio Testbed for I/Q Imbalanced Single-Carrier Communication Systems. Electronics, 13(15), 3002. https://doi.org/10.3390/electronics13153002