An Analog Delay-Locked Loop with Digital Coarse Lock Incorporating Error Compensation for Fast and Robust Locking

Abstract

This paper presents an analog delay-locked loop (DLL) with a digital coarse lock and error compensation, designed to enhance locking speed in duty-cycled operation while ensuring reliability. To accelerate coarse locking speed and prevent coarse lock failure, the proposed DLL combines a low-resolution digital-to-analog converter (DAC) with an analog method for accurate lock range identification, efficiently handling scenarios where the DAC’s limited resolution could lead to failure. Additionally, it enables the rapid control of voltage adjustments by disconnecting a loop filter during the coarse lock, eliminating the need for a buffer. The DLL improves the coarse lock process reliability by compensating for potential false lock errors caused by circuit non-idealities, such as residual RC delay and amplifier offset. Furthermore, it reuses the previously identified DAC input for the duty-cycled operation to significantly reduce relock time. To mitigate the risk of potential false lock resulting from changes in locking conditions, it can update the previous DAC input upon relocking, ensuring more reliable relocking. The proposed DLL, implemented in a 28 nm CMOS process, reduces initial lock and relock times by an average of 49.3% and 65.9% at a supply voltage of 0.5 V, and 42.4% and 70.2% at 1 V, respectively, compared to the conventional analog DLL.

1. Introduction

In neural network hardware, analog multiplier accumulators often utilize pulse width modulation (PWM) to convert multi-bit digital inputs into time-domain signals [1,2,3] (Figure 1a). Increasing the clock frequency (f_CLK) is a straightforward approach to enhance PWM resolution and achieve higher throughput. However, multiphase clock generators, such as phase-locked loops (PLLs) [4,5] or delay-locked loops (DLLs) [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23], provide a potentially more power-efficient alternative without increasing the f_CLK (Figure 1b). If frequency multiplication is unnecessary, DLLs may be preferable to PLLs because they provide better jitter performance and stability [6,7,8,9,10]. However, DLLs, particularly those with a wide range, can cause multiphase clock malfunctions due to false lock issues [11], such as harmonic or stuck false locks, depending on their initial delay. Also, since the PWM in in-memory or near-memory computing can be performed in a duty-cycled manner [1,2,3], energy efficiency can be improved by operating DLLs in duty-cycled mode instead of keeping them always on. Thus, a false-locking-free DLL with fast relocking is beneficial for energy-efficient PWM.

DLLs can be classified into analog and digital according to their delay line control method. Compared with digital DLLs, analog DLLs generally provide better jitter characteristics, smaller static phase offsets, and more precise multiphase generation due to their continuous delay control [12,13]. However, analog DLLs typically have a slower locking speed than digital DLLs. This is because, unlike analog DLLs, digital DLLs can directly adopt fast lock point search algorithms, such as successive approximation register (SAR) logic [12].

To prevent false locks, the initial delay of the delay line (T_DL) must satisfy the following condition (i.e., coarse lock) [6] before starting the DLL locking process:

$$0.5·T_{REF}<T_{DL}<1.5·T_{REF}$$

(1)

where T_REF is the period of the reference clock (CLK_REF). In conventional analog DLLs (Figure 2a), the control voltage (V_C) of the voltage-controlled delay line (VCDL) is initially set to the supply voltage (V_DD) to achieve the minimum delay. Then, V_C is gradually decreased by using an additional current source (I_B) to find the suitable condition for T_DL. However, while increasing I_B can accelerate the overall lock time, including initial T_DL adjustment, it may cause overly rapid changes in V_C. These rapid changes may fail to meet (1) due to nonlinear VCDL phase gain, increasing lock failure rate, as indicated in Monte Carlo simulation results (Figure 2b).

Various architectures have been proposed to accelerate the lock time without the false lock issues. The analog DLL with multiple loops [15] can shorten lock time by starting from a nearly locked state, utilizing the V_C from the locked reference loop (Figure 3a). However, an offset in the unity-gain buffer and mismatches between loops can decelerate locking. An analog DLL with a digital-controlled delay line (DCDL) [12] can achieve both a fast lock and false lock avoidance by employing SAR logic before fine lock using VCDL (Figure 3b). Yet, it increases the design complexity due to two distinct types of delay lines and may not be suitable for multiphase generation since VCDL and DCDL are separated. Similarly, an analog DLL with a time-to-digital converter (TDC) and a digital-to-analog converter (DAC) [17] can also achieve a fast coarse lock and a wide operational range free from false locks by applying quantized voltages to VCDL (Figure 3c). However, this may require a high-bit DAC to find a suitable quantization voltage that fulfills (1) [20,21]. While using exponential steps rather than linear ones in the DAC reduces the required bit number, a low-dropout regulator (or a unity-gain buffer) can still be needed during the coarse lock to supply the VCDL (or to handle the loop filter’s large capacitance) [17].

This paper presents an analog DLL featuring a digital coarse lock with error compensation, which enables fast locking for duty-cycled operation. The DLL identifies the coarse lock range satisfying (1) through a linear search algorithm with a low-resolution DAC. Even if the initial search fails due to the DAC’s coarse resolution, the DLL can fine-tune the V_C in an analog manner to meet (1) from the quantization voltage closest to the required T_DL condition. Moreover, by disconnecting the loop filter with large capacitance during the coarse lock process, the DLL allows rapid V_C adjustments without needing a unity-gain buffer, thus speeding up the coarse lock time. The buffer is activated only when charging the loop filter. It also compensates for errors caused by circuit non-idealities, such as parasitic RC delay or amplifier offset, reducing the risk of lock failure. The rest of the paper is organized as follows: Section 2 introduces the proposed architecture, Section 3 describes the circuit implementation, Section 4 presents the simulation and measurement results, and Section 5 concludes this work.

2. Architecture

Figure 4 presents a block diagram of the proposed DLL, which includes a conventional analog DLL, phase range detector (PRD), digital control block, DAC, unity-gain buffer, and switch controller for the V_C tuning. The proposed DLL’s locking process is divided into coarse lock and fine lock. The coarse lock employs the DAC and an analog tuning method to find an appropriate V_C satisfying (1), followed by the fine lock with the phase detector in the analog DLL. As depicted in Figure 5, the overall lock process comprises three key states: the phase range detection state, loop filter charging state, and analog DLL state. Initially, in the phase range detection state, the PRD classifies the VCDL delay (T_VCDL) phase range into three groups:

$${Under Range: T}_{VCDL}\le 0.5·T_{REF}+T_{m,under}$$

(2)

$$Lock Range:0.5·T_{REF}+T_{m,under}<T_{VCDL}\le 1.5·T_{REF}-T_{m,over}$$

(3)

$$Over Range:T_{VCDL}>1.5·T_{REF}-T_{m,over}$$

(4)

where $T_{m,under}$ and $T_{m,over}$ are the timing margins for the under range and the over range, respectively.

The PRD uses multiple phases based on these timing margins (which will be discussed in Section 3.1). During this state, the DLL incrementally increases the T_VCDL from the minimum delay to achieve the lock range (i.e., linear search). Accordingly, the DAC’s digital input (D_IN) starts at its maximum value, decreasing by 1 LSB from its previous D_IN to increase the T_VCDL whenever the PRD indicates the under range. To quickly apply D_IN adjustments to the T_VCDL, the DAC’s output resistance should be sufficiently low, given the high capacitance of the loop filter. This requirement increases the DAC’s power consumption due to the need for an output buffer. To reduce power consumption, the DLL temporarily disconnects the loop filter during this state, achieving a 90% reduction in capacitance at the DAC output, as confirmed by post-layout simulation, and eliminating the buffer requirement [24].

When the PRD output transitions from the under range to the lock range, the phase range detection state completes, indicating that the DLL has successfully identified the suitable D_IN value for the lock range (Figure 6a). Identifying the lock range across a wide CLK_REF typically requires a high-resolution DAC for fine T_VCDL control. However, this may slow the coarse lock process due to the increased number of voltage levels, adding to the design complexity. Conversely, a low-resolution DAC can accelerate the coarse lock process but may not always identify the lock range due to coarse T_VCDL control. To relax this trade-off, the proposed DLL employs an analog tuning method in the subsequent state, which is detailed later in this section, to fine-tune the V_C for the lock range. This approach efficiently identifies the lock range without the high-resolution DAC, simplifying the design. If the PRD output jumps directly from the under range to the over range, bypassing the lock range due to the low-resolution DAC, the search is halted. The D_IN corresponding to the over range then increases by 1 LSB. This adjustment returns the D_IN to its previous value, positioning the T_VCDL within the under range and close to the lock range, thereby completing the current state as the under-range condition (Figure 6b).

In the loop filter charging state, the loop filter is reconnected and charged through the unity-gain buffer with the DAC output voltage corresponding to the final D_IN value from the phase range detection state. After the predefined charging cycles are complete, the DLL transitions to the analog DLL state. Before describing the subsequent state, it is important to note two primary causes of potential lock failure: parasitic RC delay in the phase range detection state and buffer offset (or insufficient charging cycles) in the loop filter charging state.

Even though disconnecting the loop filter in the phase range detection state significantly reduces its capacitance, residual capacitance and resistance still introduce a delay in this state, which is particularly noticeable as T_REF decreases. In the phase range detection state, the actual T_VCDL can be less than the ideal value due to the RC delay at the input node of the VCDL, which elevates the average V_C level above the ideal DAC output level. However, if an ideal buffer is used, the V_C level in the loop filter charging state is precisely charged to the desired ideal level. Therefore, the PRD output of the loop filter charging state can differ from that of the phase range detection state (Figure 7a), potentially leading to lock failure. For example, even when the D_IN corresponding to the lock range is successfully identified in the phase range detection state, harmonic lock can occur if the T_VCDL falls into the over range in the loop filter charging state. This issue arises from an underestimation of the phase range, which can be attributed to the RC delay previously mentioned.

Additionally, even in the absence of RC delay in the phase range detection state, a similar problem can arise from buffer offset (or insufficient charging cycles) in the loop filter charging state. A negative offset (or insufficient cycles) can induce the over-range condition by increasing the T_VCDL (Figure 7b).

In the analog DLL state, operation depends on the phase range induced by the actual V_C after the loop filter charging state. There are three cases: (1) If the PRD output indicates the under range, the switch controller initiates the V_C tuning step by turning on I_B to gradually increase the T_VCDL. Once the PRD output reaches the lock range, the switch controller turns off I_B. Subsequently, the proposed DLL completes the V_C tuning step and transitions to the fine lock step. (2) If the PRD output indicates the lock range, the fine lock step is immediately initiated using the phase detector. (3) If the over-range condition is detected, the proposed DLL transitions back to the loop filter charging state by increasing the D_IN by 1 LSB to reduce the T_VCDL. This action aims to exit the over-range condition and achieve either the under-range or lock-range conditions. It then transitions back to the analog DLL state to reclassify the phase range of the reduced T_VCDL. Even if a delay error greater than 2 LSBs occurs, causing the over-range condition, this sequence repeats until the PRD output indicates the under range or lock range. This initiates the V_C tuning step if the under-range condition is detected or the fine lock step if the lock-range condition is detected. Consequently, the proposed DLL can lock to CLK_REF without encountering the false lock issue.

Furthermore, whenever the DLL restarts after achieving the initial lock in the duty-cycled operation, the previous final D_IN can generally be reused to bypass the phase range detection state, significantly reducing the relock time. However, if the locking conditions have changed between the previous lock and the restart, the reused D_IN may lead to the over-range condition, making the reused D_IN unsuitable (Figure 7c). In such cases, the DLL updates the D_IN using the same compensation strategy as described earlier, ensuring a reliable relock process. In conclusion, the proposed architecture achieves fast locking without the risk of false locks, even when utilizing a low-resolution DAC.

3. Circuit Implementation

3.1. Phase Range Detector

Figure 8a,b illustrate the proposed PRD circuit and the defined ranges, respectively. These defined ranges, as specified in (2)–(4), are determined by the positions of the feedback clock (CLK_FB) relative to the phase of CLK_REF. The PRD captures CLK_REF at the rising edges of the DLL’s multiphase outputs using D flip-flops (DFFs) [25]. The outputs Q [11:1] from these DFFs enable combinational logic to classify the T_VCDL into the lock range, under range, or over range. For the VCDL with M delay stages, the phase range of T_VCDL can be determined by the AND gating of the Nth Q (=Q [N]) and the inverted (N + 1)th Q (=Q [N + 1]), as follows:

$$\frac{M·D·T_{REF}}{N+1}<T_{VCDL}\le \frac{M·D·T_{REF}}{N}$$

(5)

where D denotes the duty cycle of the CLK_REF. To define the lock range, the phase range in (5) is extended by OR gating multiple AND gate outputs. In this work, with 50% duty cycled CLK_REF, the lock range is defined as

$$\frac{8}{11}·T_{REF}<T_{VCDL}\le \frac{4}{3}·T_{REF}$$

(6)

This configuration sets the $T_{m,under}$ and the $T_{m,over}$ in (3) to $5/22·T_{REF}$ and $1/6·T_{REF}$, respectively. The values 5/22 and 1/6 were determined based on simulations and are intended to provide sufficient margin under typical PVT variations. Additionally, to guarantee $T_{VCDL}\le 1.6·T_{REF}$, the AND gating of Q [5:1] is included in the lock range logic. For the under range, the AND gating of Q [11:1] indicates the following range:

$$T_{VCDL}\le \frac{8}{11}·T_{REF}$$

(7)

The over-range signal occurs when both the lock-range and the under-range signals are 0, identified by NOR gating.

3.2. DAC, Auto-Zero Buffer, and Voltage-Boosting Circuits (VBCs)

The DAC is designed with a resistor ladder structure using unary resistors and includes a footer transistor, which helps reduce static power consumption by deactivating the DAC when it is not in use (Figure 9). Although the proposed algorithm, presented in Section 2, can compensate for buffer offset error, an excessive offset may delay the locking process, as it requires additional time for compensation. Thus, the auto-zero technique is utilized for robust operation during the loop filter charging state. Even if some residual offset remains after auto-zeroing, the proposed algorithm can still compensate for it.

At a low V_DD (e.g., 0.5 V), the DAC switches face challenges in turning on, leading to substantial signal-dependent delays in the phase range detection state. To address this, a voltage-boosting circuit [26] is used (Figure 10), enabling efficient switch operation with a smaller transistor size. These circuits can be manually disabled when V_DD is sufficiently high.

3.3. Self-Resetting Phase Detector

Figure 11a,b show the proposed phase detector (PD) and its operations, respectively. Local feedback is employed for static logic design to ensure the PD’s reliable operation even at low frequencies of CLK_REF, where dynamic circuits may face challenges. For the PD’s normal operation, the rising edge timing difference between CLK_REF and CLK_FB should be less than $0.5·T_{REF}$. When CLK_REF leads (or lags) CLK_FB, the pulse width of the UP (or DN) signal is proportional to the input phase difference while maintaining a low DN (or UP) signal. This single-output approach helps reduce the power consumption during the fine lock process by preventing short currents. However, the PD’s dead zone can worsen jitter performance due to its range of undetectable phase differences. To mitigate this, the PD is designed to generate short pulses for both UP and DN in the locked state, effectively reducing the dead zone [4].

3.4. Digital Building Blocks

The digital blocks, including the FSM, control logic, counter, and decoder, were designed with a hardware description language and synthesized with automated placement and routing. To ensure a 50% duty cycle for CLK_REF, which is necessary for the normal operation of the PRD circuit, the external clock is halved. Additionally, these digital blocks support configurable options that allow for adjusting cycles as needed to accommodate the settling time required for V_C changes due to D_IN settings or for loop filter charging. To further reduce power consumption, clock gating is applied to these digital blocks.

4. Experimental Results

The proposed DLL was fabricated using a 28 nm CMOS process. The chip micrograph, shown in Figure 12, indicates that the core circuit occupies an active area of 0.013 mm². As a building block of a low-power neural network system with a processing-in-memory architecture for biomedical applications (e.g., a standard clinical ECG application has a bandwidth of 0.05 Hz to 100 Hz), the DLL was designed to operate at a V_DD of 0.5 V and within the CLK_REF frequency range of several MHz, generating 16 multiphases.

To determine the minimum DAC level required for lock range detection without employing the analog tuning method, Monte Carlo simulations were conducted at various CLK_REF frequencies and DAC levels under consistent conditions, including at the V_DD of 0.5 V, and including both global and local process variations. The results, illustrated in Figure 13, show that the lock range detection rate increases with the DAC level, suggesting that a minimum of 30 levels is necessary for the given V_DD.

Further Monte Carlo simulations were conducted to determine appropriate DAC levels when the analog tuning method is employed, focusing on the coarse lock time across different CLK_REF frequencies and DAC levels (Figure 14). As expected, the mean coarse lock time tends to increase as the CLK_REF frequency decreases at the same DAC levels because the V_C required for the lock range also decreases at these lower frequencies.

Additionally, the simulations revealed that lower DAC levels initially reduce the mean coarse lock time, which can be attributed to the larger voltage step per LSB during the phase range detection state. However, if the DAC level is too low (e.g., five levels in Figure 14), this large voltage step can lead to severe over-range conditions at some CLK_REF frequencies, resulting in excessive T_VCDL. These conditions prolong the cycles for phase range detection because correct PRD outputs are only obtained after all PRD inputs have been updated.

Furthermore, as DAC levels continue to decrease, the lock range detection rate, using only the DAC, drops. This necessitates an increase in the average number of cycles required for the analog tuning method. Therefore, using excessively low DAC levels can ultimately result in increased coarse lock time. Additionally, the standard deviations (σ), as seen in Figure 14, tend to increase as the DAC level decreases, indicating more frequent activation of the analog tuning method. Based on these findings, the prototype employed seven DAC levels with the V_DD of 0.5 V.

Figure 15a,b show the measured DLL output and state transitions for scenarios without and with error compensation, respectively, confirming alignment with the previously described timing diagrams. These measurements were conducted using a core V_DD of 0.5 V and an I/O V_DD of 0.7 V. The CLK_REF frequency was set at 0.75 MHz for the former scenario and 1.25 MHz for the latter.

Figure 16a,b show the measured lock times for various CLK_REF frequencies at core V_DDs of 0.5 V and 1 V, respectively. By disabling the digital coarse lock feature, the proposed DLL can function as the conventional analog DLL, allowing for direct comparisons that demonstrate the effectiveness of the proposed design; these results are summarized in

Table 1. Measured lock time summary.

VDD (V)	Average Lock Time (Cycles)			Lock Time Reduction (%)
	* Conv.	Proposed (Initial Lock)	Proposed (Relock)	Initial Lock vs. Conv.	Relock vs. Conv.	Initial Lock vs. Relock
0.5	29.6	15	10.1	49.3	65.9	32.7
1	34.9	20.1	10.4	42.4	70.2	48.3

* Conv.: conventional.

. When the digital coarse lock feature is enabled, it significantly reduces both initial lock and relock times. On average, at a V_DD of 0.5 V, initial lock time is reduced by 49.3% and relock time by 65.9%; at 1 V, the reductions are 42.4% for initial lock time and 70.2% for relock time, compared to those of the conventional analog DLL. Furthermore, the proposed DLL shows an average reduction in relock time over initial lock time by 32.7% at 0.5 V and 48.3% at 1 V, making it particularly suitable for applications requiring duty-cycled operations.

Figure 17 shows the simulated power breakdown under different V_DD conditions during the coarse lock process, where the buffer, DAC, PRD, and digital control block are activated. It should be noted that the DAC and analog DLL dominate the overall power consumption across different frequencies of the CLK_REF.

The external clock of the DLL, sourced from a waveform generator, is halved by the system’s main control block and routed through a synthesized clock tree, resulting in the CLK_REF. This CLK_REF has an RMS jitter of 16.64 ps at 40 MHz, which is the primary contributor to the DLL’s overall jitter. The DLL output exhibits an RMS jitter of 24.57 ps at a core V_DD of 1 V (Figure 18).

The performance of the proposed DLL compared with previous works is summarized in

Table 2. Performance comparison.

	TCAS-I’ 2012 [13]	TCAS-II’ 2022 [18]	TVLSI’ 2015 [21]	Access’ 2020 [22]	TCAS-II’ 2014 [26]	TCAS-II’ 2020 [27]	This Work
Process (nm)	180	180	130	180	130	28	28
Loop Filter	Analog	Analog	Digital	Digital	Digital	Digital	Analog
VDD (V)	1.8	1.8	1.5	1.8	1.2	1	0.5–1
Area (mm2)	0.035	0.0092	0.08	0.06	0.025	0.0072	0.013
Locking Freq. (MHz)	400–800	250	80–450	350–900	400–800	1800–2500	0.5–2.5 @0.5 V 1–40 @1 V
RMS Jitter (ps)	2.81 @800 MHz	1 14.72 @250 MHz	2.3 @180 MHz	1.2 @625 MHz	2.3 @800 MHz	1.7 @2.5 GHz	24.57 @40 MHz, 1 V
Power (mW)	19 @800 MHz	2.28 @250 MHz	26 @180 MHz	6.8 @625 MHz	7.2 @800 MHz	3.7 @2.5 GHz	0.107 @40 MHz, 1 V
2 FOMPOWER	7.33	2.81	64.2	3.35	6.25	1.48	3.50 @0.5 V 2.68 @1 V
Lock Time (Cycle)	<52	-	8–16	-	75–374	<72	9–25

¹ RMS jitter estimated from peak-to-peak jitter/6; ² FoM_POWER = power consumption (μW)/operating frequency (MHz)/supply voltage² (V²).

, highlighting its fast locking time and comparable figure of merit (FoM) for power.

5. Conclusions

A false-lock-free analog DLL with digital coarse lock and error compensation demonstrates significant improvements in lock speed. Using a low-resolution DAC alongside an analog tuning method, the DLL not only quickly and accurately identifies the lock range but also enhances its reliability by compensating for errors caused by circuit non-idealities, such as parasitic RC delays and amplifier offsets. Furthermore, the DLL achieves fast relock while minimizing potential false locks by reusing or updating the previous DAC input during duty-cycled operations. Fabricated using a 28 nm CMOS technology, the proposed DLL shows promise for applications requiring efficient phase synchronization, especially in environments with frequent on–off cycling.