A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

Round 1

Reviewer 1 Report

The topic of this paper is a dedicated digital signal process (DSP) for four pulse amplitude modulation receivers, targeting  as applications data recovery and adaptive equalization.

I have some concerns regarding this paper.

1. The introduction doesn't have a related work section

2. The DSP architecture should be better explained, section 2 is very difficult to follow

3. The paper claims some simulation results and 28 nm CMOS implementation. However, the simulation environment is not specified. Also, the 28 nm CMOS solution is only simulated or fabricated? It is not clear.

4. How was the power consumption estimated? 

5. In what environment was the layout from figure 16 generated?

 

 

Author Response

Thank you for your comments. Please refer to the attachment for specific reply.

 

Author Response File: Author Response.pdf

Reviewer 2 Report

The authors have investigated a digital signal processing scheme for PAM-4 Serdes receivers. The data recovery and the adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high-power efficiency have been implemented. Analyses and discussions are interesting and helpful for CMOS communication systems. This paper can be published in Electronics, provided following issues can be addressed.

 

1.     Some abbreviations should be clarified when they appear for the first time.

2.     The affiliations have to be reformatted according to the journal template.

3.     The language can be double-checked and improved, and need to written in American style.

4.     Add some discussion on the performance of the BER in the evaluate system.

5.     Add more discussion regarding the practical limitations of the discussed communication systems

See e.g.

C Jin et al., Nonlinear coherent optical systems in the presence of equalization enhanced phase noise, Journal of Lightwave Technology, 2021.

B Wang et al., Multi-wavelength photonic neuromorphic computing for intra and inter-channel distortion compensations in WDM optical communication systems, IEEE Journal of Selected Topics in Quantum Electronics, 2022.

Author Response

Thank you for your comments. Please refer to the attachment for specific reply.

Author Response File: Author Response.pdf

Reviewer 3 Report

Dear Authors,    

Thank You for so interesting and relevant Article entitled "A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver".

1. The article is written on a relevant topic, well-structured, and logically proven. 

2. The topic is highly original and relevant in the field. 

3. The authors duly describe the subject area compared with other published material. 

4. The authors could consider some minor improvements in the logic of the presentation of the results. I'd suggest describing the topic for future research in a separate section 4. Discussion. The authors could add some paragraphs about the possibility of finding a stable solution.

5. The conclusions are consistent with the evidence and arguments presented. I’d recommend the authors should move table 4 "PAM4 receiver performance comparisons." and Figure 16. "The layout of whole system." from the Conclusion section to the end of Section 4. "Simulation Results". I'd recommend correcting the title of Figure 16 to "The layout of the whole system." (adding the article "the").

6. The references are appropriate.

7. Please disclose the abbreviations "VEC" and "VEOR" in the title of Figure 11. "Trend of VEC and VEOR with attenuation". 

Author Response

Thank you for your comments. Please refer to the attachment for specific reply.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

My concerns have been addressed