Multi-Layer QCA Shift Registers and Wiring Structure for LFSR in Stream Cipher with Low Energy Dissipation in Quantum Nanotechnology

Abstract

Pseudorandom numbers (PRN) are used in various cryptographic applications, such as cryptographic protocols and stream ciphers. The most efficient hardware method used to generate PRNs is to use a Linear Feedback Shift Register (LFSR) structure, which is generally composed of a Shift Register (SR) and an XOR gate. The most important factors in designing the entire LFSR structure are design cost and energy efficiency, which are highly dependent on the SR structure. In the proposed study, the structural characteristics and problems of existing various types of SRs are presented, and new multi-layered serial-in-serial-out (SISO) and parallel-in-parallel-out (PIPO) SRs are proposed. In addition, we compare and analyze the area-time complexity, design cost, and energy dissipation through simulation using QCADesigner and QCADesigner-E. As a result, the proposed SISO and PIPO showed a performance improvement of more than 27% compared to the existing structure, which showed the best performance, and showed energy dissipation reduction rates of about 65% and 59%, respectively. In particular, we proposed multi-layer wiring that can reduce energy dissipation and verified through simulation that it can save up to 24.8%.

1. Introduction

CMOS technology is reaching its physical limits with problems such as short-channel effects, interconnect delays, and high power consumption, and Moore’s Law has also reached its limit [1]. Quantum-Dot Cellular Automata (QCA) is a next-generation quantum circuit design technology that shows improved characteristics in terms of energy efficiency, operation speed, and area compared to previously used digital circuit design technologies. Due to these characteristics, it is considered that QCA can replace the digital circuit design technology represented by conventional CMOS [2,3,4].

Various existing digital circuits have been redesigned into QCA circuits. Most circuits have been designed and improved with an emphasis on reducing circuit area and latency [5,6,7]. In addition to this, research is being conducted to minimize the energy dissipation that occurs during circuit operation and fault tolerance [8,9,10,11,12]. In addition, although various studies are being conducted to improve the energy dissipation of the circuit, a specific method or model for minimizing it is currently not proposed. Most of the recent studies have been carried out in a way to reduce the overall energy loss by reducing the area of the circuit [13,14,15,16]. Currently, the best way to reduce the area is to implement circuits around the existing majority gate using cell interaction [17,18,19].

Existing studies have focused on the calculation part, which is the core of the circuit, and have hardly progressed on the energy loss of wiring, which is indispensable in constructing a circuit. Meanwhile, in this study, the hardware design of the pseudorandom number generator (PRNG), which is widely used in linear cryptography and cryptographic protocols, is mainly implemented by the linear feedback shift register (LFSR) structure. The core principle of stream ciphers is to generate ciphertext through XOR operations with the original text by generating a bit string or character string with a long period [8,20]. Therefore, since the LFSR structure with a long period consists of a long SR structure and a small number of XOR gates, most of the design cost and energy consumption are highly dependent on the SR structure. At this time, the SR is composed of D-latch or Mux [21,22,23,24,25,26,27].

The efficient design of the SR structure, which requires the largest area and latency in the components, is proportional to the efficiency of the entire LFSR structure. This has a high relationship with the energy dissipation rate, which directly affects signal stability and circuit operation. This study also identifies the wiring problem that arises as the number of bits increases in linear structures and determines how much energy consumption can be reduced by solving this problem.

The SR is classified into four types according to the input/output structure designed by function: serial-in parallel-out (SIPO), serial-in serial-out (SISO), parallel-in parallel-out (PIPO), and parallel-in serial-out (PISO) [28,29,30,31,32,33,34,35,36,37,38]. We would like to analyze and discuss three structures except for PISO, which is not often used due to structural reasons. The contributions of this study can be summarized as follows:

• Multi-layered SISO and PIPO QCA circuits using cell interactions are proposed.
• The structure, characteristics, and energy dissipation of SR structures are compared and analyzed.
• Problems with existing SR structures are presented, and ways to increase signal stability through structural improvement are proposed.
• A method for minimizing energy dissipation by changing the wiring structure is proposed.
• The novelty of the proposed research is the easy conversion of serial and parallel input and output in a multi-layer structure and the proposal of a multi-layer wiring technique.
• A modified equation that can calculate the design cost of a QCA circuit including a MUX using cell interaction is proposed.
• The performance and energy dissipation of the proposed structures and existing circuits are simulated and compared using QCADesigner and QCADesigner-E.

This paper is structured as follows: In Section 2, the basic background knowledge of QCA and the existing SR structures is reviewed; in Section 3, we propose SISO and PIPO SRs; and in Section 4, the performance and energy dissipation of existing SRs and the proposed structures are compared and analyzed. In addition, a new wiring structure is proposed, and the relationship between the proposed wiring structure and energy dissipation rate is investigated. Finally, we conclude in Section 5.

2. Related Works

2.1. Background of QCA

One QCA cell is composed of four quantum dots in a square pattern. In addition, the QCA cell state can be divided into a null state in which electrons are not activated, as shown in Figure 1a, and a polarized state in which two electrons in each cell are activated, as shown in Figure 1b [1]. The two electrons have a repulsive force that pushes each other, and this is called Coulomb repulsion. Therefore, as shown in Figure 1c, two states are possible, and cell polarization P = +1 or −1 in standard cells and 45° rotated cells represents “1” or “0” in binary logic [2]. QCA wiring can be made most simply by attaching cells next to QCA cells in order.

$$MV\left(A,B,C\right)=AB+BC+AC$$

(1)

Figure 2a shows a majority vote (MV) gate to represent a logic gate. The logic function of the MV gate is achieved by Equation (1). Therefore, as shown in Figure 2b or Figure 2c, when the input value of C becomes 0 or 1, the MV gates perform AB or A + B operations. Therefore, it can be used as an AND or OR gate. Figure 2d,e show a strong and weak inverter, respectively. In the inverse phase, each state value is changed to the opposite value by the Coulomb repulsive force. Since the output value of a strong inverter is changed by the Coulomb repulsive force of two cells, the signal strength is stronger than that of a weak inverter that is changed by one cell, and the value is transmitted stably [5,6,7].

A QCA cell has four clock states. Locking is a period in which the potential of the cell gradually increases and becomes stronger, Locked is a state in which the potential between quantum dots is maintained high, Relaxing is a period in which the potential gradually decreases and becomes weak, and Relaxed means a state in which all potential is lost. In QCA, these four states constitute one clock cycle, and each clock phase has an interval delay of 90°. Figure 3 shows these four state changes along with clock changes from clock 0 to clock 3. The arrow inside the square box indicates the state change of the corresponding clock phase. These states are also called Switch, Hold, Release and Relax [2,3]. When an input value enters an input cell, neighboring cells are sequentially activated according to the clock state.

The QCA circuit is classified into a coplanar structure composed of only one layer and a multi-layer structure using several layers [19]. Unlike the coplanar structure, the multi-layer structure has a high design complexity because the circuit is designed considering the interaction between the layers. Figure 4a shows the wire crossover of the coplanar structure. Normal cells and cells rotated by 45° do not affect each other’s values when crossing, so they can be used for plane crossing. Figure 4b is a wire crossover of a multi-layer structure using three layers and shows that the value of the other layer is not affected when there is a difference between two or more layers [33,35].

2.2. Previous QCA SR Structure

A SR is a circuit that temporarily stores binary information in storage and transfers information left or right. The n-bit SR is composed of n D-latches and wires, and 1-bit binary information is input to the SR according to a clock input, and the stored information is shifted according to the next clock input. SRs are classified into four types according to the input/output format: SIPO, SISO, PIPO, and PISO. Figure 5 shows the logic diagram of the shift registers, excluding PISO, which is not frequently used.

Figure 6 shows various typical structures on SIPO SR. In 2015, Beigh et al. proposed a 3-bit SR to design a LFSR [28], and Reshi et al. introduced three types of SR [29]. In 2019, Roshan et al. proposed a 4-bit serial SR with a reset function and minimized complexity [30], and in 2021, Ajitha et al. proposed a SR using a 5-input MV gate [31], and Fan et al. proposed serial and parallel SR using a dual edge-triggered D flip-flop [32]. Recently, in 2022, Kim et al. proposed a multi-layered SIPO SR while proposing an LFSR structure for random number generation [33].

Figure 7 shows various typical SISO SRs. In 2015, Reshi et al. introduced three types of SR [29], and in 2017, Das et al. proposed a 3-bit SR under thermal randomness [34]. In 2018, Divshali et al. proposed a multi-layered SR consisting of three different D flip-flops and five layers [35], and Kalyan et al. proposed a 4-bit SR using a JK flip-flop [36]. In 2019, Abdullah-Al-Shaf et al. proposed a SIPO-type SISO SR with a RAM structure [37], and Li et al. proposed a SISO SR with PIPO [38].

Figure 8 shows the existing research on PIPO SR, where both input and output are made in parallel. In 2015, Reshi et al. introduced PIPO SR along with SIPO and SISO structures [29], and in 2019, Li et al. proposed PIPO SR together with SISO structures [38]. Moreover, in 2021, Fan et al. proposed serial and parallel SRs with dual edge-triggered D flip-flops [32].

3. The Proposed Structures

In 2022, our team proposed a multi-layered D-latch to design an efficient LFSR structure and proposed a SIPO SR [33]. The proposed D-latch was designed very simply by cell interaction without using an MV gate. In this section, we show how easily the existing SIPO structure can be converted into SISO and PIPO structures and how superior the modularity and extensibility of the proposed structures are compared to the existing ones. Figure 9 shows a 4-bit SISO SR proposed in this study. The input value D is stored in the D-latch using the multi-layer structure and transmitted to the next D-latch by the CLK input. The proposed SISO SR can be easily implemented by replacing the output cells of layers 1 and 3 of the existing SIPO structure with normal cells.

Figure 10 shows a proposed 4-bit PIPO SR. For parallel input and output, input values D0~D3 and output values OUT0~OUT3 are located in all D-latch. Since each input cell is in a very stable state, it was confirmed that stable signal transmission is possible even though it is composed of only one cell. In addition, it was confirmed that each input value was output in parallel to the corresponding latch on every clock.

As shown in Figure 9 and Figure 10, the proposed SR structures can be converted very easily regardless of the type, and it can be confirmed that each layer of the proposed structure is easily expandable due to its excellent modularity. In addition, the structure using cell interaction does not depend on the operation of the MV gate.

4. Structural Analysis and Simulation

In this section, we compare and analyze the performance along with the structural analysis of existing SR structures.

4.1. Structural Analysis

Since the LFSR structure for calculating a cryptographic random value only needs to add an XOR gate to the SR structure, most of the structure design cost depends on the SR structure. QCADesigner (version 2.0.3) was used to measure the design complexity of SR structures and to measure the accuracy and reliability of operations [39]. The simulation engine used Bistable Approximation, and the values of the simulation parameters are as follows: cell size: 18 nm, dot diameter: 5 nm, cell separation: 2 nm, layer separation: 11.5 nm, clock high: 9.8 × 10⁻²² J, clock low:3.8 × 10⁻²³ J, clock shift: 0, clock amplitude factor: 2.0, relative permittivity: 12.9, Temperature: 1 K, relaxation time: 1.0 × 10⁻¹⁵ s, time step: 1.0 × 10⁻¹⁶ s, and radius of effect: 65 nm.

The method of measuring the cost of QCA circuit design varies according to the basic unit and purpose of the circuit design [40]. There is a problem in that the existing cost measurement method for circuits designed based on MV gates cannot be applied to circuits based on cell interaction. Therefore, in this study, the design cost is calculated using the most basic AT product and the newly proposed cost calculation formula. AT complexity using the product of circuit area and latency is defined as Equation (2).

$$AT complexity=A\times T^p,0\le p\le 2$$

(2)

where A is the area and T is the latency of the QCA circuit. We assume that the value of p is 1 here and calculate and compare the AT complexity for each bit. However, AT complexity cannot measure the complexity of the multi-layer structure, and the design cost formula proposed in [40] cannot measure the MUX using cell interaction. Therefore, in this study, a new design cost calculation formula that complements the problems is proposed as Equation (3).

$$Cost=\left({\left(M_3+F\times M_{C,5}\right)}^k+I+C^l\right)\times T^p$$

(3)

where M₃ is the number of 3-input majority gates, F is the ratio of the number of cells of the cell-interaction-based multiplexer under consideration to the number of cells of the 3-input majority gate, M_C,5 is the number of cell-interaction-based multiplexer or the 5-input majority gate, I is the number of inverters, C is the number of crossovers, and T is the delay of the circuit, and k, l, and p are the exponential weightings for majority gate count, crossover count, and delay, respectively. In the most general case, a double weighting is applied to M and C, which are associated with both complexity and fabrication difficulty, and a double weighting can be given to the delay as well since the demand for speed in recent circuit designs is increasing [40].

Table 1. Performance comparison of QCA SIPO SR.

Circuit	Cell Count	Area (nm2)	Latency (Clock Phase)	AT Comp.	Bits	AT(# of Fixed Inputs)/Bit	Cost/3-Bit	Structure
[28]	147	162,538	12	487,614	3	162,538(3)	11,808	coplanar
[29]	191	174,420	17	741,285	4	185,321(3)	14,703	coplanar
[30]	92	68,724	15	257,715	4	64,429(2)	6273	coplanar
[31]	160	132,404	8	264,808	4	66,202(2)	2298	coplanar
[32]	161	204,978	24	1,229,868	3	409,956(4)	121,167	coplanar
[33]	80	33,124	3	24,843	4	6210(2)	548	multi-layer

compares the performance of the previously introduced SIPO SRs in Section 2. The SIPO SRs in references [28,29] are typical majority gate-based structures, and D flip-flops are constructed using majority gates and turning wires. The three SR structures proposed in [29] do not normally output result values because they are not composed of two or more cells in one clock phase. Ref. [30] uses a D-latch based on cell interaction to confirm that the AT complexity is reduced by about 60 to 65% and the cost by 47 to 57% compared to the existing MV gate-based SR.

The structure of [31] uses a 5-input MV gate and reduces the number of MVs and the clock phase; therefore, it has a very low AT complexity and a design cost that is more than 63% lower than that of [30]. The structure of [32] is a circuit designed to emphasize the functional aspect rather than structural characteristics by designing a dual edge-triggered D flip-flop; therefore, the design cost is very high. However, it has the advantage that both negative and positive triggers are possible. SRs with a multi-layer structure and a D-latch based on cell interaction were introduced in [33] and minimized the AT complexity and the design cost of existing coplanar SIPO SRs by approximately 90% and 76%, respectively.

Table 2. Performance comparison of QCA SISO SR.

Circuit	Cell Count	Area (nm2)	Latency (Clock Phase)	AT Comp.	Bits	AT(# of Fixed Inputs)/Bit	Cost/3-Bit	Structure
[29]	191	174,420	17	741,285	4	185,321(3)	14,703	coplanar
[34]	100	80,500	12	241,500	3	80,500(3)	12,096	coplanar
[35]	120	28,124	12	84,372	3	28,124(3)	15,696	multi-layer
[36]	226	182,684	4	182,684	4	45,671(2)	1377	coplanar
[37]	128	108,564	12	325,692	3	108,564(3)	21,168	coplanar
[38]	105	134,922	11	371,036	3	123,679(3)	10,164	coplanar
Ours	80	33,124	15	124,215	4	31,054(2)	7362	multi-layer

compares the performance of the proposed structure and the existing QCA SISO SR. The SISO SR presented in [29] has the same performance value as the SIPO SR described above, with the same structure except for the output cell part. The SR in [34] has the same form as SIPO structurally; however, it is serially output through the clock control of CLK. Ref. [35] proposed three different D flip-flops and designed them to operate in five multi-layer structures. By reducing the area, the AT complexity was reduced by 65% compared to existing coplanar structures; however, the cost was reduced by only about 18%. This is because the spatial design complexity of the multi-layer structure was considered.

Most existing SR structures used D flip-flops; however, the structure proposed in [36] was designed using a JK flip-flop, and this structure minimized latency by using one clock phase for processing one bit. However, one clock phase has to process too many cells, and the CLK input is not properly routed throughout the circuit; therefore, it does not work accurately. The SISO structures proposed in [37,38] are also MV gate-based SR structures with no particular differences, but they are composed of only one cell in one clock phase, or the space between cells is too narrow; therefore, signals are transmitted very unstable. However, the SISO structure proposed in this study can reduce the design cost by more than 53% compared to the multi-layer structure of [35] and can reduce the design cost by 27% compared to the structure of [38], which has the lowest design cost among the SISO SRs that operate properly.

Table 3. Performance comparison of QCA PIPO SR.

Circuit	Cell Count	Area (nm2)	Latency (Clock Phase)	AT Comp.	Bits	AT(# of Fixed Inputs)/Bit	Cost/3-Bit	Structure
[29]	173	153,640	5	192,050	4	48,013(3)	2175	coplanar
[38]	115	92,204	3	69,153	3	23,051(3)	756	coplanar
[32]	177	149,702	8	299,404	3	99,801(4)	13,463	coplanar
Ours	81	38,491	3	28,868	4	7217(2)	548	multi-layer

shows the performance comparison of QCA PIPO SRs. The PIPO structure has the advantage of very low AT complexity and design cost because it has low latency and fast output compared to other SR structures. The proposed PIPO structure compared AT complexity and cost with the structure of [38], which shows the best performance among existing PIPO SRs, and confirmed that it was reduced by more than 68% and 27%, respectively.

Figure 11 shows the simulation results of the proposed SISO and PIPO SRs. As shown in Figure 11a, it was confirmed that the result outputs a stable value with the input value as it is after 3.75 clock cycles. Figure 11b confirms that the input values from D0 to D3 designated through the vector table are output normally after 0.75 clock cycles. It can be seen that the proposed structures have a very stable signal of −9.86× 10⁻¹ J ≤ OUT ≤ 9.87× 10⁻¹ J.

4.2. Characteristic Analysis

Table 4. Comparison of characteristics of QCA SR.

Circuit	Feature	Pros	Cons
[28]	- week Inverter	- high modularity	- high AT complexity
[29]	- 45° rotated cell	- no inverter	- high AT complexity
[30]	- cell-interaction based D-latch	- low area	- high latency
[31]	- 5-input MV gate	- low latency	- no CLK input
[32]	- dual edge-triggered D F/F	- positive and negative triggering	- low scalability
[33]	- multi-layer structure (3-layer)	- minimized AT complexity	- high design complexity
[34]	- week Inverter	- low cell count	- forced control of CLK clocks
[35]	- multi-layer structure (5-layer) - Three types of D F/F	- minimized area	- high design complexity - low scalability
[36]	- JK F/F	- minimized latency	- CLK routing problem
[37]	- week Inverter	- available as SISO and SIPO	- forced control of the output
[38]	- week Inverter	- low design cost	- low signal stability
Ours	- multi-layer structure (3-layer)	- high scalability and signal stability - low AT complexity and design cost	- high design complexity

shows an analysis of the characteristics, strengths, and weaknesses of existing studies. In many papers, a weak inverter was used to reduce the area, and a 45° rotated cell was used instead of the inverter [29]. There have been many efforts to reduce the design cost by designing a D-latch based on cell interaction instead of the typical MV gate [30,32,33]. Ref. [31] uses a 5-input majority gate to have low latency; however, it needs to be redesigned by adding a CLK input. It is possible to have low AT complexity and design cost by designing a three-dimensional spatial SR structure that is composed of several multi-layer structures and breaking away from the coplanar limitations [33,35]. In Ref. [34], the circuit was designed based on the MV gate using at least cells, but forced control is required because there are many outputs. There has been a study to minimize latency by using the JK flip-flop instead of the D flip-flop, but the circuit does not work properly due to CLK routing problems [36]. Ref. [37] showed a circuit that can be used with both SIPO and SISO according to the adjustment of the output; however, there is a problem that the output must be forcibly adjusted. The structure of [38], which claims a very low design cost, makes it difficult to obtain stable results due to low signal stability. The proposed SISO and PIPO SRs can be easily modified from the previously proposed SIPO in [33] and have the lowest design cost compared to the existing SRs that operate accurately and output very stable signals.

5. Energy Dissipation Analysis

In order to find the energy dissipation and polarization of the QCA cell, a quantum mechanical calculation obtained by a Hamiltonian matrix is required. The Hamiltonian matrix using the Hartree-Fock approximation is used to calculate the energy analysis of QCA cells [41,42,43]. The Hamiltonian expression is as in Equation (4).

$$H=\left[\begin{array}{cc}-\frac{1}{2}{\displaystyle \sum _i}{E}_k{P}_i{f}_i& -\gamma \\ -\gamma & \frac{1}{2}{\displaystyle \sum _i}{E}_k{P}_i{f}_i\end{array}\right]=\left[\begin{array}{cc}-\frac{1}{2}{E}_k\stackrel{-}{P}& -\gamma \\ -\gamma & \frac{1}{2}{E}_k\stackrel{-}{P}\end{array}\right]$$

(4)

where the sums are over the cells in the local neighborhood. $E_k$ is the “kink energy” or the energy cost of two neighboring cells having opposite polarizations. $f_i$ is the geometric factor capturing electrostatic fall off with distance between cells. $P_i$ is the polarization of the $\mathcal{i}$-th cell. And, $\gamma$ is the tunneling energy between two cell states, which is controlled by the clocking mechanism [43]. The notation can be further simplified by using $\stackrel{-}{P}$ to denote the weighted sum of the neighborhood polarizations ${\sum }_i{P}_i{f}_i$. From the above Equation (4), we can use the term $\left(P_{diss}\right)$ which represents the instantaneous energy dissipated as shown in the following Equation (5).

$$P_{diss}\left(t\right)=\frac{\stackrel{-}{h}}{2}\overrightarrow{\mathsf{\Gamma }}\left(t\right)\cdot \left(\frac{d}{dt}\overrightarrow{\lambda }\left(t\right)\right)$$

(5)

where $\overrightarrow{\lambda }$ us the coherence vector and $\overrightarrow{\mathsf{\Gamma }}$ is the three-dimensional energy vector [23].

In this section, energy dissipation for the various SR structures introduced above is analyzed. For equal comparison, all SR structures are set to three bits, and energy dissipation is focused regardless of whether the proposed structure operates. To measure them, the QCADesigner-E [44] tool was used. This application for estimating the power dissipation of QCA circuits is based on the previous studies [41,42,43]. The simulation engine used a coherence vector with energy, and the values of the simulation parameters are as follows: cell size; 18 nm, dot diameter; 5 nm, cell separation; 2 nm, layer separation-11.5 nm, clock high; 9.8 × 10⁻²² J, clock low; 3.8 × 10⁻²³ J, clock shift; 0, clock amplitude factor; 2.0, relative permittivity 12.9, temperature; 1 K, relaxation time; 1.0 × 10⁻¹⁵ s, clock/input period; 4.0 × 10⁻¹² s, time step; 1.0 × 10⁻¹⁶ s, clock slope; 1.0 × 10⁻¹² s and radius of effect; 80 nm, relative permittivity: 12.9, layer separation 11.5 nm.

Table 5. Energy dissipation comparison of QCA 3-bit SR structure.

Energy Dissi.	STR.	[28]	[29]	[30]	[31]	[32]	[33]	[34]	[35]	[36]	[37]	[38]	Ours
Total (10−2 eV)	SIPO	6.08 (4.91)	4.89 (4.18)	2.62 (1.97)	3.93	3.09	1.25
	SISO		5.04 (4.11)					4.09 (4.13)	3.56	5.32 (5.14)	5.32 (4.57)	5.23	1.25
	PIPO		5.03 (4.04)			3.88 (3.87)						6.94 (7.01)	1.59
Average per cycle (10−3 eV)	SIPO	5.52 (4.46)	4.45 (3.80)	2.38 (1.79)	3.57	2.81	1.14
	SISO		4.58 (3.74)					3.72 (3.75)	3.23	4.84 (4.68)	4.84 (4.16)	4.76	1.13
	PIPO		4.57 (3.67)			3.53 (3.52)						6.31 (6.37)	1.44

is a table summarizing the energy dissipation of the existing SR structures discussed above. For spatial reasons, error rates are not indicated. Overall, it is generally true that the design cost of the circuit and the energy dissipation value are directly proportional; however, the structure in [32] has a relatively low energy dissipation value despite the high design cost. It has a long latency, but the length of each clock phase is short; therefore, it is judged that there is no large energy dissipation. The structure in [36] has a relatively high energy dissipation value despite having a very low design cost. This resulted in the dissipation of a lot of energy by processing too many cells in one clock phase. The proposed SISO has the lowest value of energy dissipation as well as the lowest existing structural complexity and design cost. This shows that if the multi-layer structure is designed efficiently, it is very effective in terms of overall circuit design cost and energy efficiency.

As seen in the previous experimental results, it can be confirmed that a short clock phase creates a long latency but is effective for energy loss. Conversely, a long clock phase not only causes large energy dissipation but also does not operate normally. Therefore, in this study, we would like to suggest an efficient way to reduce energy dissipation without increasing latency. In a circuit that is long according to the number of bits, such as the SR structure, many structures have a long CLK input wire. Such long input wiring not only causes signal instability but also has a lot of energy dissipation. Therefore, the long planar wiring is changed to a multi-layered wiring consisting of two layers. Figure 12 shows the CLK multi-layer input wiring consisting of lower and upper layers.

This prevents continuous energy dissipation that can occur in long planar wires by changing the potential energy of electrons in the cell and giving stability to the signal. The values in parentheses in Table 5 represent the energy dissipation of the modified circuit with multi-layered wiring. Among the circuits designed in a coplanar structure, when all the circuits with long CLK input wires were modified with multi-layer wiring and tested, most of the normal circuits showed improved results. The structure in [30] could lower the energy dissipation by up to 24.8% by moving only 6 cells to the upper layer. On the other hand, it is difficult to reduce energy dissipation when the CLK input changes to multiple clock phases, as in [34], and when there are problems with clock routing and signal instability, as in [32,36,38]. The summary of energy dissipation reduction using multi-layer wiring is as follows:

• It is useful for circuits with long single-clock phase wiring, such as SR structure clock input.
• Effective for circuits with longer wiring due to circuit expansion or relatively long wiring compared to the overall circuit size.
• Do not use it in the corner of the circuit or in the section where the clock phase changes, as it may cause problems with the overall operation of the circuit and signal stability.
• Circuits designed with existing multi-layer structures should be used carefully, considering inter-layer interference.

It is clear that the proposed multi-layer wiring technique helps maintain the clock and signal status of long input wiring. However, additional experiments and confirmation are needed to determine whether a stable condition can be guaranteed for a much longer wire, and another alternative is needed to ensure the stability of clocks and signals, and continuous research on this is required.

6. Conclusions

The efficiency and stability of the LFSR structure, which is the most basic hardware implementation of stream ciphers, are highly proportional to the effective design of the SR structure. Therefore, we focused on the SR structure, which occupies most of the design cost of the LFSR structure. The proposed study designed the circuit considering design cost, signal stability, and energy dissipation. The proposed multi-layer structured SRs are verified to be the most efficient in all parts compared to the existing SR structures. On the other hand, multi-layer wiring that can replace the single-layer wiring of a long single clock was proposed. If the single-clock wiring, which inevitably gets longer as the number of bits increases, is changed to a multi-layer structure, the wiring itself can have an amplification effect, preventing not only energy loss but also serious problems that can cause operational errors. As a result, this study proposed a structure and wiring that can minimize design cost and energy dissipation and verified its effect and performance. In the next study, various experiments and verifications will be conducted to determine how multi-layer wiring can be used well in a multi-layer structure and the length of single-clock wiring that can overcome signal stability.