A Novel Buck Converter with Dual Loops Control Mechanism
Abstract
:1. Introduction
2. Proposed Control Topology and Circuit Realization
2.1. Proposed Control Topology
- (A)
- Constant Frequency Mechanism:
- (B)
- Proposed adaptive TOFF controller:
- (C)
- Proposed adaptive TON controller:
- (D)
- EA (Error Amplifier)
- (E)
- DRIVER:
- Advantages
- (A)
- The scheme does not need to design a complex sensing circuit to sense the inductor current at any time. Compared with the scheme of using the current sensor [2], the proposed scheme is easy to implement and suitable for mass production.
- (B)
- The whole control circuit does not require special semiconductor devices, and there is no special matching issue in layout.
- (C)
- By the “constant frequency mechanism” module, the proposed scheme can make the switching frequency constant, which greatly reduces the difficulty in solving EMI issue. Moreover, the “constant frequency mechanism” is easy to implement, instead of PLL [31].
- Disadvantages
- (A)
- In contrast to SC converter, the scheme cannot be fully integrated into silicon.
2.2. Circuit Realization and Operating Principle
- The switch S1 turns ON, and the switch S2 turns OFF. In this state, the inductor is in the charging phase. The ON time of S1 is labeled as TON. The TON is determined by the “proposed adaptive TON controller” module. When S1 is ON, the Vramp begins to rise toward the VCMP. Once the Vramp reaches the VCMP, the S1 is turned OFF, and the S2 is turned ON.
- The switch S1 turns OFF, and the switch S2 turns ON. In this state, the inductor is in the discharging phase. The OFF time of S1 is labeled as TOFF. The TOFF is determined by the “proposed adaptive TOFF controller” module.
- The “constant frequency mechanism” works to detect the switching frequency. The VEA1 controls the “proposed adaptive TOFF controller” to decide TOFF [31].
- In the steady state, the VFB and the Vfreq are almost equal to the VREF and the VREF2, respectively. In other words, the VCMP and the VEA1 will eventually converge to their stable voltages. The key waveforms of the converter are drawn in Figure 4.
3. Theoretical Analysis
3.1. Mathematical Model
3.2. Component Selection
4. Simulation Results
4.1. SIMPLIS Schematic
4.2. Transient Performance
4.3. Load Regulation
4.4. Line Regulation
4.5. Switching Frequency Regulation
- (A)
- Conversion step:
- (B)
- Regulation step:
4.6. Performance List
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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Component | Value | Unit |
---|---|---|
RLOAD | 3.6 | Ω |
Co | 10 | μF |
L | 4.7 | μH |
RESR | 5 | mΩ |
Ro | 1 | MΩ |
R3 | 180 | kΩ |
C1 | 200 | pF |
Parameter | Conditions | Min. | Typ. | Max. | Unit |
---|---|---|---|---|---|
Input voltage | 3.0 | 3.6 | V | ||
Output voltage | 1.0 | 2.5 | V | ||
Output ripple | Vin = 3.6 V, Vo = 2.5 V | 2.7 | mV | ||
Load current | 100 | 500 | mA | ||
Inductor | DCR *: 30 mΩ | 4.7 | μH | ||
Output capacitor | ESR: 5 mΩ | 10 | μF | ||
Switching frequency | Vin = 3.0~3.6 V, Vo = 1.0~2.5 V | 1 | MHz | ||
Recovery time (step-up) | Vo = 1.8 V Load current: 100 mA to 500 mA | 1.5 | μs | ||
Recovery time (step-down) | Vo = 1.8 V Load current: 500 mA to 100 mA | 0.9 | μs | ||
Overshoot voltage | Vin = 3.3 V, Vo = 1.8 V | 16 | mV | ||
Undershoot voltage | Vin = 3.3 V, Vo = 1.8 V | 12 | mV |
References | 2018 [36] | 2020 [37] | 2021 [30] | 2021 [31] | This Work |
---|---|---|---|---|---|
Results | simulation | simulation | simulation | simulation | simulation |
Control scheme | AOT | AOT | AOT | AOT | dual loops |
Process (μm) | 0.35 | 0.18 | 0.35 ** | 0.18 ** | 0.35 ** |
Input voltage (V) | 12 | 3.3–5.0 | 3.0–3.6 | 3.0–3.6 | 3.0–3.6 |
Output voltage (V) | 1.2 | 1.8 | 1.0–2.5 | 1.0–2.5 | 1.0–2.5 |
Inductor (μH) | 1 | 1.5 | 4.7 | 4.7 | 4.7 |
Output Capacitor (μF) | 47 | 20 | 10 | 10 | 10 |
Switching Frequency (MHz) | 1 | 1 | 1 | 1 | 1 |
Switching frequency variation (%) | N/A | N/A | N/A | <1% | <1% |
Max. Load current (mA) | 5000 | 2000 | 500 | 500 | 500 |
Load current step (mA) | 4000 | 800 | 400 | 400 | 400 |
Undershoot/Overshoot (mV) | 20/26 | 13/14 | 23/26 | 20/24 | 16/12 |
Recovery time (μs) (rise/fall) | <3 | 6/2 | 1.98/1.6 | 1.69/1.62 | 1.5/0.9 |
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Chou, H.-H.; Luo, W.-H.; Chen, H.-L.; Wang, S.-F. A Novel Buck Converter with Dual Loops Control Mechanism. Electronics 2022, 11, 1256. https://doi.org/10.3390/electronics11081256
Chou H-H, Luo W-H, Chen H-L, Wang S-F. A Novel Buck Converter with Dual Loops Control Mechanism. Electronics. 2022; 11(8):1256. https://doi.org/10.3390/electronics11081256
Chicago/Turabian StyleChou, Hsiao-Hsing, Wen-Hao Luo, Hsin-Liang Chen, and San-Fu Wang. 2022. "A Novel Buck Converter with Dual Loops Control Mechanism" Electronics 11, no. 8: 1256. https://doi.org/10.3390/electronics11081256
APA StyleChou, H.-H., Luo, W.-H., Chen, H.-L., & Wang, S.-F. (2022). A Novel Buck Converter with Dual Loops Control Mechanism. Electronics, 11(8), 1256. https://doi.org/10.3390/electronics11081256